| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterCoalescer.h | 37 unsigned DstIdx = 0; member in class:llvm::CoalescerPair
101 unsigned getDstIdx() const { return DstIdx; }
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| H A D | TwoAddressInstructionPass.cpp | 136 bool commuteInstruction(MachineInstr *MI, unsigned DstIdx,
156 unsigned SrcIdx, unsigned DstIdx,
681 unsigned DstIdx,
702 Register RegA = MI->getOperand(DstIdx).getReg();
1271 unsigned SrcIdx, unsigned DstIdx,
1277 Register regA = MI.getOperand(DstIdx).getReg();
1287 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist);
1468 unsigned DstIdx = 0; local
1469 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1473 MachineOperand &DstMO = MI->getOperand(DstIdx);
680 commuteInstruction(MachineInstr *MI, unsigned DstIdx, unsigned RegBIdx, unsigned RegCIdx, unsigned Dist) argument
1269 tryInstructionTransform(MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi, unsigned SrcIdx, unsigned DstIdx, unsigned Dist, bool shouldOnlyCommute) argument
1519 unsigned DstIdx = TiedPairs[tpi].second; local
1741 unsigned DstIdx = TiedPairs[0].second; local
[all...] |
| H A D | RegisterCoalescer.cpp | 244 unsigned DstIdx);
428 SrcIdx = DstIdx = 0;
475 SrcIdx, DstIdx);
484 DstIdx = SrcSub;
497 if (DstIdx && !SrcIdx) {
499 std::swap(SrcIdx, DstIdx);
518 std::swap(SrcIdx, DstIdx);
542 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
557 TRI.composeSubRegIndices(DstIdx, DstSub);
1240 unsigned DstIdx local
1800 unsigned DstIdx = CP.getDstIdx(); local
3374 unsigned DstIdx = CP.getDstIdx(); local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIAddIMGInit.cpp | 98 int DstIdx = local
127 RI->getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32;
133 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx));
151 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx));
171 MI.tieOperands(DstIdx, MI.getNumOperands() - 1);
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| H A D | R600ExpandSpecialInstrs.cpp | 98 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); local
99 assert(DstIdx != -1);
100 MachineOperand &DstOp = MI.getOperand(DstIdx);
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| H A D | R600Packetizer.cpp | 89 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); local
90 if (DstIdx == -1) {
93 Register Dst = BI->getOperand(DstIdx).getReg();
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| H A D | SIPeepholeSDWA.cpp | 403 auto DstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), local
405 auto TiedIdx = MI.findTiedOperandIdx(DstIdx);
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| H A D | SIInstrInfo.cpp | 3316 int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst);
3318 const int OpIndicies[] = { DstIdx, Src0Idx, Src1Idx, Src2Idx };
3352 if (!ST.hasSDWASdst() && DstIdx != -1) {
3354 const MachineOperand &Dst = MI.getOperand(DstIdx);
3379 const MachineOperand &Dst = MI.getOperand(DstIdx);
3386 MI.getOperand(MI.findTiedOperandIdx(DstIdx));
3420 const uint32_t DstIdx =
3422 const MachineOperand &Dst = MI.getOperand(DstIdx);
3424 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx);
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| H A D | R600ISelLowering.cpp | 304 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); local
305 assert(DstIdx != -1);
309 if (!MRI.use_empty(MI.getOperand(DstIdx).getReg()) ||
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| /freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGNonTrivialStruct.cpp | 33 enum { DstIdx = 0, SrcIdx = 1 }; enumerator in enum:__anon369::__anon370
348 Address DstAddr = StartAddrs[DstIdx];
379 CGF.Builder.CreateICmpEQ(PHIs[DstIdx], DstArrayEnd, "done");
516 Address DstAddr = this->getAddrWithOffset(Addrs[DstIdx], this->Start);
548 Address DstAddr = this->getAddrWithOffset(Addrs[DstIdx], Offset);
558 Address DstAddr = this->CGF->Builder.CreateBitCast(Addrs[DstIdx], Ty);
589 *CGF, getAddrWithOffset(Addrs[DstIdx], CurStructOffset, FD), QT);
595 *CGF, getAddrWithOffset(Addrs[DstIdx], CurStructOffset, FD), QT);
601 CGF->MakeAddrLValue(getAddrWithOffset(Addrs[DstIdx], Offset), FT));
630 getAddrWithOffset(Addrs[DstIdx], CurStructOffse
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3406 unsigned DstIdx = 0; // Low bits of the result. local
3408 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
3409 DstRegs[DstIdx] = FactorSum;
3414 for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
3415 // Collect low parts of muls for DstIdx.
3416 for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2894 const int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst); local
2895 if (DstIdx == -1 ||
2896 Desc.getOperandConstraint(DstIdx, MCOI::EARLY_CLOBBER) == -1) {
2906 assert(DstIdx != -1);
2907 const MCOperand &Dst = Inst.getOperand(DstIdx);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 1632 unsigned DstIdx = (Imm >> 4) & 3; variable
1637 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
1639 unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
4742 unsigned DstIdx = (Imm >> 4) & 3; local
4750 unsigned NewImm = (DstIdx << 4) | ZMask;
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| H A D | X86ISelLowering.cpp | [all...] |