Searched refs:DefR (Results 1 - 7 of 7) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp635 RegisterSubReg DefR(MD);
636 assert(Register::isVirtualRegister(DefR.Reg));
641 if (DefR.SubReg) {
643 const LatticeCell &T = Cells.get(DefR.Reg);
645 Cells.update(DefR.Reg, Bottom);
647 visitUsesOf(DefR.Reg);
651 LatticeCell DefC = Cells.get(DefR.Reg);
678 Cells.update(DefR.Reg, DefC);
683 visitUsesOf(DefR.Reg);
705 RegisterSubReg DefR(M
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H A DHexagonGenMux.cpp108 unsigned DefR, PredR; member in struct:__anon2248::HexagonGenMux::MuxInfo
115 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1),
343 auto NewMux = BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR)
H A DHexagonEarlyIfConv.cpp441 Register DefR = MI.getOperand(0).getReg();
442 if (isPredicate(DefR))
993 Register DefR = PN->getOperand(0).getReg(); local
1000 const TargetRegisterClass *RC = MRI->getRegClass(DefR);
1005 MRI->replaceRegWith(DefR, NewR);
H A DHexagonOptAddrMode.cpp97 bool analyzeUses(unsigned DefR, const NodeList &UNodeList,
728 Register DefR = MI->getOperand(0).getReg(); local
733 if (!analyzeUses(DefR, UNodeList, InstrEvalResult, SizeInc))
757 if (op.isReg() && op.isUse() && DefR == op.getReg())
761 // This could happen, for example, when DefR = R4, but the used
H A DHexagonConstExtenders.cpp1529 llvm::Register DefR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); local
1542 // DefR = PS_fi Rb,##EV
1543 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::PS_fi), DefR)
1549 // DefR = ##EV
1550 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_tfrsi), DefR)
1554 // DefR = sub(##EV,Rb)
1555 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR)
1559 // DefR = add(Rb,##EV)
1560 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR)
1567 // DefR
1906 Register DefR = insertInitializer(Q.first, P.first); local
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H A DHexagonBitSimplify.cpp1221 Register DefR = UseI.getOperand(0).getReg();
1222 if (!Register::isVirtualRegister(DefR))
1224 Pending.push_back(DefR);
2919 unsigned DefR;
2926 bool isBitShuffle(const MachineInstr *MI, unsigned DefR) const;
2927 bool isStoreInput(const MachineInstr *MI, unsigned DefR) const;
2945 DefR = HexagonLoopRescheduling::getDefReg(&P);
2980 unsigned DefR) const {
3134 dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi("
3162 unsigned DefR
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H A DHexagonBitTracker.cpp963 if (unsigned DefR = getUniqueDefVReg(MI)) {
964 if (MRI.getRegClass(DefR) == &Hexagon::PredRegsRegClass) {
965 BT::RegisterRef PD(DefR, 0);
968 RegisterCell RC = RegisterCell::self(DefR, RW);

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