Searched refs:DefOp (Results 1 - 9 of 9) sorted by relevance
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineTraceMetrics.cpp | 629 unsigned DefOp; 632 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) 633 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} 642 DefOp = DefI.getOperandNo(); 742 for (unsigned DefOp : LiveDefOps) { 743 for (MCRegUnitIterator Units(UseMI->getOperand(DefOp).getReg(), TRI); 747 LRU.Op = DefOp; 805 .computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI, Dep.UseOp); 959 UseHeight += SchedModel.computeOperandLatency(Dep.DefMI, Dep.DefOp, [all...] |
H A D | PeepholeOptimizer.cpp | 1521 MachineOperand &DefOp = MI.getOperand(0); 1522 if (!isVirtualRegisterOperand(DefOp)) 1534 return findTargetRecurrence(DefOp.getReg(), TargetRegs, RC); 1540 return findTargetRecurrence(DefOp.getReg(), TargetRegs, RC); 1839 const MachineOperand DefOp = Def->getOperand(DefIdx); local 1840 if (DefOp.getSubReg() != DefSubReg) 1868 for (const MachineInstr &UseMI : MRI.use_nodbg_instructions(DefOp.getReg())) {
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H A D | SplitKit.cpp | 439 for (const MachineOperand &DefOp : DefMI->defs()) { 440 Register R = DefOp.getReg(); 443 if (unsigned SR = DefOp.getSubReg())
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H A D | MachinePipeliner.cpp | 353 MachineOperand &DefOp = PI.getOperand(0); local 354 assert(DefOp.getSubReg() == 0); 355 auto *RC = MRI.getRegClass(DefOp.getReg());
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | MachineTraceMetrics.h | 335 void addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonExpandCondsets.cpp | 224 void predicateAt(const MachineOperand &DefOp, MachineInstr &MI, 854 void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp, argument 885 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg());
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86DomainReassignment.cpp | 592 for (auto &DefOp : UseMI.defs()) { 593 if (!DefOp.isReg()) 596 Register DefReg = DefOp.getReg();
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H A D | X86SpeculativeLoadHardening.cpp | 1593 if (MachineOperand *DefOp = MI.findRegisterDefOperand(X86::EFLAGS)) { 1595 if (DefOp->isDead()) 2334 auto &DefOp = MI.getOperand(0); local 2335 Register OldDefReg = DefOp.getReg(); 2342 DefOp.setReg(UnhardenedReg);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.cpp | 629 MachineOperand &DefOp = Def->getOperand(1); local 630 assert(DefOp.isReg() || DefOp.isImm()); 632 if (DefOp.isReg()) { 637 if (I->modifiesRegister(DefOp.getReg(), &RI)) 643 DefOp.setIsKill(false); 647 .add(DefOp);
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