Lines Matching refs:DefOp
629 unsigned DefOp;
632 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp)
633 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {}
642 DefOp = DefI.getOperandNo();
742 for (unsigned DefOp : LiveDefOps) {
743 for (MCRegUnitIterator Units(UseMI->getOperand(DefOp).getReg(), TRI);
747 LRU.Op = DefOp;
805 .computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI, Dep.UseOp);
959 UseHeight += SchedModel.computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI,
975 /// Assuming that the virtual register defined by DefMI:DefOp was used by
979 addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
982 unsigned Reg = DefMI->getOperand(DefOp).getReg();
1086 addLiveIns(Deps.front().DefMI, Deps.front().DefOp, Stack);
1119 addLiveIns(Dep.DefMI, Dep.DefOp, Stack);
1191 DepCycle += TE.MTM.SchedModel.computeOperandLatency(Dep.DefMI, Dep.DefOp,