Searched refs:DAG (Results 1 - 25 of 146) sorted by relevance

123456

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp25 static SDValue emitMemMem(SelectionDAG &DAG, const SDLoc &DL, unsigned Sequence, argument
41 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src,
42 DAG.getConstant(Size, DL, PtrVT),
43 DAG.getConstant(Size / 256, DL, PtrVT));
44 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src,
45 DAG.getConstant(Size, DL, PtrVT));
49 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src,
56 return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP,
64 static SDValue memsetStore(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, argument
70 return DAG
48 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool IsVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
75 EmitTargetCodeForMemset( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Byte, SDValue Size, unsigned Align, bool IsVolatile, MachinePointerInfo DstPtrInfo) const argument
145 emitCLC(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, SDValue Src2, uint64_t Size) argument
169 addIPMSequence(const SDLoc &DL, SDValue CCReg, SelectionDAG &DAG) argument
179 EmitTargetCodeForMemcmp( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
194 EmitTargetCodeForMemchr( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src, SDValue Char, SDValue Length, MachinePointerInfo SrcPtrInfo) const argument
220 EmitTargetCodeForStrcpy( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dest, SDValue Src, MachinePointerInfo DestPtrInfo, MachinePointerInfo SrcPtrInfo, bool isStpcpy) const argument
230 EmitTargetCodeForStrcmp( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, SDValue Src2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
248 getBoundedStrlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src, SDValue Limit) argument
261 EmitTargetCodeForStrlen( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src, MachinePointerInfo SrcPtrInfo) const argument
268 EmitTargetCodeForStrnlen( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src, SDValue MaxLength, MachinePointerInfo SrcPtrInfo) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.h1 //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
10 /// R600 DAG Lowering interface definition
35 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
39 SelectionDAG &DAG) const override;
44 const SDLoc &DL, SelectionDAG &DAG,
50 const SelectionDAG &DAG) const override;
63 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
68 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG,
70 SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
72 SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) cons
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H A DAMDGPUISelLowering.cpp1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
51 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) { argument
53 KnownBits Known = DAG.computeKnownBits(Op);
57 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) { argument
62 return VT.getSizeInBits() - DAG.ComputeNumSignBits(Op);
674 const SelectionDAG &DAG,
689 return allowsMemoryAccessForAlignment(*DAG.getContext(), DAG.getDataLayout(),
1021 const SDLoc &DL, SelectionDAG &DAG) const {
1025 return DAG
673 isLoadBitCastBeneficial(EVT LoadTy, EVT CastTy, const SelectionDAG &DAG, const MachineMemOperand &MMO) const argument
1043 addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const argument
1083 SelectionDAG &DAG = CLI.DAG; local
1126 Op->print(errs(), &DAG); local
1526 LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool Sign) const argument
1635 LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl<SDValue> &Results) const argument
2064 extractF64Exponent(SDValue Hi, const SDLoc &SL, SelectionDAG &DAG) argument
2291 LowerFLOG(SDValue Op, SelectionDAG &DAG, double Log2BaseInverted) const argument
2396 LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const argument
2481 LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const argument
2581 LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const argument
2782 isU24(SDValue Op, SelectionDAG &DAG) argument
2786 isI24(SDValue Op, SelectionDAG &DAG) argument
2795 SelectionDAG &DAG = DCI.DAG; local
2831 constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset, uint32_t Width, const SDLoc &DL) argument
2884 SelectionDAG &DAG = DCI.DAG; local
2941 SelectionDAG &DAG = DCI.DAG; local
2987 SelectionDAG &DAG = DCI.DAG; local
3026 SelectionDAG &DAG = DCI.DAG; local
3059 SelectionDAG &DAG = DCI.DAG; local
3157 SelectionDAG &DAG = DCI.DAG; local
3200 SelectionDAG &DAG = DCI.DAG; local
3286 getMul24(SelectionDAG &DAG, const SDLoc &SL, SDValue N0, SDValue N1, unsigned Size, bool Signed) argument
3403 SelectionDAG &DAG = DCI.DAG; local
3430 getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const argument
3498 SelectionDAG &DAG = DCI.DAG; local
3516 SelectionDAG &DAG = DCI.DAG; local
3592 SelectionDAG &DAG = DCI.DAG; local
3665 SelectionDAG &DAG = DCI.DAG; local
3867 SelectionDAG &DAG = DCI.DAG; local
3904 SelectionDAG &DAG = DCI.DAG; local
4118 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT, const SDLoc &SL, bool RawReg) const argument
4154 loadStackInputValue(SelectionDAG &DAG, EVT VT, const SDLoc &SL, int64_t Offset) const argument
4170 storeStackInputValue(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue ArgVal, int64_t Offset) const argument
4184 loadInputValue(SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) const argument
4385 getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const argument
4403 getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const argument
4424 computeKnownBitsForTargetNode( const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
4568 ComputeNumSignBitsForTargetNode( SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
4610 isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN, unsigned Depth) const argument
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H A DSIISelLowering.h1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
10 /// SI DAG Lowering interface definition
40 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
42 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
43 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
48 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
51 SDValue getPreloadedValue(SelectionDAG &DAG,
57 SelectionDAG &DAG) const override;
58 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
61 SelectionDAG &DAG) cons
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblySelectionDAGInfo.cpp22 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src,
25 if (!DAG.getMachineFunction()
30 SDValue MemIdx = DAG.getConstant(0, DL, MVT::i32);
31 return DAG.getNode(WebAssemblyISD::MEMORY_COPY, DL, MVT::Other,
33 DAG.getZExtOrTrunc(Size, DL, MVT::i32)});
37 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2,
40 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, Align,
46 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Val,
49 if (!DAG.getMachineFunction()
54 SDValue MemIdx = DAG
21 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool IsVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
36 EmitTargetCodeForMemmove( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool IsVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
45 EmitTargetCodeForMemset( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Val, SDValue Size, unsigned Align, bool IsVolatile, MachinePointerInfo DstPtrInfo) const argument
[all...]
H A DWebAssemblyISelLowering.h1 //- WebAssemblyISelLowering.h - WebAssembly DAG Lowering Interface -*- C++ -*-//
11 /// code into a selection DAG.
90 SelectionDAG &DAG) const override;
94 const SDLoc &DL, SelectionDAG &DAG,
98 SelectionDAG &DAG) const override;
105 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
106 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
109 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) cons
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
10 // selection DAG.
119 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
151 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
153 SelectionDAG &DAG) const override;
155 SelectionDAG &DAG) const override;
159 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
160 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
161 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
162 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) cons
[all...]
H A DHexagonISelLoweringHVX.cpp36 // nodes, which would be unoptimizable by the DAG combiner.
209 const SDLoc &dl, SelectionDAG &DAG) const {
211 IntOps.push_back(DAG.getConstant(IntId, dl, MVT::i32));
214 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResTy, IntOps);
251 SelectionDAG &DAG) const {
255 return DAG.getBitcast(CastTy, Vec);
260 SelectionDAG &DAG) const {
261 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)),
267 SelectionDAG &DAG) const {
271 return DAG
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H A DHexagonSelectionDAGInfo.cpp20 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
33 const TargetLowering &TLI = *DAG.getSubtarget().getTargetLowering();
36 Entry.Ty = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
46 const MachineFunction &MF = DAG.getMachineFunction();
50 TargetLowering::CallLoweringInfo CLI(DAG);
55 Type::getVoidTy(*DAG.getContext()),
56 DAG.getTargetExternalSymbol(
57 SpecialMemcpyName, TLI.getPointerTy(DAG.getDataLayout()), Flags),
19 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreSelectionDAGInfo.cpp19 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
25 DAG.MaskedValueIsZero(Size, APInt(SizeBitWidth, 3))) {
26 const TargetLowering &TLI = *DAG.getSubtarget().getTargetLowering();
29 Entry.Ty = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
34 TargetLowering::CallLoweringInfo CLI(DAG);
38 Type::getVoidTy(*DAG.getContext()),
39 DAG.getExternalSymbol(
40 "__memcpy_4", TLI.getPointerTy(DAG.getDataLayout())),
18 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
H A DXCoreISelLowering.cpp1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
198 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
201 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
202 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
203 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
204 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
205 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
206 case ISD::LOAD: return LowerLOAD(Op, DAG);
207 case ISD::STORE: return LowerSTORE(Op, DAG);
208 case ISD::VAARG: return LowerVAARG(Op, DAG);
404 isWordAligned(SDValue Value, SelectionDAG &DAG) argument
1033 SelectionDAG &DAG = CLI.DAG; local
1061 LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl<CCValAssign> &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) argument
1107 LowerCCCCallTo( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1241 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1260 LowerCCCArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1592 SelectionDAG &DAG = DCI.DAG; local
1816 computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
[all...]
H A DXCoreISelLowering.h1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
10 // selection DAG.
108 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
114 SelectionDAG &DAG) const override;
117 // DAG node.
150 const SDLoc &dl, SelectionDAG &DAG,
158 const SDLoc &dl, SelectionDAG &DAG,
160 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
162 SelectionDAG &DAG) const;
166 SelectionDAG &DAG) cons
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.h1 //===-- LanaiISelLowering.h - Lanai DAG Lowering Interface -....-*- C++ -*-===//
10 // selection DAG.
72 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
75 // DAG node.
78 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
79 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
80 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
81 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
82 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
83 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) cons
[all...]
H A DLanaiISelLowering.cpp1 //===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===//
176 SelectionDAG &DAG) const {
179 return LowerMUL(Op, DAG);
181 return LowerBR_CC(Op, DAG);
183 return LowerConstantPool(Op, DAG);
185 return LowerGlobalAddress(Op, DAG);
187 return LowerBlockAddress(Op, DAG);
189 return LowerJumpTable(Op, DAG);
191 return LowerSELECT_CC(Op, DAG);
193 return LowerSETCC(Op, DAG);
396 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
411 SelectionDAG &DAG = CLI.DAG; local
437 LowerCCCArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
596 LowerCCCCallTo( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool IsVarArg, bool , const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
774 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
801 IntCondCCodeToICC(SDValue CC, const SDLoc &DL, SDValue &RHS, SelectionDAG &DAG) argument
1347 isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG) argument
1421 SelectionDAG &DAG = DCI.DAG; local
1488 computeKnownBitsForTargetNode( const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp27 SelectionDAG &DAG, ArrayRef<MCPhysReg> ClobberSet) const {
33 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
38 DAG.getSubtarget().getRegisterInfo());
47 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Val,
52 DAG.getMachineFunction().getSubtarget<X86Subtarget>();
58 assert(!isBaseRegConflictPossible(DAG, ClobberSet));
74 ? DAG.getTargetLoweringInfo().getLibcallName(RTLIB::BZERO)
76 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
77 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
78 Type *IntPtrTy = DAG
26 isBaseRegConflictPossible( SelectionDAG &DAG, ArrayRef<MCPhysReg> ClobberSet) const argument
46 EmitTargetCodeForMemset( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Val, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
186 emitRepmovs(const X86Subtarget &Subtarget, SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, MVT AVT) argument
208 emitRepmovsB(const X86Subtarget &Subtarget, SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size) argument
236 emitConstantSizeRepmov( SelectionDAG &DAG, const X86Subtarget &Subtarget, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, EVT SizeVT, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) argument
292 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFSelectionDAGInfo.cpp21 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
35 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
37 Dst = DAG.getNode(BPFISD::MEMCPY, dl, VTs, Chain, Dst, Src,
38 DAG.getConstant(CopyLen, dl, MVT::i64),
39 DAG.getConstant(Align, dl, MVT::i64));
20 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMacroFusion.cpp9 /// \file This file contains the implementation of the DAG scheduling mutation
54 static bool fuseInstructionPair(ScheduleDAGInstrs &DAG, SUnit &FirstSU, argument
71 if (!DAG.addEdge(&SecondSU, SDep(&FirstSU, SDep::Cluster)))
92 dbgs() << "Macro fuse: "; DAG.dumpNodeName(FirstSU); dbgs() << " - ";
93 DAG.dumpNodeName(SecondSU); dbgs() << " / ";
94 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - "
95 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';);
99 if (&SecondSU != &DAG.ExitSU)
103 SU == &DAG.ExitSU || SU == &SecondSU || SU->isPred(&SecondSU))
105 LLVM_DEBUG(dbgs() << " Bind "; DAG
154 apply(ScheduleDAGInstrs *DAG) argument
168 scheduleAdjacentImpl(ScheduleDAGInstrs &DAG, SUnit &AnchorSU) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SelectionDAGInfo.cpp19 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
26 DAG.getMachineFunction().getSubtarget<AArch64Subtarget>();
28 ? DAG.getTargetLoweringInfo().getLibcallName(RTLIB::BZERO) : nullptr;
34 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
35 Type *IntPtrTy = Type::getInt8PtrTy(*DAG.getContext());
43 TargetLowering::CallLoweringInfo CLI(DAG);
46 .setLibCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
47 DAG.getExternalSymbol(bzeroName, IntPtr),
62 static SDValue EmitUnrolledSetTag(SelectionDAG &DAG, const SDLoc &dl, argument
66 MachineFunction &MF = DAG
18 EmitTargetCodeForMemset( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
112 EmitTargetCodeForSetTag( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Addr, SDValue Size, MachinePointerInfo DstPtrInfo, bool ZeroData) const argument
[all...]
H A DAArch64ISelLowering.cpp1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
1043 // independent DAG combine optimize this node.
1045 New = TLO.DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0),
1046 TLO.DAG.getConstant(NewImm, DL, VT));
1047 // Otherwise, create a machine node so that target independent DAG combine
1051 SDValue EncConst = TLO.DAG.getTargetConstant(Enc, DL, VT);
1053 TLO.DAG.getMachineNode(NewOpc, DL, VT, Op.getOperand(0), EncConst), 0);
1105 const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {
1111 Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
1112 Known2 = DAG
1103 computeKnownBitsForTargetNode( const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
1695 emitStrictFPComparison(SDValue LHS, SDValue RHS, const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, bool IsSignaling) argument
1706 emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) argument
1804 emitConditionalComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue CCOp, AArch64CC::CondCode Predicate, AArch64CC::CondCode OutCC, const SDLoc &DL, SelectionDAG &DAG) argument
1914 emitConjunctionRec(SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp, AArch64CC::CondCode Predicate) argument
2026 emitConjunction(SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC) argument
2074 getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AArch64cc, SelectionDAG &DAG, const SDLoc &dl) argument
2206 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) argument
2320 LowerF128Call(SDValue Op, SelectionDAG &DAG, RTLIB::Libcall Call) const argument
2343 LowerXOR(SDValue Op, SelectionDAG &DAG) argument
2423 LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) argument
2459 LowerXALUO(SDValue Op, SelectionDAG &DAG) argument
2490 LowerPREFETCH(SDValue Op, SelectionDAG &DAG) argument
2622 LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) argument
2722 LowerBITCAST(SDValue Op, SelectionDAG &DAG) argument
2754 addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode) argument
2771 isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, bool isSigned) argument
2797 skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) argument
2821 isSignExtended(SDNode *N, SelectionDAG &DAG) argument
2826 isZeroExtended(SDNode *N, SelectionDAG &DAG) argument
2831 isAddSubSExt(SDNode *N, SelectionDAG &DAG) argument
2842 isAddSubZExt(SDNode *N, SelectionDAG &DAG) argument
2873 LowerMUL(SDValue Op, SelectionDAG &DAG) argument
3069 LowerTruncateVectorStore(SDLoc DL, StoreSDNode *ST, EVT VT, EVT MemVT, SelectionDAG &DAG) argument
3330 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3587 saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL, SDValue &Chain) const argument
3673 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn, SDValue ThisVal) const argument
3871 addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const argument
3914 SelectionDAG &DAG = CLI.DAG; local
4470 getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument
4477 getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument
4483 getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument
4490 getTargetNode(BlockAddressSDNode* N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument
4498 getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags) const argument
4511 getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags) const argument
4527 getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags) const argument
4541 getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags) const argument
6034 getEstimate(const AArch64Subtarget *ST, unsigned Opcode, SDValue Operand, SelectionDAG &DAG, int &ExtraSteps) argument
6056 getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &ExtraSteps, bool &UseOneConst, bool Reciprocal) const argument
6098 getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &ExtraSteps) const argument
6506 WidenVector(SDValue V64Reg, SelectionDAG &DAG) argument
6526 NarrowVector(SDValue V128Reg, SelectionDAG &DAG) argument
7002 tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) argument
7032 GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl) argument
7134 GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask, SelectionDAG &DAG) argument
7460 tryAdvSIMDModImm64(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) argument
7481 tryAdvSIMDModImm32(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits, const SDValue *LHS = nullptr) argument
7529 tryAdvSIMDModImm16(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits, const SDValue *LHS = nullptr) argument
7569 tryAdvSIMDModImm321s(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) argument
7600 tryAdvSIMDModImm8(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) argument
7621 tryAdvSIMDModImmFP(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) argument
7689 tryLowerToSLI(SDNode *N, SelectionDAG &DAG) argument
7795 NormalizeBuildVector(SDValue Op, SelectionDAG &DAG) argument
7826 ConstantBuildVector(SDValue Op, SelectionDAG &DAG) argument
8376 EmitVectorComparison(SDValue LHS, SDValue RHS, AArch64CC::CondCode CC, bool NoNans, EVT VT, const SDLoc &dl, SelectionDAG &DAG) argument
8535 getReductionSDNode(unsigned Op, SDLoc DL, SDValue ScalarOp, SelectionDAG &DAG) argument
9628 foldVectorXorShiftIntoCmp(SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument
9652 performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) argument
9679 performXorCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument
9692 BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl<SDNode *> &Created) const argument
9747 performMulCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument
9855 performVectorCompareAndMaskUnaryOpCombine(SDNode *N, SelectionDAG &DAG) argument
9901 performIntToFpCombine(SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument
9942 performFpToIntCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument
10017 performFDivCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument
10110 SelectionDAG &DAG = DCI.DAG; local
10151 SelectionDAG &DAG = DCI.DAG; local
10198 SelectionDAG &DAG = DCI.DAG; local
10276 SelectionDAG &DAG = DCI.DAG; local
10319 SelectionDAG &DAG = DCI.DAG; local
10345 performConcatVectorsCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
10427 tryCombineFixedPointConvert(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
10489 tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) argument
10622 performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) argument
10672 performAddSubLongCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
10721 tryCombineLongOpWithDup(unsigned IID, SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
10750 tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) argument
10821 tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) argument
10834 combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N, SelectionDAG &DAG) argument
10844 LowerSVEIntReduction(SDNode *N, unsigned Opc, SelectionDAG &DAG) argument
10872 LowerSVEIntrinsicEXT(SDNode *N, SelectionDAG &DAG) argument
10897 tryConvertSVEWideCompare(SDNode *N, unsigned ReplacementIID, bool Invert, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
10968 getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op, AArch64CC::CondCode Cond) argument
10995 SelectionDAG &DAG = DCI.DAG; local
11105 performExtendCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
11203 splitStoreSplat(SelectionDAG &DAG, StoreSDNode &St, SDValue SplatVal, unsigned NumVecElts) argument
11243 performLDNT1Combine(SDNode *N, SelectionDAG &DAG) argument
11268 performSTNT1Combine(SDNode *N, SelectionDAG &DAG) argument
11300 replaceZeroVectorStore(SelectionDAG &DAG, StoreSDNode &St) argument
11363 replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode &St) argument
11416 splitStores(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument
11592 performTBISimplification(SDValue Addr, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
11607 performSTORECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument
11624 performNEONPostLDSTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
11942 performCONDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, unsigned CCIndex, unsigned CmpIndex) argument
12016 performBRCONDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
12082 getTestBitOperand(SDValue Op, unsigned &Bit, bool &Invert, SelectionDAG &DAG) argument
12155 performTBZCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
12186 performVSelectCombine(SDNode *N, SelectionDAG &DAG) argument
12217 SelectionDAG &DAG = DCI.DAG; local
12286 performGlobalAddressCombine(SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget, const TargetMachine &TM) argument
12359 performST1ScatterCombine(SDNode *N, SelectionDAG &DAG, unsigned Opcode, bool OnlyPackedOffsets = true) argument
12428 performLD1GatherCombine(SDNode *N, SelectionDAG &DAG, unsigned Opcode, bool OnlyPackedOffsets = true) argument
12489 performSignExtendInRegCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
12547 SelectionDAG &DAG = DCI.DAG; local
12797 ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) argument
12814 ReplaceReductionResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG, unsigned InterOp, unsigned AcrossOp) argument
12828 splitInt128(SDValue N, SelectionDAG &DAG) argument
12838 createGPRPairNode(SelectionDAG &DAG, SDValue V) argument
12855 ReplaceCMP_SWAP_128Results(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument
13293 shouldExpandShift(SelectionDAG &DAG, SDNode *N) const argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
10 // selection DAG.
201 const SDLoc &DL, SelectionDAG &DAG) const {
203 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
204 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
212 const SDLoc &DL, SelectionDAG &DAG) const {
213 MachineFunction &MF = DAG.getMachineFunction();
219 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
220 *DAG.getContext());
244 SDValue Part0 = DAG
369 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
383 LowerFormalArguments_32( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
578 LowerFormalArguments_64( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
694 hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, ImmutableCallSite CS) argument
719 SelectionDAG &DAG = CLI.DAG; local
1855 computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
2147 LowerF128Op(SDValue Op, SelectionDAG &DAG, const char *LibFuncName, unsigned numArgs) const argument
2297 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2313 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2330 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2359 LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2387 LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2408 LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2427 LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2464 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2500 LowerVASTART(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2520 LowerVAARG(SDValue Op, SelectionDAG &DAG) argument
2543 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument
2607 getFLUSHW(SDValue Op, SelectionDAG &DAG) argument
2614 getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget, bool AlwaysFlush = false) argument
2647 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument
2656 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget) argument
2691 LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG, unsigned opcode) argument
2725 LowerF128Load(SDValue Op, SelectionDAG &DAG) argument
2768 LowerLOAD(SDValue Op, SelectionDAG &DAG) argument
2780 LowerF128Store(SDValue Op, SelectionDAG &DAG) argument
2816 LowerSTORE(SDValue Op, SelectionDAG &DAG) argument
2838 LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) argument
2881 LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) argument
2932 LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2980 LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp38 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG);
52 N->dump(&DAG); dbgs() << "\n";
217 return DAG.getNode(ISD::AssertSext, SDLoc(N),
224 return DAG.getNode(ISD::AssertZext, SDLoc(N),
229 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
230 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
242 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
257 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
264 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
265 SDValue Res = DAG
796 earlyExpandDIVFIX(SDNode *N, SDValue LHS, SDValue RHS, unsigned Scale, const TargetLowering &TLI, SelectionDAG &DAG) argument
[all...]
H A DLegalizeVectorTypes.cpp36 LLVM_DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
44 N->dump(&DAG);
182 return DAG.getNode(N->getOpcode(), SDLoc(N),
190 return DAG.getNode(N->getOpcode(), SDLoc(N),
198 return DAG.getNode(N->getOpcode(), SDLoc(N), Op0.getValueType(), Op0, Op1,
224 SDValue Result = DAG.getNode(N->getOpcode(), dl, ValueVTs, Opers);
244 DAG.ExtractVectorElements(N->getOperand(0), ElemsLHS);
245 DAG.ExtractVectorElements(N->getOperand(1), ElemsRHS);
250 SDVTList ScalarVTs = DAG.getVTList(
252 SDNode *ScalarNode = DAG
2891 CollectOpsToWiden(SelectionDAG &DAG, const TargetLowering &TLI, SmallVectorImpl<SDValue> &ConcatOps, unsigned ConcatEnd, EVT VT, EVT MaxVT, EVT WidenVT) argument
4767 FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, unsigned Width, EVT WidenVT, unsigned Align = 0, unsigned WidenEx = 0) argument
4836 BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy, SmallVectorImpl<SDValue> &LdOps, unsigned Start, unsigned End) argument
[all...]
H A DLegalizeDAG.cpp88 SelectionDAG &DAG; member in class:__anon1812::SelectionDAGLegalize
98 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
104 SelectionDAGLegalize(SelectionDAG &DAG, argument
107 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
207 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
208 dbgs() << " with: "; New->dump(&DAG));
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp1 //===- ARCISelLowering.cpp - ARC DAG Lowering Impl --------------*- C++ -*-===//
38 SDLoc dl, SelectionDAG &DAG,
163 SDValue ARCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
172 SDValue Cmp = DAG.getNode(ARCISD::CMP, dl, MVT::Glue, LHS, RHS);
173 return DAG.getNode(ARCISD::CMOV, dl, TVal.getValueType(), TVal, FVal,
174 DAG.getConstant(ArcCC, dl, MVT::i32), Cmp);
178 SelectionDAG &DAG) const {
190 SDValue LS = DAG.getNode(ISD::SHL, dl, MVT::i32, Op0,
191 DAG.getConstant(32 - Width, dl, MVT::i32));
192 SDValue SR = DAG
225 SelectionDAG &DAG = CLI.DAG; local
370 lowerCallResult(SDValue Chain, SDValue Glue, const SmallVectorImpl<CCValAssign> &RVLocs, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) argument
431 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
446 LowerCallArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
733 LowerVASTART(SDValue Op, SelectionDAG &DAG) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScheduleDAGMutation.h21 /// Mutate the DAG as a postpass after normal DAG building.
28 virtual void apply(ScheduleDAGInstrs *DAG) = 0;

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