| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 76 case D11: case D10: case D9: case D8:
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| H A D | ARMFrameLowering.cpp | 444 if (Reg == ARM::D8)
446 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())
688 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) {
995 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
1085 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
1177 unsigned DNum = CSI[i].getReg() - ARM::D8;
[all...] |
| /freebsd-11-stable/lib/msun/ld128/ |
| H A D | s_expl.c | 178 D8 = 2.48015873015873015687993712101479612e-5L, variable
252 x * (D7 + x * (D8 + x * (D9 + x * (D10 +
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| /freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | X86RecognizableInstr.h | 51 MAP(D8, 88) \
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.h | 87 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 },
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| H A D | HexagonFrameLowering.cpp | 930 Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9,
2485 // a contiguous block starting from D8.
2494 if (F != Hexagon::D8)
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| H A D | HexagonISelLowering.cpp | 283 .Case("r17:16", Hexagon::D8)
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 119 case AArch64::D8: return AArch64::B8;
159 case AArch64::B8: return AArch64::D8;
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 116 case AArch64::D8:
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 248 case D8:
561 (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
|
| H A D | HexagonMCDuplexInfo.cpp | 690 case Hexagon::D8:
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 587 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
597 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 171 {codeview::RegisterId::ARM64_D8, AArch64::D8},
|
| H A D | AArch64AsmBackend.cpp | 672 // D8/D9 pair = 0x00000100,
676 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 &&
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 85 SP::D8, SP::D24, SP::D9, SP::D25,
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAsmBackend.cpp | 1250 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 };
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 151 Sparc::D8, Sparc::D9, Sparc::D10, Sparc::D11,
|
| /freebsd-11-stable/crypto/openssl/crypto/ec/asm/ |
| H A D | ecp_nistz256-avx2.pl | 307 my ($D0,$D1,$D2,$D3, $D4,$D5,$D6,$D7, $D8)=map("%ymm$_",(0..8));
344 vmovdqa 32*8-160(%rax), $D8
365 vpsllq \$40, $D8, $T3
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| /freebsd-11-stable/sys/contrib/edk2/Include/Library/ |
| H A D | BaseLib.h | 167 UINT64 D8; member in struct:__anon6007
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 335 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
|
| /freebsd-11-stable/contrib/amd/doc/ |
| H A D | texinfo.tex | 1562 <15> <02D8>
1572 <1F> <00D8>
1648 <15> <02D8>
1658 <1F> <00D8>
1733 <15> <02D8>
1743 <1F> <00D8>
9299 \DeclareUnicodeCharacter{00D8}{\O}
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1318 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3239 case Mips::D8: return Mips::F17;
|