| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 77 case D7: case D6: case D5: case D4:
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| H A D | ARMCallingConv.cpp | 163 ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
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| /freebsd-11-stable/lib/msun/ld128/ |
| H A D | s_expl.c | 177 D7 = 1.98412698412698412699085805424661471e-4L, variable
252 x * (D7 + x * (D8 + x * (D9 + x * (D10 +
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| /freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | X86RecognizableInstr.h | 50 MAP(D7, 87) \
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.cpp | 34 AArch64::D6, AArch64::D7};
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| H A D | AArch64PBQPRegAlloc.cpp | 66 case AArch64::D7:
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| H A D | AArch64FastISel.cpp | 3016 AArch64::D5, AArch64::D6, AArch64::D7 },
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 118 case AArch64::D7: return AArch64::B7;
158 case AArch64::B7: return AArch64::D7;
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 63 D0, D1, D2, D3, D4, D5, D6, D7, 0
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| H A D | HexagonISelLowering.cpp | 282 .Case("r15:14", Hexagon::D7)
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| /freebsd-11-stable/crypto/openssl/crypto/ec/asm/ |
| H A D | ecp_nistz256-avx2.pl | 307 my ($D0,$D1,$D2,$D3, $D4,$D5,$D6,$D7, $D8)=map("%ymm$_",(0..8));
343 vmovdqa 32*7-160(%rax), $D7
364 vpsllq \$11, $D7, $D7
366 vpaddq $D6, $D7, $D7
367 vpaddq $D7, $T3, $D3 # out[3] = (in[6] >> (64*3-shift*6)) ^ (in[7] << shift*7%64) ^ (in[8] << shift*8%64);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 170 {codeview::RegisterId::ARM64_D7, AArch64::D7},
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 586 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 84 SP::D6, SP::D22, SP::D7, SP::D23,
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1178 VA.convertToReg(Mips::D7);
1337 std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}};
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| H A D | MipsISelLowering.cpp | 2969 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 150 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 335 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
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| /freebsd-11-stable/contrib/netbsd-tests/usr.bin/netpgpverify/ |
| H A D | t_netpgpverify.sh | 2992 C6wBPSwk/p6+6SIEt4nul8x9+wKdA4upL77ggatytxA5OVCJE0wW8A0uej/Pb/D7
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1317 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3238 case Mips::D7: return Mips::F15;
|