| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 77 case D7: case D6: case D5: case D4:
|
| H A D | ARMCallingConv.cpp | 163 ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
|
| /freebsd-11-stable/lib/msun/ld128/ |
| H A D | s_expl.c | 176 D6 = 1.38888888888888888888887138722762072e-3L, variable
251 q = x * x2 * D3 + x2 * x2 * (D4 + x * (D5 + x * (D6 +
|
| /freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | X86RecognizableInstr.h | 49 MAP(D6, 86) \
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.cpp | 34 AArch64::D6, AArch64::D7};
|
| H A D | AArch64PBQPRegAlloc.cpp | 115 case AArch64::D6:
|
| H A D | AArch64FastISel.cpp | 3016 AArch64::D5, AArch64::D6, AArch64::D7 },
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 117 case AArch64::D6: return AArch64::B6;
157 case AArch64::B6: return AArch64::D6;
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 63 D0, D1, D2, D3, D4, D5, D6, D7, 0
|
| H A D | HexagonISelLowering.cpp | 281 .Case("r13:12", Hexagon::D6)
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 169 {codeview::RegisterId::ARM64_D6, AArch64::D6},
|
| /freebsd-11-stable/crypto/openssl/crypto/ec/asm/ |
| H A D | ecp_nistz256-avx2.pl | 307 my ($D0,$D1,$D2,$D3, $D4,$D5,$D6,$D7, $D8)=map("%ymm$_",(0..8));
342 vmovdqa 32*6-160(%rax), $D6
359 vpsllq \$46, $D6, $T2
363 vpsrlq \$18, $D6, $D6
366 vpaddq $D6, $D7, $D7
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 586 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 84 SP::D6, SP::D22, SP::D7, SP::D23,
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1168 VA.convertToReg(Mips::D6);
1337 std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}};
|
| H A D | MipsISelLowering.cpp | 2969 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 150 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 335 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1317 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3237 case Mips::D6: return Mips::F13;
|
| /freebsd-11-stable/contrib/amd/doc/ |
| H A D | texinfo.tex | 9298 \DeclareUnicodeCharacter{00D6}{\"O}
|