Searched refs:Concat (Results 1 - 11 of 11) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp232 static uint32_t Concat[] = { variable
314 Builder.CreateShuffleVector(Temp[2 * i], Temp[2 * i + 1], Concat);
421 reorderSubVector(VT, TransposedMatrix, VecOut, makeArrayRef(Concat, 16),
532 InVec[j * 6 + i], InVec[j * 6 + i + 3], makeArrayRef(Concat, 32));
538 Vec[i] = Builder.CreateShuffleVector(Vec[i], Vec[i + 3], Concat);
H A DX86ISelLowering.cpp19611 // Concat upper and lower parts.
19616 // Concat upper and lower parts.
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp517 CodeGenSubRegIndex *Concat = RegBank.getConcatSubRegIndex(Parts); local
519 std::make_pair(Concat, Cand);
527 SubReg2Idx.insert(std::make_pair(Cand, Concat));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/TableGen/
H A DRecord.cpp863 SmallString<80> Concat(I0->getValue());
864 Concat.append(I1->getValue());
865 return StringInit::get(Concat);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstructionSelector.cpp3821 MachineInstr *Concat = emitVectorConcat(None, Src1Reg, Src2Reg, MIRBuilder);
3822 if (!Concat) {
3834 {Concat->getOperand(0).getReg(), IndexLoad->getOperand(0).getReg()});
H A DAArch64ISelLowering.cpp7343 if (SDValue Concat = tryFormConcatFromShuffle(Op, DAG))
7344 return Concat;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp1164 auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts); local
1165 MO.setReg(Concat.getReg(0));
2888 auto Concat = MIRBuilder.buildConcatVectors(WidenedDstTy, ConcatOps);
2889 MIRBuilder.buildExtract(DstReg, Concat, 0);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp4561 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
4562 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4683 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
4684 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
H A DDAGCombiner.cpp17459 assert(NumConcats >= 2 && "Concat needs at least two inputs!");
17917 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), local
17919 return DAG.getBitcast(VT, Concat);
18201 assert(FoundMinVT && "Concat vector type mismatch");
18213 assert(SVT == OpVT.getScalarType() && "Concat vector type mismatch");
18224 "Concat vector type mismatch");
18559 "Concat and extract subvector do not change element type");
19971 auto ConcatWithConstantOrUndef = [](SDValue Concat) {
19972 return Concat.getOpcode() == ISD::CONCAT_VECTORS &&
19973 std::all_of(std::next(Concat
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp4841 SDValue Concat = InsertLo ?
4845 return DAG.getNode(ISD::BITCAST, SL, VecVT, Concat);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp11175 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), ConcatVT, local
11177 Ops.push_back(Concat);

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