Searched refs:Concat (Results 1 - 11 of 11) sorted by relevance
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InterleavedAccess.cpp | 232 static uint32_t Concat[] = { variable 314 Builder.CreateShuffleVector(Temp[2 * i], Temp[2 * i + 1], Concat); 421 reorderSubVector(VT, TransposedMatrix, VecOut, makeArrayRef(Concat, 16), 532 InVec[j * 6 + i], InVec[j * 6 + i + 3], makeArrayRef(Concat, 32)); 538 Vec[i] = Builder.CreateShuffleVector(Vec[i], Vec[i + 3], Concat);
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H A D | X86ISelLowering.cpp | 19611 // Concat upper and lower parts. 19616 // Concat upper and lower parts. [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.cpp | 517 CodeGenSubRegIndex *Concat = RegBank.getConcatSubRegIndex(Parts); local 519 std::make_pair(Concat, Cand); 527 SubReg2Idx.insert(std::make_pair(Cand, Concat));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/TableGen/ |
H A D | Record.cpp | 863 SmallString<80> Concat(I0->getValue()); 864 Concat.append(I1->getValue()); 865 return StringInit::get(Concat);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64InstructionSelector.cpp | 3821 MachineInstr *Concat = emitVectorConcat(None, Src1Reg, Src2Reg, MIRBuilder); 3822 if (!Concat) { 3834 {Concat->getOperand(0).getReg(), IndexLoad->getOperand(0).getReg()});
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H A D | AArch64ISelLowering.cpp | 7343 if (SDValue Concat = tryFormConcatFromShuffle(Op, DAG)) 7344 return Concat;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.cpp | 1164 auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts); local 1165 MO.setReg(Concat.getReg(0)); 2888 auto Concat = MIRBuilder.buildConcatVectors(WidenedDstTy, ConcatOps); 2889 MIRBuilder.buildExtract(DstReg, Concat, 0);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeDAG.cpp | 4561 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps); 4562 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat); 4683 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts); 4684 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
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H A D | DAGCombiner.cpp | 17459 assert(NumConcats >= 2 && "Concat needs at least two inputs!"); 17917 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), local 17919 return DAG.getBitcast(VT, Concat); 18201 assert(FoundMinVT && "Concat vector type mismatch"); 18213 assert(SVT == OpVT.getScalarType() && "Concat vector type mismatch"); 18224 "Concat vector type mismatch"); 18559 "Concat and extract subvector do not change element type"); 19971 auto ConcatWithConstantOrUndef = [](SDValue Concat) { 19972 return Concat.getOpcode() == ISD::CONCAT_VECTORS && 19973 std::all_of(std::next(Concat [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 4841 SDValue Concat = InsertLo ? 4845 return DAG.getNode(ISD::BITCAST, SL, VecVT, Concat);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 11175 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), ConcatVT, local 11177 Ops.push_back(Concat);
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