Searched refs:CPSR (Results 1 - 20 of 20) sorted by relevance

/freebsd-10.3-release/contrib/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp53 // 2 - Always set CPSR.
184 // Last instruction to define CPSR in the current block.
186 // Was CPSR last defined by a high latency instruction?
187 // When CPSRDef is null, this refers to CPSR defs in predecessors.
215 if (*Regs == ARM::CPSR)
231 /// the 's' 16-bit instruction partially update CPSR. Abort the
232 /// transformation to avoid adding false dependency on last CPSR setting
236 /// last instruction that defines the CPSR and the current instruction. If there
238 /// before the CPSR setting instruction anyway.
264 if (Reg == 0 || Reg == ARM::CPSR)
[all...]
H A DARMMCInstLower.cpp71 // Ignore all non-CPSR implicit register operands.
72 if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
H A DThumb2ITBlockPass.cpp87 if (Reg == ARM::CPSR)
125 // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
143 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
H A DARMFastISel.cpp226 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
239 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
240 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { argument
244 // Look to see if our OptionalDef is defining CPSR or CCR.
248 if (MO.getReg() == ARM::CPSR)
249 *CPSR = true;
272 // CPSR defs that need to be added before the remaining operands. See s_cc_out
285 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
286 bool CPSR local
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H A DARMBaseInstrInfo.cpp507 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
508 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
1652 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1682 // predicated instructions which will be reading CPSR.
1715 // 4: CPSR use.
1762 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1780 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1783 /// This will go away once we can teach tblgen how to set the optional CPSR def
2260 // There are two possible candidates which can be changed to set CPSR:
2279 // Check that CPSR is
[all...]
H A DARMBaseInstrInfo.h336 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
391 /// CPSR def operand.
H A DARMISelLowering.cpp3365 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3406 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3518 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3550 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3570 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3913 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3947 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
6272 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6288 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6380 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
[all...]
H A DARMAsmPrinter.cpp1586 .addReg(ARM::CPSR)
1605 .addReg(ARM::CPSR)
1620 .addReg(ARM::CPSR)
H A DARMExpandPseudoInsts.cpp854 .addReg(ARM::CPSR, RegState::Define);
969 .addReg(ARM::CPSR, RegState::Undef);
H A DARMCodeEmitter.cpp784 // Encode S bit if MI modifies CPSR.
809 // Encode S bit if MI modifies CPSR.
1002 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
1019 // Encode S bit if MI modifies CPSR.
1320 // Encode S bit if MI modifies CPSR.
H A DARMConstantIslandPass.cpp1790 // If the conditional branch doesn't kill CPSR, then CPSR can be liveout
1792 if (!Br.MI->killsRegister(ARM::CPSR))
H A DARMLoadStoreOptimizer.cpp600 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
601 // If the instruction has live CPSR def, then it's not safe to fold it
H A DARMISelDAGToDAG.cpp136 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
/freebsd-10.3-release/contrib/gdb/gdb/
H A Dsparc-stub.c119 Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR }; enumerator in enum:regnames
230 ! CPSR and FPSR not impl
662 0); /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
675 8 * 4, 0); /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
/freebsd-10.3-release/sys/dev/cx/
H A Dcxreg.h77 #define CPSR(b) R(b,0xd4) /* CRC polynomial select register */ macro
H A Dcsigma.c1061 outb (CPSR(c->port), c->hopt.cpsr);
/freebsd-10.3-release/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp1541 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
3693 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
5110 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
6960 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7011 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7018 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7048 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7056 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7243 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7388 Inst.getOperand(4).getReg() == ARM::CPSR) ||
[all...]
/freebsd-10.3-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp233 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
235 return MI.getOperand(Op).getReg() == ARM::CPSR;
572 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
/freebsd-10.3-release/contrib/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp561 // implicitly set CPSR. Since it's not represented in the encoding, the
562 // auto-generated decoder won't inject the CPSR operand. We need to fix
572 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
577 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
641 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
651 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
677 I->setReg(ARM::CPSR);
1108 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1115 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
/freebsd-10.3-release/contrib/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp860 O << "CPSR";
891 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
892 "Expect ARM CPSR register!");

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