Target/ARM/ARMBaseInstrInfo.cpp

507     if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
508         (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
1652     if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1682   // predicated instructions which will be reading CPSR.
1715   // 4: CPSR use.
1762   // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1780 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1783 /// This will go away once we can teach tblgen how to set the optional CPSR def
2260   // There are two possible candidates which can be changed to set CPSR:
2279   // Check that CPSR isn't set between the comparison instruction and the one we
2286     if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2287         Instr.readsRegister(ARM::CPSR, TRI))
2288       // This instruction modifies or uses CPSR after the one we want to
2349     // Scan forward for the use of CPSR
2352     // It is safe to remove CmpInstr if CPSR is redefined or killed.
2353     // If we are done with the basic block, we need to check whether CPSR is
2365         if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2369         if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2375         // Condition code is after the operand before CPSR except for VSELs.
2421             // CPSR can be used multiple times, we should continue.
2434     // If CPSR is not killed nor re-defined, we should check whether it is
2440         if ((*SI)->isLiveIn(ARM::CPSR))
2444     // Toggle the optional operand to CPSR.
2445     MI->getOperand(5).setReg(ARM::CPSR);
2480     if (MO.getReg() == ARM::CPSR && !MO.isDead())
2481       // If DefMI defines CPSR and it is not dead, it's obviously not safe
2489     if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
3506   if (Reg == ARM::CPSR) {
3512     // CPSR set and branch can be paired in the same cycle.
3519     // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3521     // incur a code size penalty (not able to use the CPSR setting 16-bit
3786   if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
3787     // When predicated, CPSR is an additional source operand for CPSR updating
3815   if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3816     // When predicated, CPSR is an additional source operand for CPSR updating