/freebsd-10.2-release/contrib/gcc/config/mips/ |
H A D | crtn.asm | 5 #define RA $7 define 7 #define RA $31 define 12 ld RA,40($sp) 15 lw RA,20($sp) 18 j RA 22 ld RA,40($sp) 25 lw RA,20($sp) 28 j RA
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/freebsd-10.2-release/contrib/binutils/opcodes/ |
H A D | ppc-opc.c | 346 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ 347 #define RA NSI + 1 351 /* As above, but 0 in the RA field means zero, not r0. */ 352 #define RA0 RA + 1 355 /* The RA field in the DQ form lq instruction, which has special 360 /* The RA field in a D or X form instruction which is an updating 361 load, which means that the RA field may not be zero and may not 366 /* The RA field in an lmw instruction, which has special value 371 /* The RA field in a D or X form instruction which is an updating 372 store or an updating floating point load, which means that the RA 345 #define RA macro [all...] |
H A D | alpha-opc.c | 58 /* The RB field when it is the same as the RA field in the same insn. 60 the RA field into the RB field, and the extraction function just 209 #define RA (UNUSED + 1) 211 #define RB (RA + 1) 241 /* The RB field when it must be the same as the RA field. */ 249 /* The RC field when it can *default* to RA. */ 259 /* The FC field when it can *default* to RA. */ 413 #define ARG_BRA { RA, BDISP } 417 #define ARG_MEM { RA, MDISP, PRB } 419 #define ARG_OPR { RA, R 207 #define RA macro [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/ |
H A D | Mips16FrameLowering.cpp | 68 unsigned RA = MRI->getDwarfRegNum(Mips::RA, true); local 69 MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, RA, -4)); 107 // Registers RA, S0,S1 are the callee saved registers and they 113 // RA and return address is taken, because it has already been added in 115 // It's killed at the spill, unless the register is RA and return address 118 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA) 132 // Registers RA,S0,S1 are the callee saved registers and they will be restored 171 MF.getRegInfo().setPhysRegUsed(Mips::RA);
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H A D | MipsRegisterInfo.cpp | 46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {} 180 // Reserve RA if in mips16 mode. 182 Reserved.set(Mips::RA);
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H A D | MipsSEInstrInfo.cpp | 423 BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA); 550 unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA; local 562 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA) 566 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA);
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H A D | MipsLongBranch.cpp | 295 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) 307 .addReg(Mips::RA).addReg(Mips::AT); 308 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
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H A D | Mips16InstrInfo.cpp | 178 // Adjust SP by FrameSize bytes. Save RA, S0, S1 205 Mips::RA); 220 // Adjust SP by FrameSize bytes. Restore RA, S0, S1 249 Mips::RA);
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/freebsd-10.2-release/contrib/llvm/lib/MC/ |
H A D | MCSubtargetInfo.cpp | 48 const MCReadAdvanceEntry *RA, 59 ReadAdvanceTable = RA; 42 InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, const SubtargetFeatureKV *PF, const SubtargetFeatureKV *PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP, unsigned NF, unsigned NP) argument
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/freebsd-10.2-release/sys/mips/mips/ |
H A D | stack_machdep.c | 78 if (insn.IType.rs != SP || insn.IType.rt != RA) 102 if (insn.RType.rs != RA)
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H A D | exception.S | 320 SAVE_REG(ra, RA, sp) ;\ 366 RESTORE_REG(ra, RA, sp) ;\ 478 SAVE_U_PCB_REG(ra, RA, k1) 568 RESTORE_U_PCB_REG(ra, RA, k1) 584 REG_S ra, CALLFRAME_RA(sp) # save RA 719 SAVE_U_PCB_REG(ra, RA, k1) 835 RESTORE_U_PCB_REG(ra, RA, k1)
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/freebsd-10.2-release/contrib/llvm/lib/Transforms/IPO/ |
H A D | DeadArgumentElimination.cpp | 158 void MarkValue(const RetOrArg &RA, Liveness L, 160 void MarkLive(const RetOrArg &RA); 162 void PropagateLiveness(const RetOrArg &RA); 651 /// MarkValue - This function marks the liveness of RA depending on L. If L is 653 /// such that RA will be marked live if any use in MaybeLiveUses gets marked 655 void DAE::MarkValue(const RetOrArg &RA, Liveness L, argument 658 case Live: MarkLive(RA); break; 665 Uses.insert(std::make_pair(*UI, RA)); 690 void DAE::MarkLive(const RetOrArg &RA) { argument 691 if (LiveFunctions.count(RA 703 PropagateLiveness(const RetOrArg &RA) argument [all...] |
/freebsd-10.2-release/contrib/llvm/utils/TableGen/ |
H A D | FixedLenDecoderEmitter.cpp | 468 void reportRegion(bitAttr_t RA, unsigned StartBit, unsigned BitIndex, 1396 void FilterChooser::reportRegion(bitAttr_t RA, unsigned StartBit, 1398 if (RA == ATTR_MIXED && AllowMixed) 1400 else if (RA == ATTR_ALL_SET && !AllowMixed) 1518 bitAttr_t RA = ATTR_NONE; 1526 switch (RA) { 1533 RA = ATTR_ALL_SET; 1539 RA = ATTR_MIXED; 1548 reportRegion(RA, StartBit, BitIndex, AllowMixed); 1549 RA [all...] |
/freebsd-10.2-release/contrib/llvm/include/llvm/MC/ |
H A D | MCSubtargetInfo.h | 55 const MCReadAdvanceEntry *RA,
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H A D | MCRegisterInfo.h | 239 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, argument 252 RAReg = RA;
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/freebsd-10.2-release/lib/libc/mips/gen/ |
H A D | setjmp.S | 71 REG_S ra, CALLFRAME_RA(sp) # save RA 83 REG_L ra, CALLFRAME_RA(sp) # restore RA 152 REG_S ra, CALLFRAME_RA(sp) # save RA
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/freebsd-10.2-release/sys/dev/ixgb/ |
H A D | ixgb_hw.c | 402 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 403 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 440 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 441 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 594 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 595 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
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/freebsd-10.2-release/sys/mips/include/ |
H A D | regnum.h | 92 #define RA 31 macro
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/freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCTargetDesc.cpp | 54 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; local 57 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
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/freebsd-10.2-release/contrib/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCTargetDesc.cpp | 253 unsigned RA = (TheTriple.getArch() == Triple::x86_64) local 258 InitX86MCRegisterInfo(X, RA, 261 RA);
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/freebsd-10.2-release/contrib/binutils/include/opcode/ |
H A D | cr16.h | 38 era = 14, sp = 15, RA, enumerator in enum:__anon586
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/freebsd-10.2-release/contrib/llvm/lib/Analysis/ |
H A D | ScalarEvolution.cpp | 509 const Argument *RA = cast<Argument>(RV); local 510 unsigned LArgNo = LA->getArgNo(), RArgNo = RA->getArgNo(); 544 const APInt &RA = RC->getValue()->getValue(); local 545 unsigned LBitWidth = LA.getBitWidth(), RBitWidth = RA.getBitWidth(); 548 return LA.ult(RA) ? -1 : 1; 553 const SCEVAddRecExpr *RA = cast<SCEVAddRecExpr>(RHS); local 556 const Loop *LLoop = LA->getLoop(), *RLoop = RA->getLoop(); 565 unsigned LNumOps = LA->getNumOperands(), RNumOps = RA->getNumOperands(); 571 long X = compare(LA->getOperand(i), RA->getOperand(i)); 3884 const SCEV *RA [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCTargetDesc.cpp | 82 InitMipsMCRegisterInfo(X, Mips::RA);
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/freebsd-10.2-release/contrib/llvm/tools/clang/lib/CodeGen/ |
H A D | MicrosoftCXXABI.cpp | 199 const ReturnAdjustment &RA); 1070 const ReturnAdjustment &RA) { 1071 if (RA.isEmpty()) 1076 if (RA.Virtual.Microsoft.VBIndex) { 1077 assert(RA.Virtual.Microsoft.VBIndex > 0); 1082 GetVBaseOffsetFromVBPtr(CGF, V, RA.Virtual.Microsoft.VBPtrOffset, 1083 IntSize * RA.Virtual.Microsoft.VBIndex, &VBPtr); 1087 if (RA.NonVirtual) 1088 V = CGF.Builder.CreateConstInBoundsGEP1_32(V, RA.NonVirtual); 1069 performReturnAdjustment(CodeGenFunction &CGF, llvm::Value *Ret, const ReturnAdjustment &RA) argument
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/freebsd-10.2-release/contrib/libpcap/ |
H A D | grammar.y | 281 %token TYPE SUBTYPE DIR ADDR1 ADDR2 ADDR3 ADDR4 RA TA 446 | RA { $$ = Q_RA; }
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