133965Sjdp/* alpha-opc.c -- Alpha AXP opcode list 2218822Sdim Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 3218822Sdim Free Software Foundation, Inc. 460484Sobrien Contributed by Richard Henderson <rth@cygnus.com>, 533965Sjdp patterned after the PPC opcode handling written by Ian Lance Taylor. 633965Sjdp 733965Sjdp This file is part of GDB, GAS, and the GNU binutils. 833965Sjdp 933965Sjdp GDB, GAS, and the GNU binutils are free software; you can redistribute 1033965Sjdp them and/or modify them under the terms of the GNU General Public 1133965Sjdp License as published by the Free Software Foundation; either version 1233965Sjdp 2, or (at your option) any later version. 1333965Sjdp 1433965Sjdp GDB, GAS, and the GNU binutils are distributed in the hope that they 1533965Sjdp will be useful, but WITHOUT ANY WARRANTY; without even the implied 1633965Sjdp warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 1733965Sjdp the GNU General Public License for more details. 1833965Sjdp 1933965Sjdp You should have received a copy of the GNU General Public License 2033965Sjdp along with this file; see the file COPYING. If not, write to the 21218822Sdim Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 22218822Sdim 02110-1301, USA. */ 2333965Sjdp 2433965Sjdp#include <stdio.h> 2560484Sobrien#include "sysdep.h" 2633965Sjdp#include "opcode/alpha.h" 2733965Sjdp#include "bfd.h" 2860484Sobrien#include "opintl.h" 2933965Sjdp 3033965Sjdp/* This file holds the Alpha AXP opcode table. The opcode table includes 3133965Sjdp almost all of the extended instruction mnemonics. This permits the 3233965Sjdp disassembler to use them, and simplifies the assembler logic, at the 3333965Sjdp cost of increasing the table size. The table is strictly constant 3489857Sobrien data, so the compiler should be able to put it in the text segment. 3533965Sjdp 3633965Sjdp This file also holds the operand table. All knowledge about inserting 3789857Sobrien and extracting operands from instructions is kept in this file. 3833965Sjdp 3933965Sjdp The information for the base instruction set was compiled from the 4033965Sjdp _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE, 4133965Sjdp version 2. 4233965Sjdp 4333965Sjdp The information for the post-ev5 architecture extensions BWX, CIX and 4433965Sjdp MAX came from version 3 of this same document, which is also available 4533965Sjdp on-line at http://ftp.digital.com/pub/Digital/info/semiconductor 4633965Sjdp /literature/alphahb2.pdf 4733965Sjdp 4833965Sjdp The information for the EV4 PALcode instructions was compiled from 4933965Sjdp _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware 5033965Sjdp Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary 5133965Sjdp revision dated June 1994. 5233965Sjdp 5333965Sjdp The information for the EV5 PALcode instructions was compiled from 5433965Sjdp _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital 5533965Sjdp Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */ 5633965Sjdp 57218822Sdim/* The RB field when it is the same as the RA field in the same insn. 58218822Sdim This operand is marked fake. The insertion function just copies 59218822Sdim the RA field into the RB field, and the extraction function just 60218822Sdim checks that the fields are the same. */ 6133965Sjdp 62218822Sdimstatic unsigned 63218822Sdiminsert_rba (unsigned insn, 64218822Sdim int value ATTRIBUTE_UNUSED, 65218822Sdim const char **errmsg ATTRIBUTE_UNUSED) 66218822Sdim{ 67218822Sdim return insn | (((insn >> 21) & 0x1f) << 16); 68218822Sdim} 6933965Sjdp 70218822Sdimstatic int 71218822Sdimextract_rba (unsigned insn, int *invalid) 72218822Sdim{ 73218822Sdim if (invalid != (int *) NULL 74218822Sdim && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) 75218822Sdim *invalid = 1; 76218822Sdim return 0; 77218822Sdim} 7833965Sjdp 79218822Sdim/* The same for the RC field. */ 80218822Sdim 81218822Sdimstatic unsigned 82218822Sdiminsert_rca (unsigned insn, 83218822Sdim int value ATTRIBUTE_UNUSED, 84218822Sdim const char **errmsg ATTRIBUTE_UNUSED) 85218822Sdim{ 86218822Sdim return insn | ((insn >> 21) & 0x1f); 87218822Sdim} 88218822Sdim 89218822Sdimstatic int 90218822Sdimextract_rca (unsigned insn, int *invalid) 91218822Sdim{ 92218822Sdim if (invalid != (int *) NULL 93218822Sdim && ((insn >> 21) & 0x1f) != (insn & 0x1f)) 94218822Sdim *invalid = 1; 95218822Sdim return 0; 96218822Sdim} 97218822Sdim 98218822Sdim/* Fake arguments in which the registers must be set to ZERO. */ 99218822Sdim 100218822Sdimstatic unsigned 101218822Sdiminsert_za (unsigned insn, 102218822Sdim int value ATTRIBUTE_UNUSED, 103218822Sdim const char **errmsg ATTRIBUTE_UNUSED) 104218822Sdim{ 105218822Sdim return insn | (31 << 21); 106218822Sdim} 107218822Sdim 108218822Sdimstatic int 109218822Sdimextract_za (unsigned insn, int *invalid) 110218822Sdim{ 111218822Sdim if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31) 112218822Sdim *invalid = 1; 113218822Sdim return 0; 114218822Sdim} 115218822Sdim 116218822Sdimstatic unsigned 117218822Sdiminsert_zb (unsigned insn, 118218822Sdim int value ATTRIBUTE_UNUSED, 119218822Sdim const char **errmsg ATTRIBUTE_UNUSED) 120218822Sdim{ 121218822Sdim return insn | (31 << 16); 122218822Sdim} 123218822Sdim 124218822Sdimstatic int 125218822Sdimextract_zb (unsigned insn, int *invalid) 126218822Sdim{ 127218822Sdim if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31) 128218822Sdim *invalid = 1; 129218822Sdim return 0; 130218822Sdim} 131218822Sdim 132218822Sdimstatic unsigned 133218822Sdiminsert_zc (unsigned insn, 134218822Sdim int value ATTRIBUTE_UNUSED, 135218822Sdim const char **errmsg ATTRIBUTE_UNUSED) 136218822Sdim{ 137218822Sdim return insn | 31; 138218822Sdim} 139218822Sdim 140218822Sdimstatic int 141218822Sdimextract_zc (unsigned insn, int *invalid) 142218822Sdim{ 143218822Sdim if (invalid != (int *) NULL && (insn & 0x1f) != 31) 144218822Sdim *invalid = 1; 145218822Sdim return 0; 146218822Sdim} 147218822Sdim 148218822Sdim 149218822Sdim/* The displacement field of a Branch format insn. */ 150218822Sdim 151218822Sdimstatic unsigned 152218822Sdiminsert_bdisp (unsigned insn, int value, const char **errmsg) 153218822Sdim{ 154218822Sdim if (errmsg != (const char **)NULL && (value & 3)) 155218822Sdim *errmsg = _("branch operand unaligned"); 156218822Sdim return insn | ((value / 4) & 0x1FFFFF); 157218822Sdim} 158218822Sdim 159218822Sdimstatic int 160218822Sdimextract_bdisp (unsigned insn, int *invalid ATTRIBUTE_UNUSED) 161218822Sdim{ 162218822Sdim return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000); 163218822Sdim} 164218822Sdim 165218822Sdim/* The hint field of a JMP/JSR insn. */ 166218822Sdim 167218822Sdimstatic unsigned 168218822Sdiminsert_jhint (unsigned insn, int value, const char **errmsg) 169218822Sdim{ 170218822Sdim if (errmsg != (const char **)NULL && (value & 3)) 171218822Sdim *errmsg = _("jump hint unaligned"); 172218822Sdim return insn | ((value / 4) & 0x3FFF); 173218822Sdim} 174218822Sdim 175218822Sdimstatic int 176218822Sdimextract_jhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED) 177218822Sdim{ 178218822Sdim return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000); 179218822Sdim} 180218822Sdim 181218822Sdim/* The hint field of an EV6 HW_JMP/JSR insn. */ 182218822Sdim 183218822Sdimstatic unsigned 184218822Sdiminsert_ev6hwjhint (unsigned insn, int value, const char **errmsg) 185218822Sdim{ 186218822Sdim if (errmsg != (const char **)NULL && (value & 3)) 187218822Sdim *errmsg = _("jump hint unaligned"); 188218822Sdim return insn | ((value / 4) & 0x1FFF); 189218822Sdim} 190218822Sdim 191218822Sdimstatic int 192218822Sdimextract_ev6hwjhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED) 193218822Sdim{ 194218822Sdim return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000); 195218822Sdim} 19633965Sjdp 197218822Sdim/* The operands table. */ 19833965Sjdp 19933965Sjdpconst struct alpha_operand alpha_operands[] = 20033965Sjdp{ 20133965Sjdp /* The fields are bits, shift, insert, extract, flags */ 20233965Sjdp /* The zero index is used to indicate end-of-list */ 20333965Sjdp#define UNUSED 0 20460484Sobrien { 0, 0, 0, 0, 0, 0 }, 20533965Sjdp 206218822Sdim /* The plain integer register fields. */ 20733965Sjdp#define RA (UNUSED + 1) 20833965Sjdp { 5, 21, 0, AXP_OPERAND_IR, 0, 0 }, 20933965Sjdp#define RB (RA + 1) 21033965Sjdp { 5, 16, 0, AXP_OPERAND_IR, 0, 0 }, 21133965Sjdp#define RC (RB + 1) 21233965Sjdp { 5, 0, 0, AXP_OPERAND_IR, 0, 0 }, 21333965Sjdp 214218822Sdim /* The plain fp register fields. */ 21533965Sjdp#define FA (RC + 1) 21633965Sjdp { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 }, 21733965Sjdp#define FB (FA + 1) 21833965Sjdp { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 }, 21933965Sjdp#define FC (FB + 1) 22033965Sjdp { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 }, 22133965Sjdp 222218822Sdim /* The integer registers when they are ZERO. */ 22333965Sjdp#define ZA (FC + 1) 22433965Sjdp { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za }, 22533965Sjdp#define ZB (ZA + 1) 22633965Sjdp { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb }, 22733965Sjdp#define ZC (ZB + 1) 22833965Sjdp { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc }, 22933965Sjdp 230218822Sdim /* The RB field when it needs parentheses. */ 23133965Sjdp#define PRB (ZC + 1) 23233965Sjdp { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 }, 23333965Sjdp 234218822Sdim /* The RB field when it needs parentheses _and_ a preceding comma. */ 23533965Sjdp#define CPRB (PRB + 1) 23633965Sjdp { 5, 16, 0, 23733965Sjdp AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 }, 23833965Sjdp 239218822Sdim /* The RB field when it must be the same as the RA field. */ 24033965Sjdp#define RBA (CPRB + 1) 24133965Sjdp { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba }, 24233965Sjdp 243218822Sdim /* The RC field when it must be the same as the RB field. */ 24433965Sjdp#define RCA (RBA + 1) 24533965Sjdp { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca }, 24633965Sjdp 247218822Sdim /* The RC field when it can *default* to RA. */ 24833965Sjdp#define DRC1 (RCA + 1) 24933965Sjdp { 5, 0, 0, 25033965Sjdp AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, 25133965Sjdp 252218822Sdim /* The RC field when it can *default* to RB. */ 25333965Sjdp#define DRC2 (DRC1 + 1) 25433965Sjdp { 5, 0, 0, 25533965Sjdp AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, 25633965Sjdp 257218822Sdim /* The FC field when it can *default* to RA. */ 25833965Sjdp#define DFC1 (DRC2 + 1) 25933965Sjdp { 5, 0, 0, 26033965Sjdp AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, 26133965Sjdp 262218822Sdim /* The FC field when it can *default* to RB. */ 26333965Sjdp#define DFC2 (DFC1 + 1) 26433965Sjdp { 5, 0, 0, 26533965Sjdp AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, 26633965Sjdp 267218822Sdim /* The unsigned 8-bit literal of Operate format insns. */ 26833965Sjdp#define LIT (DFC2 + 1) 26933965Sjdp { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 }, 27033965Sjdp 27133965Sjdp /* The signed 16-bit displacement of Memory format insns. From here 272218822Sdim we can't tell what relocation should be used, so don't use a default. */ 27333965Sjdp#define MDISP (LIT + 1) 27433965Sjdp { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 }, 27533965Sjdp 276218822Sdim /* The signed "23-bit" aligned displacement of Branch format insns. */ 27733965Sjdp#define BDISP (MDISP + 1) 27833965Sjdp { 21, 0, BFD_RELOC_23_PCREL_S2, 27933965Sjdp AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp }, 28033965Sjdp 28133965Sjdp /* The 26-bit PALcode function */ 28233965Sjdp#define PALFN (BDISP + 1) 28333965Sjdp { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 }, 28433965Sjdp 285218822Sdim /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint. */ 28633965Sjdp#define JMPHINT (PALFN + 1) 28733965Sjdp { 14, 0, BFD_RELOC_ALPHA_HINT, 28833965Sjdp AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, 28933965Sjdp insert_jhint, extract_jhint }, 29033965Sjdp 291218822Sdim /* The optional hint to RET/JSR_COROUTINE. */ 29233965Sjdp#define RETHINT (JMPHINT + 1) 29333965Sjdp { 14, 0, -RETHINT, 29433965Sjdp AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 }, 29533965Sjdp 296218822Sdim /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns. */ 29733965Sjdp#define EV4HWDISP (RETHINT + 1) 29860484Sobrien#define EV6HWDISP (EV4HWDISP) 29933965Sjdp { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, 30033965Sjdp 301218822Sdim /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns. */ 30233965Sjdp#define EV4HWINDEX (EV4HWDISP + 1) 30333965Sjdp { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 30433965Sjdp 30533965Sjdp /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns 30633965Sjdp that occur in DEC PALcode. */ 30733965Sjdp#define EV4EXTHWINDEX (EV4HWINDEX + 1) 30833965Sjdp { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 30933965Sjdp 310218822Sdim /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns. */ 31133965Sjdp#define EV5HWDISP (EV4EXTHWINDEX + 1) 31233965Sjdp { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, 31333965Sjdp 314218822Sdim /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns. */ 31533965Sjdp#define EV5HWINDEX (EV5HWDISP + 1) 31633965Sjdp { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 31760484Sobrien 31860484Sobrien /* The 16-bit combined index/scoreboard mask for the ev6 319218822Sdim hw_m[ft]pr (pal19/pal1d) insns. */ 32060484Sobrien#define EV6HWINDEX (EV5HWINDEX + 1) 32160484Sobrien { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 32260484Sobrien 323218822Sdim /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn. */ 32460484Sobrien#define EV6HWJMPHINT (EV6HWINDEX+ 1) 32560484Sobrien { 8, 0, -EV6HWJMPHINT, 32660484Sobrien AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, 32760484Sobrien insert_ev6hwjhint, extract_ev6hwjhint } 32833965Sjdp}; 32933965Sjdp 33060484Sobrienconst unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands); 33133965Sjdp 33233965Sjdp 333218822Sdim/* Macros used to form opcodes. */ 33433965Sjdp 335218822Sdim/* The main opcode. */ 33633965Sjdp#define OP(x) (((x) & 0x3F) << 26) 33733965Sjdp#define OP_MASK 0xFC000000 33833965Sjdp 339218822Sdim/* Branch format instructions. */ 34033965Sjdp#define BRA_(oo) OP(oo) 34133965Sjdp#define BRA_MASK OP_MASK 34233965Sjdp#define BRA(oo) BRA_(oo), BRA_MASK 34333965Sjdp 344218822Sdim/* Floating point format instructions. */ 34533965Sjdp#define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5)) 34633965Sjdp#define FP_MASK (OP_MASK | 0xFFE0) 34733965Sjdp#define FP(oo,fff) FP_(oo,fff), FP_MASK 34833965Sjdp 349218822Sdim/* Memory format instructions. */ 35033965Sjdp#define MEM_(oo) OP(oo) 35133965Sjdp#define MEM_MASK OP_MASK 35233965Sjdp#define MEM(oo) MEM_(oo), MEM_MASK 35333965Sjdp 354218822Sdim/* Memory/Func Code format instructions. */ 35533965Sjdp#define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF)) 35633965Sjdp#define MFC_MASK (OP_MASK | 0xFFFF) 35733965Sjdp#define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK 35833965Sjdp 359218822Sdim/* Memory/Branch format instructions. */ 36033965Sjdp#define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14)) 36133965Sjdp#define MBR_MASK (OP_MASK | 0xC000) 36233965Sjdp#define MBR(oo,h) MBR_(oo,h), MBR_MASK 36333965Sjdp 36433965Sjdp/* Operate format instructions. The OPRL variant specifies a 365218822Sdim literal second argument. */ 36633965Sjdp#define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5)) 36733965Sjdp#define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000) 36833965Sjdp#define OPR_MASK (OP_MASK | 0x1FE0) 36933965Sjdp#define OPR(oo,ff) OPR_(oo,ff), OPR_MASK 37033965Sjdp#define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK 37133965Sjdp 372218822Sdim/* Generic PALcode format instructions. */ 37333965Sjdp#define PCD_(oo) OP(oo) 37433965Sjdp#define PCD_MASK OP_MASK 37533965Sjdp#define PCD(oo) PCD_(oo), PCD_MASK 37633965Sjdp 377218822Sdim/* Specific PALcode instructions. */ 37833965Sjdp#define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF)) 37933965Sjdp#define SPCD_MASK 0xFFFFFFFF 38033965Sjdp#define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK 38133965Sjdp 382218822Sdim/* Hardware memory (hw_{ld,st}) instructions. */ 38333965Sjdp#define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) 38433965Sjdp#define EV4HWMEM_MASK (OP_MASK | 0xF000) 38533965Sjdp#define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK 38633965Sjdp 38733965Sjdp#define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10)) 38833965Sjdp#define EV5HWMEM_MASK (OP_MASK | 0xF800) 38933965Sjdp#define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK 39033965Sjdp 39160484Sobrien#define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) 39260484Sobrien#define EV6HWMEM_MASK (OP_MASK | 0xF000) 39360484Sobrien#define EV6HWMEM(oo,f) EV6HWMEM_(oo,f), EV6HWMEM_MASK 39460484Sobrien 39560484Sobrien#define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13)) 39660484Sobrien#define EV6HWMBR_MASK (OP_MASK | 0xE000) 39760484Sobrien#define EV6HWMBR(oo,h) EV6HWMBR_(oo,h), EV6HWMBR_MASK 39860484Sobrien 39933965Sjdp/* Abbreviations for instruction subsets. */ 40033965Sjdp#define BASE AXP_OPCODE_BASE 40133965Sjdp#define EV4 AXP_OPCODE_EV4 40233965Sjdp#define EV5 AXP_OPCODE_EV5 40360484Sobrien#define EV6 AXP_OPCODE_EV6 40433965Sjdp#define BWX AXP_OPCODE_BWX 40533965Sjdp#define CIX AXP_OPCODE_CIX 40633965Sjdp#define MAX AXP_OPCODE_MAX 40733965Sjdp 408218822Sdim/* Common combinations of arguments. */ 40933965Sjdp#define ARG_NONE { 0 } 41033965Sjdp#define ARG_BRA { RA, BDISP } 41133965Sjdp#define ARG_FBRA { FA, BDISP } 41233965Sjdp#define ARG_FP { FA, FB, DFC1 } 41333965Sjdp#define ARG_FPZ1 { ZA, FB, DFC1 } 41433965Sjdp#define ARG_MEM { RA, MDISP, PRB } 41533965Sjdp#define ARG_FMEM { FA, MDISP, PRB } 41633965Sjdp#define ARG_OPR { RA, RB, DRC1 } 41733965Sjdp#define ARG_OPRL { RA, LIT, DRC1 } 41833965Sjdp#define ARG_OPRZ1 { ZA, RB, DRC1 } 41933965Sjdp#define ARG_OPRLZ1 { ZA, LIT, RC } 42033965Sjdp#define ARG_PCD { PALFN } 42133965Sjdp#define ARG_EV4HWMEM { RA, EV4HWDISP, PRB } 42233965Sjdp#define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX } 42333965Sjdp#define ARG_EV5HWMEM { RA, EV5HWDISP, PRB } 42460484Sobrien#define ARG_EV6HWMEM { RA, EV6HWDISP, PRB } 42533965Sjdp 42633965Sjdp/* The opcode table. 42733965Sjdp 42833965Sjdp The format of the opcode table is: 42933965Sjdp 43033965Sjdp NAME OPCODE MASK { OPERANDS } 43133965Sjdp 43233965Sjdp NAME is the name of the instruction. 43333965Sjdp 43433965Sjdp OPCODE is the instruction opcode. 43533965Sjdp 43633965Sjdp MASK is the opcode mask; this is used to tell the disassembler 43733965Sjdp which bits in the actual opcode must match OPCODE. 43833965Sjdp 43933965Sjdp OPERANDS is the list of operands. 44033965Sjdp 44133965Sjdp The preceding macros merge the text of the OPCODE and MASK fields. 44233965Sjdp 44333965Sjdp The disassembler reads the table in order and prints the first 44433965Sjdp instruction which matches, so this table is sorted to put more 44533965Sjdp specific instructions before more general instructions. 44633965Sjdp 44733965Sjdp Otherwise, it is sorted by major opcode and minor function code. 44833965Sjdp 44933965Sjdp There are three classes of not-really-instructions in this table: 45033965Sjdp 45133965Sjdp ALIAS is another name for another instruction. Some of 45233965Sjdp these come from the Architecture Handbook, some 45333965Sjdp come from the original gas opcode tables. In all 45433965Sjdp cases, the functionality of the opcode is unchanged. 45533965Sjdp 45633965Sjdp PSEUDO a stylized code form endorsed by Chapter A.4 of the 45733965Sjdp Architecture Handbook. 45833965Sjdp 45933965Sjdp EXTRA a stylized code form found in the original gas tables. 46033965Sjdp 46133965Sjdp And two annotations: 46233965Sjdp 46333965Sjdp EV56 BUT opcodes that are officially introduced as of the ev56, 46433965Sjdp but with defined results on previous implementations. 46533965Sjdp 46633965Sjdp EV56 UNA opcodes that were introduced as of the ev56 with 46733965Sjdp presumably undefined results on previous implementations 468218822Sdim that were not assigned to a particular extension. */ 46933965Sjdp 470218822Sdimconst struct alpha_opcode alpha_opcodes[] = 471218822Sdim{ 47233965Sjdp { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE }, 47333965Sjdp { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE }, 47433965Sjdp { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE }, 475130561Sobrien { "bugchk", SPCD(0x00,0x0081), BASE, ARG_NONE }, 47633965Sjdp { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE }, 47733965Sjdp { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE }, 47833965Sjdp { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE }, 479130561Sobrien { "rduniq", SPCD(0x00,0x009e), BASE, ARG_NONE }, 480130561Sobrien { "wruniq", SPCD(0x00,0x009f), BASE, ARG_NONE }, 481130561Sobrien { "gentrap", SPCD(0x00,0x00aa), BASE, ARG_NONE }, 48233965Sjdp { "call_pal", PCD(0x00), BASE, ARG_PCD }, 48333965Sjdp { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */ 48433965Sjdp 48591041Sobrien { "lda", MEM(0x08), BASE, { RA, MDISP, ZB } }, /* pseudo */ 48633965Sjdp { "lda", MEM(0x08), BASE, ARG_MEM }, 48791041Sobrien { "ldah", MEM(0x09), BASE, { RA, MDISP, ZB } }, /* pseudo */ 48833965Sjdp { "ldah", MEM(0x09), BASE, ARG_MEM }, 48933965Sjdp { "ldbu", MEM(0x0A), BWX, ARG_MEM }, 49089857Sobrien { "unop", MEM_(0x0B) | (30 << 16), 49189857Sobrien MEM_MASK, BASE, { ZA } }, /* pseudo */ 49233965Sjdp { "ldq_u", MEM(0x0B), BASE, ARG_MEM }, 49333965Sjdp { "ldwu", MEM(0x0C), BWX, ARG_MEM }, 49433965Sjdp { "stw", MEM(0x0D), BWX, ARG_MEM }, 49533965Sjdp { "stb", MEM(0x0E), BWX, ARG_MEM }, 49633965Sjdp { "stq_u", MEM(0x0F), BASE, ARG_MEM }, 49733965Sjdp 49833965Sjdp { "sextl", OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */ 49933965Sjdp { "sextl", OPRL(0x10,0x00), BASE, ARG_OPRLZ1 }, /* pseudo */ 50033965Sjdp { "addl", OPR(0x10,0x00), BASE, ARG_OPR }, 50133965Sjdp { "addl", OPRL(0x10,0x00), BASE, ARG_OPRL }, 50233965Sjdp { "s4addl", OPR(0x10,0x02), BASE, ARG_OPR }, 50333965Sjdp { "s4addl", OPRL(0x10,0x02), BASE, ARG_OPRL }, 50433965Sjdp { "negl", OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */ 50533965Sjdp { "negl", OPRL(0x10,0x09), BASE, ARG_OPRLZ1 }, /* pseudo */ 50633965Sjdp { "subl", OPR(0x10,0x09), BASE, ARG_OPR }, 50733965Sjdp { "subl", OPRL(0x10,0x09), BASE, ARG_OPRL }, 50833965Sjdp { "s4subl", OPR(0x10,0x0B), BASE, ARG_OPR }, 50933965Sjdp { "s4subl", OPRL(0x10,0x0B), BASE, ARG_OPRL }, 51033965Sjdp { "cmpbge", OPR(0x10,0x0F), BASE, ARG_OPR }, 51133965Sjdp { "cmpbge", OPRL(0x10,0x0F), BASE, ARG_OPRL }, 51233965Sjdp { "s8addl", OPR(0x10,0x12), BASE, ARG_OPR }, 51333965Sjdp { "s8addl", OPRL(0x10,0x12), BASE, ARG_OPRL }, 51433965Sjdp { "s8subl", OPR(0x10,0x1B), BASE, ARG_OPR }, 51533965Sjdp { "s8subl", OPRL(0x10,0x1B), BASE, ARG_OPRL }, 51633965Sjdp { "cmpult", OPR(0x10,0x1D), BASE, ARG_OPR }, 51733965Sjdp { "cmpult", OPRL(0x10,0x1D), BASE, ARG_OPRL }, 51833965Sjdp { "addq", OPR(0x10,0x20), BASE, ARG_OPR }, 51933965Sjdp { "addq", OPRL(0x10,0x20), BASE, ARG_OPRL }, 52033965Sjdp { "s4addq", OPR(0x10,0x22), BASE, ARG_OPR }, 52133965Sjdp { "s4addq", OPRL(0x10,0x22), BASE, ARG_OPRL }, 52233965Sjdp { "negq", OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */ 52333965Sjdp { "negq", OPRL(0x10,0x29), BASE, ARG_OPRLZ1 }, /* pseudo */ 52433965Sjdp { "subq", OPR(0x10,0x29), BASE, ARG_OPR }, 52533965Sjdp { "subq", OPRL(0x10,0x29), BASE, ARG_OPRL }, 52633965Sjdp { "s4subq", OPR(0x10,0x2B), BASE, ARG_OPR }, 52733965Sjdp { "s4subq", OPRL(0x10,0x2B), BASE, ARG_OPRL }, 52833965Sjdp { "cmpeq", OPR(0x10,0x2D), BASE, ARG_OPR }, 52933965Sjdp { "cmpeq", OPRL(0x10,0x2D), BASE, ARG_OPRL }, 53033965Sjdp { "s8addq", OPR(0x10,0x32), BASE, ARG_OPR }, 53133965Sjdp { "s8addq", OPRL(0x10,0x32), BASE, ARG_OPRL }, 53233965Sjdp { "s8subq", OPR(0x10,0x3B), BASE, ARG_OPR }, 53333965Sjdp { "s8subq", OPRL(0x10,0x3B), BASE, ARG_OPRL }, 53433965Sjdp { "cmpule", OPR(0x10,0x3D), BASE, ARG_OPR }, 53533965Sjdp { "cmpule", OPRL(0x10,0x3D), BASE, ARG_OPRL }, 53633965Sjdp { "addl/v", OPR(0x10,0x40), BASE, ARG_OPR }, 53733965Sjdp { "addl/v", OPRL(0x10,0x40), BASE, ARG_OPRL }, 53833965Sjdp { "negl/v", OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */ 53933965Sjdp { "negl/v", OPRL(0x10,0x49), BASE, ARG_OPRLZ1 }, /* pseudo */ 54033965Sjdp { "subl/v", OPR(0x10,0x49), BASE, ARG_OPR }, 54133965Sjdp { "subl/v", OPRL(0x10,0x49), BASE, ARG_OPRL }, 54233965Sjdp { "cmplt", OPR(0x10,0x4D), BASE, ARG_OPR }, 54333965Sjdp { "cmplt", OPRL(0x10,0x4D), BASE, ARG_OPRL }, 54433965Sjdp { "addq/v", OPR(0x10,0x60), BASE, ARG_OPR }, 54533965Sjdp { "addq/v", OPRL(0x10,0x60), BASE, ARG_OPRL }, 54633965Sjdp { "negq/v", OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */ 54733965Sjdp { "negq/v", OPRL(0x10,0x69), BASE, ARG_OPRLZ1 }, /* pseudo */ 54833965Sjdp { "subq/v", OPR(0x10,0x69), BASE, ARG_OPR }, 54933965Sjdp { "subq/v", OPRL(0x10,0x69), BASE, ARG_OPRL }, 55033965Sjdp { "cmple", OPR(0x10,0x6D), BASE, ARG_OPR }, 55133965Sjdp { "cmple", OPRL(0x10,0x6D), BASE, ARG_OPRL }, 55233965Sjdp 55333965Sjdp { "and", OPR(0x11,0x00), BASE, ARG_OPR }, 55433965Sjdp { "and", OPRL(0x11,0x00), BASE, ARG_OPRL }, 55560484Sobrien { "andnot", OPR(0x11,0x08), BASE, ARG_OPR }, /* alias */ 55633965Sjdp { "andnot", OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */ 55733965Sjdp { "bic", OPR(0x11,0x08), BASE, ARG_OPR }, 55833965Sjdp { "bic", OPRL(0x11,0x08), BASE, ARG_OPRL }, 55933965Sjdp { "cmovlbs", OPR(0x11,0x14), BASE, ARG_OPR }, 56033965Sjdp { "cmovlbs", OPRL(0x11,0x14), BASE, ARG_OPRL }, 56133965Sjdp { "cmovlbc", OPR(0x11,0x16), BASE, ARG_OPR }, 56233965Sjdp { "cmovlbc", OPRL(0x11,0x16), BASE, ARG_OPRL }, 56333965Sjdp { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */ 56433965Sjdp { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */ 56533965Sjdp { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */ 56633965Sjdp { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */ 56733965Sjdp { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */ 56860484Sobrien { "or", OPR(0x11,0x20), BASE, ARG_OPR }, /* alias */ 56933965Sjdp { "or", OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */ 57033965Sjdp { "bis", OPR(0x11,0x20), BASE, ARG_OPR }, 57133965Sjdp { "bis", OPRL(0x11,0x20), BASE, ARG_OPRL }, 57233965Sjdp { "cmoveq", OPR(0x11,0x24), BASE, ARG_OPR }, 57333965Sjdp { "cmoveq", OPRL(0x11,0x24), BASE, ARG_OPRL }, 57433965Sjdp { "cmovne", OPR(0x11,0x26), BASE, ARG_OPR }, 57533965Sjdp { "cmovne", OPRL(0x11,0x26), BASE, ARG_OPRL }, 57633965Sjdp { "not", OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */ 57733965Sjdp { "not", OPRL(0x11,0x28), BASE, ARG_OPRLZ1 }, /* pseudo */ 57833965Sjdp { "ornot", OPR(0x11,0x28), BASE, ARG_OPR }, 57933965Sjdp { "ornot", OPRL(0x11,0x28), BASE, ARG_OPRL }, 58033965Sjdp { "xor", OPR(0x11,0x40), BASE, ARG_OPR }, 58133965Sjdp { "xor", OPRL(0x11,0x40), BASE, ARG_OPRL }, 58233965Sjdp { "cmovlt", OPR(0x11,0x44), BASE, ARG_OPR }, 58333965Sjdp { "cmovlt", OPRL(0x11,0x44), BASE, ARG_OPRL }, 58433965Sjdp { "cmovge", OPR(0x11,0x46), BASE, ARG_OPR }, 58533965Sjdp { "cmovge", OPRL(0x11,0x46), BASE, ARG_OPRL }, 58633965Sjdp { "eqv", OPR(0x11,0x48), BASE, ARG_OPR }, 58733965Sjdp { "eqv", OPRL(0x11,0x48), BASE, ARG_OPRL }, 58833965Sjdp { "xornot", OPR(0x11,0x48), BASE, ARG_OPR }, /* alias */ 58933965Sjdp { "xornot", OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */ 59033965Sjdp { "amask", OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */ 59133965Sjdp { "amask", OPRL(0x11,0x61), BASE, ARG_OPRLZ1 }, /* ev56 but */ 59233965Sjdp { "cmovle", OPR(0x11,0x64), BASE, ARG_OPR }, 59333965Sjdp { "cmovle", OPRL(0x11,0x64), BASE, ARG_OPRL }, 59433965Sjdp { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR }, 59533965Sjdp { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL }, 59633965Sjdp { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13), 59733965Sjdp 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */ 59833965Sjdp 59933965Sjdp { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR }, 60033965Sjdp { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL }, 60133965Sjdp { "extbl", OPR(0x12,0x06), BASE, ARG_OPR }, 60233965Sjdp { "extbl", OPRL(0x12,0x06), BASE, ARG_OPRL }, 60333965Sjdp { "insbl", OPR(0x12,0x0B), BASE, ARG_OPR }, 60433965Sjdp { "insbl", OPRL(0x12,0x0B), BASE, ARG_OPRL }, 60533965Sjdp { "mskwl", OPR(0x12,0x12), BASE, ARG_OPR }, 60633965Sjdp { "mskwl", OPRL(0x12,0x12), BASE, ARG_OPRL }, 60733965Sjdp { "extwl", OPR(0x12,0x16), BASE, ARG_OPR }, 60833965Sjdp { "extwl", OPRL(0x12,0x16), BASE, ARG_OPRL }, 60933965Sjdp { "inswl", OPR(0x12,0x1B), BASE, ARG_OPR }, 61033965Sjdp { "inswl", OPRL(0x12,0x1B), BASE, ARG_OPRL }, 61133965Sjdp { "mskll", OPR(0x12,0x22), BASE, ARG_OPR }, 61233965Sjdp { "mskll", OPRL(0x12,0x22), BASE, ARG_OPRL }, 61333965Sjdp { "extll", OPR(0x12,0x26), BASE, ARG_OPR }, 61433965Sjdp { "extll", OPRL(0x12,0x26), BASE, ARG_OPRL }, 61533965Sjdp { "insll", OPR(0x12,0x2B), BASE, ARG_OPR }, 61633965Sjdp { "insll", OPRL(0x12,0x2B), BASE, ARG_OPRL }, 61733965Sjdp { "zap", OPR(0x12,0x30), BASE, ARG_OPR }, 61833965Sjdp { "zap", OPRL(0x12,0x30), BASE, ARG_OPRL }, 61933965Sjdp { "zapnot", OPR(0x12,0x31), BASE, ARG_OPR }, 62033965Sjdp { "zapnot", OPRL(0x12,0x31), BASE, ARG_OPRL }, 62133965Sjdp { "mskql", OPR(0x12,0x32), BASE, ARG_OPR }, 62233965Sjdp { "mskql", OPRL(0x12,0x32), BASE, ARG_OPRL }, 62333965Sjdp { "srl", OPR(0x12,0x34), BASE, ARG_OPR }, 62433965Sjdp { "srl", OPRL(0x12,0x34), BASE, ARG_OPRL }, 62533965Sjdp { "extql", OPR(0x12,0x36), BASE, ARG_OPR }, 62633965Sjdp { "extql", OPRL(0x12,0x36), BASE, ARG_OPRL }, 62733965Sjdp { "sll", OPR(0x12,0x39), BASE, ARG_OPR }, 62833965Sjdp { "sll", OPRL(0x12,0x39), BASE, ARG_OPRL }, 62933965Sjdp { "insql", OPR(0x12,0x3B), BASE, ARG_OPR }, 63033965Sjdp { "insql", OPRL(0x12,0x3B), BASE, ARG_OPRL }, 63133965Sjdp { "sra", OPR(0x12,0x3C), BASE, ARG_OPR }, 63233965Sjdp { "sra", OPRL(0x12,0x3C), BASE, ARG_OPRL }, 63333965Sjdp { "mskwh", OPR(0x12,0x52), BASE, ARG_OPR }, 63433965Sjdp { "mskwh", OPRL(0x12,0x52), BASE, ARG_OPRL }, 63533965Sjdp { "inswh", OPR(0x12,0x57), BASE, ARG_OPR }, 63633965Sjdp { "inswh", OPRL(0x12,0x57), BASE, ARG_OPRL }, 63733965Sjdp { "extwh", OPR(0x12,0x5A), BASE, ARG_OPR }, 63833965Sjdp { "extwh", OPRL(0x12,0x5A), BASE, ARG_OPRL }, 63933965Sjdp { "msklh", OPR(0x12,0x62), BASE, ARG_OPR }, 64033965Sjdp { "msklh", OPRL(0x12,0x62), BASE, ARG_OPRL }, 64133965Sjdp { "inslh", OPR(0x12,0x67), BASE, ARG_OPR }, 64233965Sjdp { "inslh", OPRL(0x12,0x67), BASE, ARG_OPRL }, 64333965Sjdp { "extlh", OPR(0x12,0x6A), BASE, ARG_OPR }, 64433965Sjdp { "extlh", OPRL(0x12,0x6A), BASE, ARG_OPRL }, 64533965Sjdp { "mskqh", OPR(0x12,0x72), BASE, ARG_OPR }, 64633965Sjdp { "mskqh", OPRL(0x12,0x72), BASE, ARG_OPRL }, 64733965Sjdp { "insqh", OPR(0x12,0x77), BASE, ARG_OPR }, 64833965Sjdp { "insqh", OPRL(0x12,0x77), BASE, ARG_OPRL }, 64933965Sjdp { "extqh", OPR(0x12,0x7A), BASE, ARG_OPR }, 65033965Sjdp { "extqh", OPRL(0x12,0x7A), BASE, ARG_OPRL }, 65133965Sjdp 65233965Sjdp { "mull", OPR(0x13,0x00), BASE, ARG_OPR }, 65333965Sjdp { "mull", OPRL(0x13,0x00), BASE, ARG_OPRL }, 65433965Sjdp { "mulq", OPR(0x13,0x20), BASE, ARG_OPR }, 65533965Sjdp { "mulq", OPRL(0x13,0x20), BASE, ARG_OPRL }, 65633965Sjdp { "umulh", OPR(0x13,0x30), BASE, ARG_OPR }, 65733965Sjdp { "umulh", OPRL(0x13,0x30), BASE, ARG_OPRL }, 65833965Sjdp { "mull/v", OPR(0x13,0x40), BASE, ARG_OPR }, 65933965Sjdp { "mull/v", OPRL(0x13,0x40), BASE, ARG_OPRL }, 66033965Sjdp { "mulq/v", OPR(0x13,0x60), BASE, ARG_OPR }, 66133965Sjdp { "mulq/v", OPRL(0x13,0x60), BASE, ARG_OPRL }, 66233965Sjdp 66333965Sjdp { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } }, 66460484Sobrien { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 }, 66560484Sobrien { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 }, 66633965Sjdp { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } }, 66733965Sjdp { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } }, 66860484Sobrien { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 }, 66960484Sobrien { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 }, 67060484Sobrien { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 }, 67160484Sobrien { "sqrtt/m", FP(0x14,0x06B), CIX, ARG_FPZ1 }, 67233965Sjdp { "sqrtf", FP(0x14,0x08A), CIX, ARG_FPZ1 }, 67360484Sobrien { "sqrts", FP(0x14,0x08B), CIX, ARG_FPZ1 }, 67433965Sjdp { "sqrtg", FP(0x14,0x0AA), CIX, ARG_FPZ1 }, 67533965Sjdp { "sqrtt", FP(0x14,0x0AB), CIX, ARG_FPZ1 }, 67660484Sobrien { "sqrts/d", FP(0x14,0x0CB), CIX, ARG_FPZ1 }, 67760484Sobrien { "sqrtt/d", FP(0x14,0x0EB), CIX, ARG_FPZ1 }, 67860484Sobrien { "sqrtf/uc", FP(0x14,0x10A), CIX, ARG_FPZ1 }, 67960484Sobrien { "sqrts/uc", FP(0x14,0x10B), CIX, ARG_FPZ1 }, 68060484Sobrien { "sqrtg/uc", FP(0x14,0x12A), CIX, ARG_FPZ1 }, 68160484Sobrien { "sqrtt/uc", FP(0x14,0x12B), CIX, ARG_FPZ1 }, 68260484Sobrien { "sqrts/um", FP(0x14,0x14B), CIX, ARG_FPZ1 }, 68360484Sobrien { "sqrtt/um", FP(0x14,0x16B), CIX, ARG_FPZ1 }, 68460484Sobrien { "sqrtf/u", FP(0x14,0x18A), CIX, ARG_FPZ1 }, 68560484Sobrien { "sqrts/u", FP(0x14,0x18B), CIX, ARG_FPZ1 }, 68660484Sobrien { "sqrtg/u", FP(0x14,0x1AA), CIX, ARG_FPZ1 }, 68760484Sobrien { "sqrtt/u", FP(0x14,0x1AB), CIX, ARG_FPZ1 }, 68860484Sobrien { "sqrts/ud", FP(0x14,0x1CB), CIX, ARG_FPZ1 }, 68960484Sobrien { "sqrtt/ud", FP(0x14,0x1EB), CIX, ARG_FPZ1 }, 69060484Sobrien { "sqrtf/sc", FP(0x14,0x40A), CIX, ARG_FPZ1 }, 69160484Sobrien { "sqrtg/sc", FP(0x14,0x42A), CIX, ARG_FPZ1 }, 69260484Sobrien { "sqrtf/s", FP(0x14,0x48A), CIX, ARG_FPZ1 }, 69360484Sobrien { "sqrtg/s", FP(0x14,0x4AA), CIX, ARG_FPZ1 }, 69460484Sobrien { "sqrtf/suc", FP(0x14,0x50A), CIX, ARG_FPZ1 }, 69560484Sobrien { "sqrts/suc", FP(0x14,0x50B), CIX, ARG_FPZ1 }, 69660484Sobrien { "sqrtg/suc", FP(0x14,0x52A), CIX, ARG_FPZ1 }, 69760484Sobrien { "sqrtt/suc", FP(0x14,0x52B), CIX, ARG_FPZ1 }, 69860484Sobrien { "sqrts/sum", FP(0x14,0x54B), CIX, ARG_FPZ1 }, 69960484Sobrien { "sqrtt/sum", FP(0x14,0x56B), CIX, ARG_FPZ1 }, 70060484Sobrien { "sqrtf/su", FP(0x14,0x58A), CIX, ARG_FPZ1 }, 70160484Sobrien { "sqrts/su", FP(0x14,0x58B), CIX, ARG_FPZ1 }, 70260484Sobrien { "sqrtg/su", FP(0x14,0x5AA), CIX, ARG_FPZ1 }, 70360484Sobrien { "sqrtt/su", FP(0x14,0x5AB), CIX, ARG_FPZ1 }, 70460484Sobrien { "sqrts/sud", FP(0x14,0x5CB), CIX, ARG_FPZ1 }, 70560484Sobrien { "sqrtt/sud", FP(0x14,0x5EB), CIX, ARG_FPZ1 }, 70660484Sobrien { "sqrts/suic", FP(0x14,0x70B), CIX, ARG_FPZ1 }, 70760484Sobrien { "sqrtt/suic", FP(0x14,0x72B), CIX, ARG_FPZ1 }, 70860484Sobrien { "sqrts/suim", FP(0x14,0x74B), CIX, ARG_FPZ1 }, 70960484Sobrien { "sqrtt/suim", FP(0x14,0x76B), CIX, ARG_FPZ1 }, 71060484Sobrien { "sqrts/sui", FP(0x14,0x78B), CIX, ARG_FPZ1 }, 71160484Sobrien { "sqrtt/sui", FP(0x14,0x7AB), CIX, ARG_FPZ1 }, 71260484Sobrien { "sqrts/suid", FP(0x14,0x7CB), CIX, ARG_FPZ1 }, 71360484Sobrien { "sqrtt/suid", FP(0x14,0x7EB), CIX, ARG_FPZ1 }, 71433965Sjdp 71533965Sjdp { "addf/c", FP(0x15,0x000), BASE, ARG_FP }, 71633965Sjdp { "subf/c", FP(0x15,0x001), BASE, ARG_FP }, 71733965Sjdp { "mulf/c", FP(0x15,0x002), BASE, ARG_FP }, 71833965Sjdp { "divf/c", FP(0x15,0x003), BASE, ARG_FP }, 71933965Sjdp { "cvtdg/c", FP(0x15,0x01E), BASE, ARG_FPZ1 }, 72033965Sjdp { "addg/c", FP(0x15,0x020), BASE, ARG_FP }, 72133965Sjdp { "subg/c", FP(0x15,0x021), BASE, ARG_FP }, 72233965Sjdp { "mulg/c", FP(0x15,0x022), BASE, ARG_FP }, 72333965Sjdp { "divg/c", FP(0x15,0x023), BASE, ARG_FP }, 72433965Sjdp { "cvtgf/c", FP(0x15,0x02C), BASE, ARG_FPZ1 }, 72533965Sjdp { "cvtgd/c", FP(0x15,0x02D), BASE, ARG_FPZ1 }, 72633965Sjdp { "cvtgq/c", FP(0x15,0x02F), BASE, ARG_FPZ1 }, 72733965Sjdp { "cvtqf/c", FP(0x15,0x03C), BASE, ARG_FPZ1 }, 72833965Sjdp { "cvtqg/c", FP(0x15,0x03E), BASE, ARG_FPZ1 }, 72933965Sjdp { "addf", FP(0x15,0x080), BASE, ARG_FP }, 73033965Sjdp { "negf", FP(0x15,0x081), BASE, ARG_FPZ1 }, /* pseudo */ 73133965Sjdp { "subf", FP(0x15,0x081), BASE, ARG_FP }, 73233965Sjdp { "mulf", FP(0x15,0x082), BASE, ARG_FP }, 73333965Sjdp { "divf", FP(0x15,0x083), BASE, ARG_FP }, 73433965Sjdp { "cvtdg", FP(0x15,0x09E), BASE, ARG_FPZ1 }, 73533965Sjdp { "addg", FP(0x15,0x0A0), BASE, ARG_FP }, 73633965Sjdp { "negg", FP(0x15,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ 73733965Sjdp { "subg", FP(0x15,0x0A1), BASE, ARG_FP }, 73833965Sjdp { "mulg", FP(0x15,0x0A2), BASE, ARG_FP }, 73933965Sjdp { "divg", FP(0x15,0x0A3), BASE, ARG_FP }, 74033965Sjdp { "cmpgeq", FP(0x15,0x0A5), BASE, ARG_FP }, 74133965Sjdp { "cmpglt", FP(0x15,0x0A6), BASE, ARG_FP }, 74233965Sjdp { "cmpgle", FP(0x15,0x0A7), BASE, ARG_FP }, 74333965Sjdp { "cvtgf", FP(0x15,0x0AC), BASE, ARG_FPZ1 }, 74433965Sjdp { "cvtgd", FP(0x15,0x0AD), BASE, ARG_FPZ1 }, 74533965Sjdp { "cvtgq", FP(0x15,0x0AF), BASE, ARG_FPZ1 }, 74633965Sjdp { "cvtqf", FP(0x15,0x0BC), BASE, ARG_FPZ1 }, 74733965Sjdp { "cvtqg", FP(0x15,0x0BE), BASE, ARG_FPZ1 }, 74833965Sjdp { "addf/uc", FP(0x15,0x100), BASE, ARG_FP }, 74933965Sjdp { "subf/uc", FP(0x15,0x101), BASE, ARG_FP }, 75033965Sjdp { "mulf/uc", FP(0x15,0x102), BASE, ARG_FP }, 75133965Sjdp { "divf/uc", FP(0x15,0x103), BASE, ARG_FP }, 75233965Sjdp { "cvtdg/uc", FP(0x15,0x11E), BASE, ARG_FPZ1 }, 75333965Sjdp { "addg/uc", FP(0x15,0x120), BASE, ARG_FP }, 75433965Sjdp { "subg/uc", FP(0x15,0x121), BASE, ARG_FP }, 75533965Sjdp { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP }, 75633965Sjdp { "divg/uc", FP(0x15,0x123), BASE, ARG_FP }, 75733965Sjdp { "cvtgf/uc", FP(0x15,0x12C), BASE, ARG_FPZ1 }, 75833965Sjdp { "cvtgd/uc", FP(0x15,0x12D), BASE, ARG_FPZ1 }, 75933965Sjdp { "cvtgq/vc", FP(0x15,0x12F), BASE, ARG_FPZ1 }, 76033965Sjdp { "addf/u", FP(0x15,0x180), BASE, ARG_FP }, 76133965Sjdp { "subf/u", FP(0x15,0x181), BASE, ARG_FP }, 76233965Sjdp { "mulf/u", FP(0x15,0x182), BASE, ARG_FP }, 76333965Sjdp { "divf/u", FP(0x15,0x183), BASE, ARG_FP }, 76433965Sjdp { "cvtdg/u", FP(0x15,0x19E), BASE, ARG_FPZ1 }, 76533965Sjdp { "addg/u", FP(0x15,0x1A0), BASE, ARG_FP }, 76633965Sjdp { "subg/u", FP(0x15,0x1A1), BASE, ARG_FP }, 76733965Sjdp { "mulg/u", FP(0x15,0x1A2), BASE, ARG_FP }, 76833965Sjdp { "divg/u", FP(0x15,0x1A3), BASE, ARG_FP }, 76933965Sjdp { "cvtgf/u", FP(0x15,0x1AC), BASE, ARG_FPZ1 }, 77033965Sjdp { "cvtgd/u", FP(0x15,0x1AD), BASE, ARG_FPZ1 }, 77133965Sjdp { "cvtgq/v", FP(0x15,0x1AF), BASE, ARG_FPZ1 }, 77233965Sjdp { "addf/sc", FP(0x15,0x400), BASE, ARG_FP }, 77333965Sjdp { "subf/sc", FP(0x15,0x401), BASE, ARG_FP }, 77433965Sjdp { "mulf/sc", FP(0x15,0x402), BASE, ARG_FP }, 77533965Sjdp { "divf/sc", FP(0x15,0x403), BASE, ARG_FP }, 77633965Sjdp { "cvtdg/sc", FP(0x15,0x41E), BASE, ARG_FPZ1 }, 77733965Sjdp { "addg/sc", FP(0x15,0x420), BASE, ARG_FP }, 77833965Sjdp { "subg/sc", FP(0x15,0x421), BASE, ARG_FP }, 77933965Sjdp { "mulg/sc", FP(0x15,0x422), BASE, ARG_FP }, 78033965Sjdp { "divg/sc", FP(0x15,0x423), BASE, ARG_FP }, 78133965Sjdp { "cvtgf/sc", FP(0x15,0x42C), BASE, ARG_FPZ1 }, 78233965Sjdp { "cvtgd/sc", FP(0x15,0x42D), BASE, ARG_FPZ1 }, 78333965Sjdp { "cvtgq/sc", FP(0x15,0x42F), BASE, ARG_FPZ1 }, 78433965Sjdp { "addf/s", FP(0x15,0x480), BASE, ARG_FP }, 78533965Sjdp { "negf/s", FP(0x15,0x481), BASE, ARG_FPZ1 }, /* pseudo */ 78633965Sjdp { "subf/s", FP(0x15,0x481), BASE, ARG_FP }, 78733965Sjdp { "mulf/s", FP(0x15,0x482), BASE, ARG_FP }, 78833965Sjdp { "divf/s", FP(0x15,0x483), BASE, ARG_FP }, 78933965Sjdp { "cvtdg/s", FP(0x15,0x49E), BASE, ARG_FPZ1 }, 79033965Sjdp { "addg/s", FP(0x15,0x4A0), BASE, ARG_FP }, 79133965Sjdp { "negg/s", FP(0x15,0x4A1), BASE, ARG_FPZ1 }, /* pseudo */ 79233965Sjdp { "subg/s", FP(0x15,0x4A1), BASE, ARG_FP }, 79333965Sjdp { "mulg/s", FP(0x15,0x4A2), BASE, ARG_FP }, 79433965Sjdp { "divg/s", FP(0x15,0x4A3), BASE, ARG_FP }, 79533965Sjdp { "cmpgeq/s", FP(0x15,0x4A5), BASE, ARG_FP }, 79633965Sjdp { "cmpglt/s", FP(0x15,0x4A6), BASE, ARG_FP }, 79733965Sjdp { "cmpgle/s", FP(0x15,0x4A7), BASE, ARG_FP }, 79833965Sjdp { "cvtgf/s", FP(0x15,0x4AC), BASE, ARG_FPZ1 }, 79933965Sjdp { "cvtgd/s", FP(0x15,0x4AD), BASE, ARG_FPZ1 }, 80033965Sjdp { "cvtgq/s", FP(0x15,0x4AF), BASE, ARG_FPZ1 }, 80133965Sjdp { "addf/suc", FP(0x15,0x500), BASE, ARG_FP }, 80233965Sjdp { "subf/suc", FP(0x15,0x501), BASE, ARG_FP }, 80333965Sjdp { "mulf/suc", FP(0x15,0x502), BASE, ARG_FP }, 80433965Sjdp { "divf/suc", FP(0x15,0x503), BASE, ARG_FP }, 80533965Sjdp { "cvtdg/suc", FP(0x15,0x51E), BASE, ARG_FPZ1 }, 80633965Sjdp { "addg/suc", FP(0x15,0x520), BASE, ARG_FP }, 80733965Sjdp { "subg/suc", FP(0x15,0x521), BASE, ARG_FP }, 80833965Sjdp { "mulg/suc", FP(0x15,0x522), BASE, ARG_FP }, 80933965Sjdp { "divg/suc", FP(0x15,0x523), BASE, ARG_FP }, 81033965Sjdp { "cvtgf/suc", FP(0x15,0x52C), BASE, ARG_FPZ1 }, 81133965Sjdp { "cvtgd/suc", FP(0x15,0x52D), BASE, ARG_FPZ1 }, 81233965Sjdp { "cvtgq/svc", FP(0x15,0x52F), BASE, ARG_FPZ1 }, 81333965Sjdp { "addf/su", FP(0x15,0x580), BASE, ARG_FP }, 81433965Sjdp { "subf/su", FP(0x15,0x581), BASE, ARG_FP }, 81533965Sjdp { "mulf/su", FP(0x15,0x582), BASE, ARG_FP }, 81633965Sjdp { "divf/su", FP(0x15,0x583), BASE, ARG_FP }, 81733965Sjdp { "cvtdg/su", FP(0x15,0x59E), BASE, ARG_FPZ1 }, 81833965Sjdp { "addg/su", FP(0x15,0x5A0), BASE, ARG_FP }, 81933965Sjdp { "subg/su", FP(0x15,0x5A1), BASE, ARG_FP }, 82033965Sjdp { "mulg/su", FP(0x15,0x5A2), BASE, ARG_FP }, 82133965Sjdp { "divg/su", FP(0x15,0x5A3), BASE, ARG_FP }, 82233965Sjdp { "cvtgf/su", FP(0x15,0x5AC), BASE, ARG_FPZ1 }, 82333965Sjdp { "cvtgd/su", FP(0x15,0x5AD), BASE, ARG_FPZ1 }, 82433965Sjdp { "cvtgq/sv", FP(0x15,0x5AF), BASE, ARG_FPZ1 }, 82533965Sjdp 82633965Sjdp { "adds/c", FP(0x16,0x000), BASE, ARG_FP }, 82733965Sjdp { "subs/c", FP(0x16,0x001), BASE, ARG_FP }, 82833965Sjdp { "muls/c", FP(0x16,0x002), BASE, ARG_FP }, 82933965Sjdp { "divs/c", FP(0x16,0x003), BASE, ARG_FP }, 83033965Sjdp { "addt/c", FP(0x16,0x020), BASE, ARG_FP }, 83133965Sjdp { "subt/c", FP(0x16,0x021), BASE, ARG_FP }, 83233965Sjdp { "mult/c", FP(0x16,0x022), BASE, ARG_FP }, 83333965Sjdp { "divt/c", FP(0x16,0x023), BASE, ARG_FP }, 83433965Sjdp { "cvtts/c", FP(0x16,0x02C), BASE, ARG_FPZ1 }, 83533965Sjdp { "cvttq/c", FP(0x16,0x02F), BASE, ARG_FPZ1 }, 83633965Sjdp { "cvtqs/c", FP(0x16,0x03C), BASE, ARG_FPZ1 }, 83733965Sjdp { "cvtqt/c", FP(0x16,0x03E), BASE, ARG_FPZ1 }, 83833965Sjdp { "adds/m", FP(0x16,0x040), BASE, ARG_FP }, 83933965Sjdp { "subs/m", FP(0x16,0x041), BASE, ARG_FP }, 84033965Sjdp { "muls/m", FP(0x16,0x042), BASE, ARG_FP }, 84133965Sjdp { "divs/m", FP(0x16,0x043), BASE, ARG_FP }, 84233965Sjdp { "addt/m", FP(0x16,0x060), BASE, ARG_FP }, 84333965Sjdp { "subt/m", FP(0x16,0x061), BASE, ARG_FP }, 84433965Sjdp { "mult/m", FP(0x16,0x062), BASE, ARG_FP }, 84533965Sjdp { "divt/m", FP(0x16,0x063), BASE, ARG_FP }, 84633965Sjdp { "cvtts/m", FP(0x16,0x06C), BASE, ARG_FPZ1 }, 84733965Sjdp { "cvttq/m", FP(0x16,0x06F), BASE, ARG_FPZ1 }, 84833965Sjdp { "cvtqs/m", FP(0x16,0x07C), BASE, ARG_FPZ1 }, 84933965Sjdp { "cvtqt/m", FP(0x16,0x07E), BASE, ARG_FPZ1 }, 85033965Sjdp { "adds", FP(0x16,0x080), BASE, ARG_FP }, 85133965Sjdp { "negs", FP(0x16,0x081), BASE, ARG_FPZ1 }, /* pseudo */ 85233965Sjdp { "subs", FP(0x16,0x081), BASE, ARG_FP }, 85333965Sjdp { "muls", FP(0x16,0x082), BASE, ARG_FP }, 85433965Sjdp { "divs", FP(0x16,0x083), BASE, ARG_FP }, 85533965Sjdp { "addt", FP(0x16,0x0A0), BASE, ARG_FP }, 85633965Sjdp { "negt", FP(0x16,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ 85733965Sjdp { "subt", FP(0x16,0x0A1), BASE, ARG_FP }, 85833965Sjdp { "mult", FP(0x16,0x0A2), BASE, ARG_FP }, 85933965Sjdp { "divt", FP(0x16,0x0A3), BASE, ARG_FP }, 86033965Sjdp { "cmptun", FP(0x16,0x0A4), BASE, ARG_FP }, 86133965Sjdp { "cmpteq", FP(0x16,0x0A5), BASE, ARG_FP }, 86233965Sjdp { "cmptlt", FP(0x16,0x0A6), BASE, ARG_FP }, 86333965Sjdp { "cmptle", FP(0x16,0x0A7), BASE, ARG_FP }, 86433965Sjdp { "cvtts", FP(0x16,0x0AC), BASE, ARG_FPZ1 }, 86533965Sjdp { "cvttq", FP(0x16,0x0AF), BASE, ARG_FPZ1 }, 86633965Sjdp { "cvtqs", FP(0x16,0x0BC), BASE, ARG_FPZ1 }, 86733965Sjdp { "cvtqt", FP(0x16,0x0BE), BASE, ARG_FPZ1 }, 86833965Sjdp { "adds/d", FP(0x16,0x0C0), BASE, ARG_FP }, 86933965Sjdp { "subs/d", FP(0x16,0x0C1), BASE, ARG_FP }, 87033965Sjdp { "muls/d", FP(0x16,0x0C2), BASE, ARG_FP }, 87133965Sjdp { "divs/d", FP(0x16,0x0C3), BASE, ARG_FP }, 87233965Sjdp { "addt/d", FP(0x16,0x0E0), BASE, ARG_FP }, 87333965Sjdp { "subt/d", FP(0x16,0x0E1), BASE, ARG_FP }, 87433965Sjdp { "mult/d", FP(0x16,0x0E2), BASE, ARG_FP }, 87533965Sjdp { "divt/d", FP(0x16,0x0E3), BASE, ARG_FP }, 87633965Sjdp { "cvtts/d", FP(0x16,0x0EC), BASE, ARG_FPZ1 }, 87733965Sjdp { "cvttq/d", FP(0x16,0x0EF), BASE, ARG_FPZ1 }, 87833965Sjdp { "cvtqs/d", FP(0x16,0x0FC), BASE, ARG_FPZ1 }, 87933965Sjdp { "cvtqt/d", FP(0x16,0x0FE), BASE, ARG_FPZ1 }, 88033965Sjdp { "adds/uc", FP(0x16,0x100), BASE, ARG_FP }, 88133965Sjdp { "subs/uc", FP(0x16,0x101), BASE, ARG_FP }, 88233965Sjdp { "muls/uc", FP(0x16,0x102), BASE, ARG_FP }, 88333965Sjdp { "divs/uc", FP(0x16,0x103), BASE, ARG_FP }, 88433965Sjdp { "addt/uc", FP(0x16,0x120), BASE, ARG_FP }, 88533965Sjdp { "subt/uc", FP(0x16,0x121), BASE, ARG_FP }, 88633965Sjdp { "mult/uc", FP(0x16,0x122), BASE, ARG_FP }, 88733965Sjdp { "divt/uc", FP(0x16,0x123), BASE, ARG_FP }, 88833965Sjdp { "cvtts/uc", FP(0x16,0x12C), BASE, ARG_FPZ1 }, 88933965Sjdp { "cvttq/vc", FP(0x16,0x12F), BASE, ARG_FPZ1 }, 89033965Sjdp { "adds/um", FP(0x16,0x140), BASE, ARG_FP }, 89133965Sjdp { "subs/um", FP(0x16,0x141), BASE, ARG_FP }, 89233965Sjdp { "muls/um", FP(0x16,0x142), BASE, ARG_FP }, 89333965Sjdp { "divs/um", FP(0x16,0x143), BASE, ARG_FP }, 89433965Sjdp { "addt/um", FP(0x16,0x160), BASE, ARG_FP }, 89533965Sjdp { "subt/um", FP(0x16,0x161), BASE, ARG_FP }, 89633965Sjdp { "mult/um", FP(0x16,0x162), BASE, ARG_FP }, 89733965Sjdp { "divt/um", FP(0x16,0x163), BASE, ARG_FP }, 89833965Sjdp { "cvtts/um", FP(0x16,0x16C), BASE, ARG_FPZ1 }, 89938889Sjdp { "cvttq/vm", FP(0x16,0x16F), BASE, ARG_FPZ1 }, 90033965Sjdp { "adds/u", FP(0x16,0x180), BASE, ARG_FP }, 90133965Sjdp { "subs/u", FP(0x16,0x181), BASE, ARG_FP }, 90233965Sjdp { "muls/u", FP(0x16,0x182), BASE, ARG_FP }, 90333965Sjdp { "divs/u", FP(0x16,0x183), BASE, ARG_FP }, 90433965Sjdp { "addt/u", FP(0x16,0x1A0), BASE, ARG_FP }, 90533965Sjdp { "subt/u", FP(0x16,0x1A1), BASE, ARG_FP }, 90633965Sjdp { "mult/u", FP(0x16,0x1A2), BASE, ARG_FP }, 90733965Sjdp { "divt/u", FP(0x16,0x1A3), BASE, ARG_FP }, 90833965Sjdp { "cvtts/u", FP(0x16,0x1AC), BASE, ARG_FPZ1 }, 90933965Sjdp { "cvttq/v", FP(0x16,0x1AF), BASE, ARG_FPZ1 }, 91033965Sjdp { "adds/ud", FP(0x16,0x1C0), BASE, ARG_FP }, 91133965Sjdp { "subs/ud", FP(0x16,0x1C1), BASE, ARG_FP }, 91233965Sjdp { "muls/ud", FP(0x16,0x1C2), BASE, ARG_FP }, 91333965Sjdp { "divs/ud", FP(0x16,0x1C3), BASE, ARG_FP }, 91433965Sjdp { "addt/ud", FP(0x16,0x1E0), BASE, ARG_FP }, 91533965Sjdp { "subt/ud", FP(0x16,0x1E1), BASE, ARG_FP }, 91633965Sjdp { "mult/ud", FP(0x16,0x1E2), BASE, ARG_FP }, 91733965Sjdp { "divt/ud", FP(0x16,0x1E3), BASE, ARG_FP }, 91833965Sjdp { "cvtts/ud", FP(0x16,0x1EC), BASE, ARG_FPZ1 }, 91938889Sjdp { "cvttq/vd", FP(0x16,0x1EF), BASE, ARG_FPZ1 }, 92033965Sjdp { "cvtst", FP(0x16,0x2AC), BASE, ARG_FPZ1 }, 92133965Sjdp { "adds/suc", FP(0x16,0x500), BASE, ARG_FP }, 92233965Sjdp { "subs/suc", FP(0x16,0x501), BASE, ARG_FP }, 92333965Sjdp { "muls/suc", FP(0x16,0x502), BASE, ARG_FP }, 92433965Sjdp { "divs/suc", FP(0x16,0x503), BASE, ARG_FP }, 92533965Sjdp { "addt/suc", FP(0x16,0x520), BASE, ARG_FP }, 92633965Sjdp { "subt/suc", FP(0x16,0x521), BASE, ARG_FP }, 92733965Sjdp { "mult/suc", FP(0x16,0x522), BASE, ARG_FP }, 92833965Sjdp { "divt/suc", FP(0x16,0x523), BASE, ARG_FP }, 92933965Sjdp { "cvtts/suc", FP(0x16,0x52C), BASE, ARG_FPZ1 }, 93033965Sjdp { "cvttq/svc", FP(0x16,0x52F), BASE, ARG_FPZ1 }, 93133965Sjdp { "adds/sum", FP(0x16,0x540), BASE, ARG_FP }, 93233965Sjdp { "subs/sum", FP(0x16,0x541), BASE, ARG_FP }, 93333965Sjdp { "muls/sum", FP(0x16,0x542), BASE, ARG_FP }, 93433965Sjdp { "divs/sum", FP(0x16,0x543), BASE, ARG_FP }, 93533965Sjdp { "addt/sum", FP(0x16,0x560), BASE, ARG_FP }, 93633965Sjdp { "subt/sum", FP(0x16,0x561), BASE, ARG_FP }, 93733965Sjdp { "mult/sum", FP(0x16,0x562), BASE, ARG_FP }, 93833965Sjdp { "divt/sum", FP(0x16,0x563), BASE, ARG_FP }, 93933965Sjdp { "cvtts/sum", FP(0x16,0x56C), BASE, ARG_FPZ1 }, 94038889Sjdp { "cvttq/svm", FP(0x16,0x56F), BASE, ARG_FPZ1 }, 94133965Sjdp { "adds/su", FP(0x16,0x580), BASE, ARG_FP }, 94233965Sjdp { "negs/su", FP(0x16,0x581), BASE, ARG_FPZ1 }, /* pseudo */ 94333965Sjdp { "subs/su", FP(0x16,0x581), BASE, ARG_FP }, 94433965Sjdp { "muls/su", FP(0x16,0x582), BASE, ARG_FP }, 94533965Sjdp { "divs/su", FP(0x16,0x583), BASE, ARG_FP }, 94633965Sjdp { "addt/su", FP(0x16,0x5A0), BASE, ARG_FP }, 94733965Sjdp { "negt/su", FP(0x16,0x5A1), BASE, ARG_FPZ1 }, /* pseudo */ 94833965Sjdp { "subt/su", FP(0x16,0x5A1), BASE, ARG_FP }, 94933965Sjdp { "mult/su", FP(0x16,0x5A2), BASE, ARG_FP }, 95033965Sjdp { "divt/su", FP(0x16,0x5A3), BASE, ARG_FP }, 95133965Sjdp { "cmptun/su", FP(0x16,0x5A4), BASE, ARG_FP }, 95233965Sjdp { "cmpteq/su", FP(0x16,0x5A5), BASE, ARG_FP }, 95333965Sjdp { "cmptlt/su", FP(0x16,0x5A6), BASE, ARG_FP }, 95433965Sjdp { "cmptle/su", FP(0x16,0x5A7), BASE, ARG_FP }, 95533965Sjdp { "cvtts/su", FP(0x16,0x5AC), BASE, ARG_FPZ1 }, 95633965Sjdp { "cvttq/sv", FP(0x16,0x5AF), BASE, ARG_FPZ1 }, 95733965Sjdp { "adds/sud", FP(0x16,0x5C0), BASE, ARG_FP }, 95833965Sjdp { "subs/sud", FP(0x16,0x5C1), BASE, ARG_FP }, 95933965Sjdp { "muls/sud", FP(0x16,0x5C2), BASE, ARG_FP }, 96033965Sjdp { "divs/sud", FP(0x16,0x5C3), BASE, ARG_FP }, 96133965Sjdp { "addt/sud", FP(0x16,0x5E0), BASE, ARG_FP }, 96233965Sjdp { "subt/sud", FP(0x16,0x5E1), BASE, ARG_FP }, 96333965Sjdp { "mult/sud", FP(0x16,0x5E2), BASE, ARG_FP }, 96433965Sjdp { "divt/sud", FP(0x16,0x5E3), BASE, ARG_FP }, 96533965Sjdp { "cvtts/sud", FP(0x16,0x5EC), BASE, ARG_FPZ1 }, 96638889Sjdp { "cvttq/svd", FP(0x16,0x5EF), BASE, ARG_FPZ1 }, 96733965Sjdp { "cvtst/s", FP(0x16,0x6AC), BASE, ARG_FPZ1 }, 96833965Sjdp { "adds/suic", FP(0x16,0x700), BASE, ARG_FP }, 96933965Sjdp { "subs/suic", FP(0x16,0x701), BASE, ARG_FP }, 97033965Sjdp { "muls/suic", FP(0x16,0x702), BASE, ARG_FP }, 97133965Sjdp { "divs/suic", FP(0x16,0x703), BASE, ARG_FP }, 97233965Sjdp { "addt/suic", FP(0x16,0x720), BASE, ARG_FP }, 97333965Sjdp { "subt/suic", FP(0x16,0x721), BASE, ARG_FP }, 97433965Sjdp { "mult/suic", FP(0x16,0x722), BASE, ARG_FP }, 97533965Sjdp { "divt/suic", FP(0x16,0x723), BASE, ARG_FP }, 97633965Sjdp { "cvtts/suic", FP(0x16,0x72C), BASE, ARG_FPZ1 }, 97733965Sjdp { "cvttq/svic", FP(0x16,0x72F), BASE, ARG_FPZ1 }, 97833965Sjdp { "cvtqs/suic", FP(0x16,0x73C), BASE, ARG_FPZ1 }, 97933965Sjdp { "cvtqt/suic", FP(0x16,0x73E), BASE, ARG_FPZ1 }, 98033965Sjdp { "adds/suim", FP(0x16,0x740), BASE, ARG_FP }, 98133965Sjdp { "subs/suim", FP(0x16,0x741), BASE, ARG_FP }, 98233965Sjdp { "muls/suim", FP(0x16,0x742), BASE, ARG_FP }, 98333965Sjdp { "divs/suim", FP(0x16,0x743), BASE, ARG_FP }, 98433965Sjdp { "addt/suim", FP(0x16,0x760), BASE, ARG_FP }, 98533965Sjdp { "subt/suim", FP(0x16,0x761), BASE, ARG_FP }, 98633965Sjdp { "mult/suim", FP(0x16,0x762), BASE, ARG_FP }, 98733965Sjdp { "divt/suim", FP(0x16,0x763), BASE, ARG_FP }, 98833965Sjdp { "cvtts/suim", FP(0x16,0x76C), BASE, ARG_FPZ1 }, 98938889Sjdp { "cvttq/svim", FP(0x16,0x76F), BASE, ARG_FPZ1 }, 99033965Sjdp { "cvtqs/suim", FP(0x16,0x77C), BASE, ARG_FPZ1 }, 99133965Sjdp { "cvtqt/suim", FP(0x16,0x77E), BASE, ARG_FPZ1 }, 99233965Sjdp { "adds/sui", FP(0x16,0x780), BASE, ARG_FP }, 99333965Sjdp { "negs/sui", FP(0x16,0x781), BASE, ARG_FPZ1 }, /* pseudo */ 99433965Sjdp { "subs/sui", FP(0x16,0x781), BASE, ARG_FP }, 99533965Sjdp { "muls/sui", FP(0x16,0x782), BASE, ARG_FP }, 99633965Sjdp { "divs/sui", FP(0x16,0x783), BASE, ARG_FP }, 99733965Sjdp { "addt/sui", FP(0x16,0x7A0), BASE, ARG_FP }, 99833965Sjdp { "negt/sui", FP(0x16,0x7A1), BASE, ARG_FPZ1 }, /* pseudo */ 99933965Sjdp { "subt/sui", FP(0x16,0x7A1), BASE, ARG_FP }, 100033965Sjdp { "mult/sui", FP(0x16,0x7A2), BASE, ARG_FP }, 100133965Sjdp { "divt/sui", FP(0x16,0x7A3), BASE, ARG_FP }, 100233965Sjdp { "cvtts/sui", FP(0x16,0x7AC), BASE, ARG_FPZ1 }, 100333965Sjdp { "cvttq/svi", FP(0x16,0x7AF), BASE, ARG_FPZ1 }, 100433965Sjdp { "cvtqs/sui", FP(0x16,0x7BC), BASE, ARG_FPZ1 }, 100533965Sjdp { "cvtqt/sui", FP(0x16,0x7BE), BASE, ARG_FPZ1 }, 100633965Sjdp { "adds/suid", FP(0x16,0x7C0), BASE, ARG_FP }, 100733965Sjdp { "subs/suid", FP(0x16,0x7C1), BASE, ARG_FP }, 100833965Sjdp { "muls/suid", FP(0x16,0x7C2), BASE, ARG_FP }, 100933965Sjdp { "divs/suid", FP(0x16,0x7C3), BASE, ARG_FP }, 101033965Sjdp { "addt/suid", FP(0x16,0x7E0), BASE, ARG_FP }, 101133965Sjdp { "subt/suid", FP(0x16,0x7E1), BASE, ARG_FP }, 101233965Sjdp { "mult/suid", FP(0x16,0x7E2), BASE, ARG_FP }, 101333965Sjdp { "divt/suid", FP(0x16,0x7E3), BASE, ARG_FP }, 101433965Sjdp { "cvtts/suid", FP(0x16,0x7EC), BASE, ARG_FPZ1 }, 101538889Sjdp { "cvttq/svid", FP(0x16,0x7EF), BASE, ARG_FPZ1 }, 101633965Sjdp { "cvtqs/suid", FP(0x16,0x7FC), BASE, ARG_FPZ1 }, 101733965Sjdp { "cvtqt/suid", FP(0x16,0x7FE), BASE, ARG_FPZ1 }, 101833965Sjdp 101933965Sjdp { "cvtlq", FP(0x17,0x010), BASE, ARG_FPZ1 }, 102033965Sjdp { "fnop", FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */ 102133965Sjdp { "fclr", FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */ 102233965Sjdp { "fabs", FP(0x17,0x020), BASE, ARG_FPZ1 }, /* pseudo */ 102333965Sjdp { "fmov", FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */ 102433965Sjdp { "cpys", FP(0x17,0x020), BASE, ARG_FP }, 102533965Sjdp { "fneg", FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */ 102633965Sjdp { "cpysn", FP(0x17,0x021), BASE, ARG_FP }, 102733965Sjdp { "cpyse", FP(0x17,0x022), BASE, ARG_FP }, 102833965Sjdp { "mt_fpcr", FP(0x17,0x024), BASE, { FA, RBA, RCA } }, 102933965Sjdp { "mf_fpcr", FP(0x17,0x025), BASE, { FA, RBA, RCA } }, 103033965Sjdp { "fcmoveq", FP(0x17,0x02A), BASE, ARG_FP }, 103133965Sjdp { "fcmovne", FP(0x17,0x02B), BASE, ARG_FP }, 103233965Sjdp { "fcmovlt", FP(0x17,0x02C), BASE, ARG_FP }, 103333965Sjdp { "fcmovge", FP(0x17,0x02D), BASE, ARG_FP }, 103433965Sjdp { "fcmovle", FP(0x17,0x02E), BASE, ARG_FP }, 103533965Sjdp { "fcmovgt", FP(0x17,0x02F), BASE, ARG_FP }, 103633965Sjdp { "cvtql", FP(0x17,0x030), BASE, ARG_FPZ1 }, 103733965Sjdp { "cvtql/v", FP(0x17,0x130), BASE, ARG_FPZ1 }, 103833965Sjdp { "cvtql/sv", FP(0x17,0x530), BASE, ARG_FPZ1 }, 103933965Sjdp 104033965Sjdp { "trapb", MFC(0x18,0x0000), BASE, ARG_NONE }, 104133965Sjdp { "draint", MFC(0x18,0x0000), BASE, ARG_NONE }, /* alias */ 104233965Sjdp { "excb", MFC(0x18,0x0400), BASE, ARG_NONE }, 104333965Sjdp { "mb", MFC(0x18,0x4000), BASE, ARG_NONE }, 104433965Sjdp { "wmb", MFC(0x18,0x4400), BASE, ARG_NONE }, 104560484Sobrien { "fetch", MFC(0x18,0x8000), BASE, { ZA, PRB } }, 104660484Sobrien { "fetch_m", MFC(0x18,0xA000), BASE, { ZA, PRB } }, 1047130561Sobrien { "rpcc", MFC(0x18,0xC000), BASE, { RA, ZB } }, 1048130561Sobrien { "rpcc", MFC(0x18,0xC000), BASE, { RA, RB } }, /* ev6 una */ 104933965Sjdp { "rc", MFC(0x18,0xE000), BASE, { RA } }, 105060484Sobrien { "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */ 105133965Sjdp { "rs", MFC(0x18,0xF000), BASE, { RA } }, 105260484Sobrien { "wh64", MFC(0x18,0xF800), BASE, { ZA, PRB } }, /* ev56 una */ 105389857Sobrien { "wh64en", MFC(0x18,0xFC00), BASE, { ZA, PRB } }, /* ev7 una */ 105433965Sjdp 105533965Sjdp { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, 105633965Sjdp { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, 105760484Sobrien { "hw_mfpr", OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } }, 105833965Sjdp { "hw_mfpr/i", OPR(0x19,0x01), EV4, ARG_EV4HWMPR }, 105933965Sjdp { "hw_mfpr/a", OPR(0x19,0x02), EV4, ARG_EV4HWMPR }, 106033965Sjdp { "hw_mfpr/ai", OPR(0x19,0x03), EV4, ARG_EV4HWMPR }, 106133965Sjdp { "hw_mfpr/p", OPR(0x19,0x04), EV4, ARG_EV4HWMPR }, 106233965Sjdp { "hw_mfpr/pi", OPR(0x19,0x05), EV4, ARG_EV4HWMPR }, 106333965Sjdp { "hw_mfpr/pa", OPR(0x19,0x06), EV4, ARG_EV4HWMPR }, 106433965Sjdp { "hw_mfpr/pai", OPR(0x19,0x07), EV4, ARG_EV4HWMPR }, 106533965Sjdp { "pal19", PCD(0x19), BASE, ARG_PCD }, 106633965Sjdp 106791041Sobrien { "jmp", MBR_(0x1A,0), MBR_MASK | 0x3FFF, /* pseudo */ 106891041Sobrien BASE, { ZA, CPRB } }, 106933965Sjdp { "jmp", MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } }, 107033965Sjdp { "jsr", MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } }, 107191041Sobrien { "ret", MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */ 107291041Sobrien 0xFFFFFFFF, BASE, { 0 } }, 107333965Sjdp { "ret", MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } }, 107433965Sjdp { "jcr", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */ 107533965Sjdp { "jsr_coroutine", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, 107633965Sjdp 107733965Sjdp { "hw_ldl", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, 107833965Sjdp { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, 107960484Sobrien { "hw_ldl", EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM }, 108033965Sjdp { "hw_ldl/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, 108133965Sjdp { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, 108260484Sobrien { "hw_ldl/a", EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM }, 108333965Sjdp { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 108433965Sjdp { "hw_ldl/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, 108533965Sjdp { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, 108633965Sjdp { "hw_ldl/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 108733965Sjdp { "hw_ldl/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, 108833965Sjdp { "hw_ldl/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 108933965Sjdp { "hw_ldl/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, 109033965Sjdp { "hw_ldl/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 109133965Sjdp { "hw_ldl/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 109233965Sjdp { "hw_ldl/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, 109333965Sjdp { "hw_ldl/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, 109460484Sobrien { "hw_ldl/p", EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM }, 109533965Sjdp { "hw_ldl/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, 109633965Sjdp { "hw_ldl/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, 109733965Sjdp { "hw_ldl/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 109833965Sjdp { "hw_ldl/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, 109933965Sjdp { "hw_ldl/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, 110033965Sjdp { "hw_ldl/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 110133965Sjdp { "hw_ldl/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, 110233965Sjdp { "hw_ldl/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 110333965Sjdp { "hw_ldl/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, 110433965Sjdp { "hw_ldl/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 110533965Sjdp { "hw_ldl/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 110633965Sjdp { "hw_ldl/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, 110733965Sjdp { "hw_ldl/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, 110833965Sjdp { "hw_ldl/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 110933965Sjdp { "hw_ldl/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, 111033965Sjdp { "hw_ldl/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 111133965Sjdp { "hw_ldl/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, 111233965Sjdp { "hw_ldl/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 111333965Sjdp { "hw_ldl/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, 111433965Sjdp { "hw_ldl/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, 111560484Sobrien { "hw_ldl/v", EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM }, 111633965Sjdp { "hw_ldl/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 111733965Sjdp { "hw_ldl/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, 111860484Sobrien { "hw_ldl/w", EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM }, 111960484Sobrien { "hw_ldl/wa", EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM }, 112033965Sjdp { "hw_ldl/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 112133965Sjdp { "hw_ldl/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, 112233965Sjdp { "hw_ldl/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 112333965Sjdp { "hw_ldl_l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 112433965Sjdp { "hw_ldl_l/a", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 112533965Sjdp { "hw_ldl_l/av", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 112633965Sjdp { "hw_ldl_l/aw", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 112733965Sjdp { "hw_ldl_l/awv", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 112833965Sjdp { "hw_ldl_l/p", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 112960484Sobrien { "hw_ldl_l/p", EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM }, 113033965Sjdp { "hw_ldl_l/pa", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 113133965Sjdp { "hw_ldl_l/pav", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 113233965Sjdp { "hw_ldl_l/paw", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 113333965Sjdp { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 113433965Sjdp { "hw_ldl_l/pv", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 113533965Sjdp { "hw_ldl_l/pw", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 113633965Sjdp { "hw_ldl_l/pwv", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 113733965Sjdp { "hw_ldl_l/v", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 113833965Sjdp { "hw_ldl_l/w", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 113933965Sjdp { "hw_ldl_l/wv", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 114033965Sjdp { "hw_ldq", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, 114133965Sjdp { "hw_ldq", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, 114260484Sobrien { "hw_ldq", EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM }, 114333965Sjdp { "hw_ldq/a", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, 114433965Sjdp { "hw_ldq/a", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, 114560484Sobrien { "hw_ldq/a", EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM }, 114633965Sjdp { "hw_ldq/al", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 114733965Sjdp { "hw_ldq/ar", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, 114833965Sjdp { "hw_ldq/av", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, 114933965Sjdp { "hw_ldq/avl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 115033965Sjdp { "hw_ldq/aw", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, 115133965Sjdp { "hw_ldq/awl", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 115233965Sjdp { "hw_ldq/awv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, 115333965Sjdp { "hw_ldq/awvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 115433965Sjdp { "hw_ldq/l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 115533965Sjdp { "hw_ldq/p", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, 115633965Sjdp { "hw_ldq/p", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, 115760484Sobrien { "hw_ldq/p", EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM }, 115833965Sjdp { "hw_ldq/pa", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, 115933965Sjdp { "hw_ldq/pa", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, 116033965Sjdp { "hw_ldq/pal", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 116133965Sjdp { "hw_ldq/par", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, 116233965Sjdp { "hw_ldq/pav", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, 116333965Sjdp { "hw_ldq/pavl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 116433965Sjdp { "hw_ldq/paw", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, 116533965Sjdp { "hw_ldq/pawl", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 116633965Sjdp { "hw_ldq/pawv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, 116733965Sjdp { "hw_ldq/pawvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 116833965Sjdp { "hw_ldq/pl", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 116933965Sjdp { "hw_ldq/pr", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, 117033965Sjdp { "hw_ldq/pv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, 117133965Sjdp { "hw_ldq/pvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 117233965Sjdp { "hw_ldq/pw", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, 117333965Sjdp { "hw_ldq/pwl", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 117433965Sjdp { "hw_ldq/pwv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, 117533965Sjdp { "hw_ldq/pwvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 117633965Sjdp { "hw_ldq/r", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, 117733965Sjdp { "hw_ldq/v", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, 117860484Sobrien { "hw_ldq/v", EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM }, 117933965Sjdp { "hw_ldq/vl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 118033965Sjdp { "hw_ldq/w", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, 118160484Sobrien { "hw_ldq/w", EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM }, 118260484Sobrien { "hw_ldq/wa", EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM }, 118333965Sjdp { "hw_ldq/wl", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 118433965Sjdp { "hw_ldq/wv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, 118533965Sjdp { "hw_ldq/wvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 118633965Sjdp { "hw_ldq_l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 118733965Sjdp { "hw_ldq_l/a", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 118833965Sjdp { "hw_ldq_l/av", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 118933965Sjdp { "hw_ldq_l/aw", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 119033965Sjdp { "hw_ldq_l/awv", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 119133965Sjdp { "hw_ldq_l/p", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 119260484Sobrien { "hw_ldq_l/p", EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM }, 119333965Sjdp { "hw_ldq_l/pa", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 119433965Sjdp { "hw_ldq_l/pav", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 119533965Sjdp { "hw_ldq_l/paw", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 119633965Sjdp { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 119733965Sjdp { "hw_ldq_l/pv", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 119833965Sjdp { "hw_ldq_l/pw", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 119933965Sjdp { "hw_ldq_l/pwv", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 120033965Sjdp { "hw_ldq_l/v", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 120133965Sjdp { "hw_ldq_l/w", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 120233965Sjdp { "hw_ldq_l/wv", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 120333965Sjdp { "hw_ld", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, 120433965Sjdp { "hw_ld", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, 120533965Sjdp { "hw_ld/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, 120633965Sjdp { "hw_ld/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, 120733965Sjdp { "hw_ld/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 120833965Sjdp { "hw_ld/aq", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, 120933965Sjdp { "hw_ld/aq", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, 121033965Sjdp { "hw_ld/aql", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 121133965Sjdp { "hw_ld/aqv", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, 121233965Sjdp { "hw_ld/aqvl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 121333965Sjdp { "hw_ld/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, 121433965Sjdp { "hw_ld/arq", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, 121533965Sjdp { "hw_ld/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, 121633965Sjdp { "hw_ld/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 121733965Sjdp { "hw_ld/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, 121833965Sjdp { "hw_ld/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 121933965Sjdp { "hw_ld/awq", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, 122033965Sjdp { "hw_ld/awql", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 122133965Sjdp { "hw_ld/awqv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, 122233965Sjdp { "hw_ld/awqvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 122333965Sjdp { "hw_ld/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, 122433965Sjdp { "hw_ld/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 122533965Sjdp { "hw_ld/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 122633965Sjdp { "hw_ld/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, 122733965Sjdp { "hw_ld/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, 122833965Sjdp { "hw_ld/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, 122933965Sjdp { "hw_ld/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, 123033965Sjdp { "hw_ld/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 123133965Sjdp { "hw_ld/paq", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, 123233965Sjdp { "hw_ld/paq", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, 123333965Sjdp { "hw_ld/paql", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 123433965Sjdp { "hw_ld/paqv", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, 123533965Sjdp { "hw_ld/paqvl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 123633965Sjdp { "hw_ld/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, 123733965Sjdp { "hw_ld/parq", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, 123833965Sjdp { "hw_ld/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, 123933965Sjdp { "hw_ld/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 124033965Sjdp { "hw_ld/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, 124133965Sjdp { "hw_ld/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 124233965Sjdp { "hw_ld/pawq", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, 124333965Sjdp { "hw_ld/pawql", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 124433965Sjdp { "hw_ld/pawqv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, 124533965Sjdp { "hw_ld/pawqvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 124633965Sjdp { "hw_ld/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, 124733965Sjdp { "hw_ld/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 124833965Sjdp { "hw_ld/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 124933965Sjdp { "hw_ld/pq", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, 125033965Sjdp { "hw_ld/pq", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, 125133965Sjdp { "hw_ld/pql", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 125233965Sjdp { "hw_ld/pqv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, 125333965Sjdp { "hw_ld/pqvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 125433965Sjdp { "hw_ld/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, 125533965Sjdp { "hw_ld/prq", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, 125633965Sjdp { "hw_ld/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, 125733965Sjdp { "hw_ld/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 125833965Sjdp { "hw_ld/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, 125933965Sjdp { "hw_ld/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 126033965Sjdp { "hw_ld/pwq", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, 126133965Sjdp { "hw_ld/pwql", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 126233965Sjdp { "hw_ld/pwqv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, 126333965Sjdp { "hw_ld/pwqvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 126433965Sjdp { "hw_ld/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, 126533965Sjdp { "hw_ld/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 126633965Sjdp { "hw_ld/q", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, 126733965Sjdp { "hw_ld/q", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, 126833965Sjdp { "hw_ld/ql", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 126933965Sjdp { "hw_ld/qv", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, 127033965Sjdp { "hw_ld/qvl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 127133965Sjdp { "hw_ld/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, 127233965Sjdp { "hw_ld/rq", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, 127333965Sjdp { "hw_ld/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, 127433965Sjdp { "hw_ld/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 127533965Sjdp { "hw_ld/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, 127633965Sjdp { "hw_ld/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 127733965Sjdp { "hw_ld/wq", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, 127833965Sjdp { "hw_ld/wql", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 127933965Sjdp { "hw_ld/wqv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, 128033965Sjdp { "hw_ld/wqvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 128133965Sjdp { "hw_ld/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, 128233965Sjdp { "hw_ld/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 128333965Sjdp { "pal1b", PCD(0x1B), BASE, ARG_PCD }, 128433965Sjdp 128533965Sjdp { "sextb", OPR(0x1C, 0x00), BWX, ARG_OPRZ1 }, 128633965Sjdp { "sextw", OPR(0x1C, 0x01), BWX, ARG_OPRZ1 }, 128733965Sjdp { "ctpop", OPR(0x1C, 0x30), CIX, ARG_OPRZ1 }, 128833965Sjdp { "perr", OPR(0x1C, 0x31), MAX, ARG_OPR }, 128933965Sjdp { "ctlz", OPR(0x1C, 0x32), CIX, ARG_OPRZ1 }, 129033965Sjdp { "cttz", OPR(0x1C, 0x33), CIX, ARG_OPRZ1 }, 129133965Sjdp { "unpkbw", OPR(0x1C, 0x34), MAX, ARG_OPRZ1 }, 129233965Sjdp { "unpkbl", OPR(0x1C, 0x35), MAX, ARG_OPRZ1 }, 129333965Sjdp { "pkwb", OPR(0x1C, 0x36), MAX, ARG_OPRZ1 }, 129433965Sjdp { "pklb", OPR(0x1C, 0x37), MAX, ARG_OPRZ1 }, 129533965Sjdp { "minsb8", OPR(0x1C, 0x38), MAX, ARG_OPR }, 129633965Sjdp { "minsb8", OPRL(0x1C, 0x38), MAX, ARG_OPRL }, 129733965Sjdp { "minsw4", OPR(0x1C, 0x39), MAX, ARG_OPR }, 129833965Sjdp { "minsw4", OPRL(0x1C, 0x39), MAX, ARG_OPRL }, 129933965Sjdp { "minub8", OPR(0x1C, 0x3A), MAX, ARG_OPR }, 130033965Sjdp { "minub8", OPRL(0x1C, 0x3A), MAX, ARG_OPRL }, 130133965Sjdp { "minuw4", OPR(0x1C, 0x3B), MAX, ARG_OPR }, 130233965Sjdp { "minuw4", OPRL(0x1C, 0x3B), MAX, ARG_OPRL }, 130333965Sjdp { "maxub8", OPR(0x1C, 0x3C), MAX, ARG_OPR }, 130433965Sjdp { "maxub8", OPRL(0x1C, 0x3C), MAX, ARG_OPRL }, 130533965Sjdp { "maxuw4", OPR(0x1C, 0x3D), MAX, ARG_OPR }, 130633965Sjdp { "maxuw4", OPRL(0x1C, 0x3D), MAX, ARG_OPRL }, 130733965Sjdp { "maxsb8", OPR(0x1C, 0x3E), MAX, ARG_OPR }, 130833965Sjdp { "maxsb8", OPRL(0x1C, 0x3E), MAX, ARG_OPRL }, 130933965Sjdp { "maxsw4", OPR(0x1C, 0x3F), MAX, ARG_OPR }, 131033965Sjdp { "maxsw4", OPRL(0x1C, 0x3F), MAX, ARG_OPRL }, 131133965Sjdp { "ftoit", FP(0x1C, 0x70), CIX, { FA, ZB, RC } }, 131233965Sjdp { "ftois", FP(0x1C, 0x78), CIX, { FA, ZB, RC } }, 131333965Sjdp 131433965Sjdp { "hw_mtpr", OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, 131533965Sjdp { "hw_mtpr", OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, 131660484Sobrien { "hw_mtpr", OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } }, 131733965Sjdp { "hw_mtpr/i", OPR(0x1D,0x01), EV4, ARG_EV4HWMPR }, 131833965Sjdp { "hw_mtpr/a", OPR(0x1D,0x02), EV4, ARG_EV4HWMPR }, 131933965Sjdp { "hw_mtpr/ai", OPR(0x1D,0x03), EV4, ARG_EV4HWMPR }, 132033965Sjdp { "hw_mtpr/p", OPR(0x1D,0x04), EV4, ARG_EV4HWMPR }, 132133965Sjdp { "hw_mtpr/pi", OPR(0x1D,0x05), EV4, ARG_EV4HWMPR }, 132233965Sjdp { "hw_mtpr/pa", OPR(0x1D,0x06), EV4, ARG_EV4HWMPR }, 132333965Sjdp { "hw_mtpr/pai", OPR(0x1D,0x07), EV4, ARG_EV4HWMPR }, 132433965Sjdp { "pal1d", PCD(0x1D), BASE, ARG_PCD }, 132533965Sjdp 132633965Sjdp { "hw_rei", SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE }, 132738889Sjdp { "hw_rei_stall", SPCD(0x1E,0x3FFC000), EV5, ARG_NONE }, 132860484Sobrien { "hw_jmp", EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } }, 132960484Sobrien { "hw_jsr", EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } }, 133060484Sobrien { "hw_ret", EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } }, 133160484Sobrien { "hw_jcr", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, 133260484Sobrien { "hw_coroutine", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */ 133360484Sobrien { "hw_jmp/stall", EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } }, 133460484Sobrien { "hw_jsr/stall", EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } }, 133560484Sobrien { "hw_ret/stall", EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } }, 133660484Sobrien { "hw_jcr/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, 133760484Sobrien { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */ 133833965Sjdp { "pal1e", PCD(0x1E), BASE, ARG_PCD }, 133933965Sjdp 134033965Sjdp { "hw_stl", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, 134133965Sjdp { "hw_stl", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, 134260484Sobrien { "hw_stl", EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */ 134333965Sjdp { "hw_stl/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, 134433965Sjdp { "hw_stl/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, 134560484Sobrien { "hw_stl/a", EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM }, 134633965Sjdp { "hw_stl/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 134733965Sjdp { "hw_stl/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, 134833965Sjdp { "hw_stl/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, 134933965Sjdp { "hw_stl/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 135033965Sjdp { "hw_stl/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 135133965Sjdp { "hw_stl/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, 135233965Sjdp { "hw_stl/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, 135360484Sobrien { "hw_stl/p", EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM }, 135433965Sjdp { "hw_stl/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, 135533965Sjdp { "hw_stl/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, 135633965Sjdp { "hw_stl/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 135733965Sjdp { "hw_stl/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, 135833965Sjdp { "hw_stl/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 135933965Sjdp { "hw_stl/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 136033965Sjdp { "hw_stl/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, 136133965Sjdp { "hw_stl/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, 136233965Sjdp { "hw_stl/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 136333965Sjdp { "hw_stl/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, 136433965Sjdp { "hw_stl/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, 136533965Sjdp { "hw_stl/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 136633965Sjdp { "hw_stl_c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 136733965Sjdp { "hw_stl_c/a", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 136833965Sjdp { "hw_stl_c/av", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 136933965Sjdp { "hw_stl_c/p", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 137060484Sobrien { "hw_stl_c/p", EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM }, 137133965Sjdp { "hw_stl_c/pa", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 137233965Sjdp { "hw_stl_c/pav", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 137333965Sjdp { "hw_stl_c/pv", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 137433965Sjdp { "hw_stl_c/v", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 137533965Sjdp { "hw_stq", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, 137633965Sjdp { "hw_stq", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, 137760484Sobrien { "hw_stq", EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */ 137833965Sjdp { "hw_stq/a", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, 137933965Sjdp { "hw_stq/a", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, 138060484Sobrien { "hw_stq/a", EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM }, 138133965Sjdp { "hw_stq/ac", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 138233965Sjdp { "hw_stq/ar", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, 138333965Sjdp { "hw_stq/av", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, 138433965Sjdp { "hw_stq/avc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 138533965Sjdp { "hw_stq/c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 138633965Sjdp { "hw_stq/p", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, 138733965Sjdp { "hw_stq/p", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, 138860484Sobrien { "hw_stq/p", EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM }, 138933965Sjdp { "hw_stq/pa", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, 139033965Sjdp { "hw_stq/pa", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, 139133965Sjdp { "hw_stq/pac", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 139233965Sjdp { "hw_stq/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, 139333965Sjdp { "hw_stq/par", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, 139433965Sjdp { "hw_stq/pav", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, 139533965Sjdp { "hw_stq/pavc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 139633965Sjdp { "hw_stq/pc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 139733965Sjdp { "hw_stq/pr", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, 139833965Sjdp { "hw_stq/pv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, 139933965Sjdp { "hw_stq/pvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 140033965Sjdp { "hw_stq/r", EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM }, 140133965Sjdp { "hw_stq/v", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, 140233965Sjdp { "hw_stq/vc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 140333965Sjdp { "hw_stq_c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 140433965Sjdp { "hw_stq_c/a", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 140533965Sjdp { "hw_stq_c/av", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 140633965Sjdp { "hw_stq_c/p", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 140760484Sobrien { "hw_stq_c/p", EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM }, 140833965Sjdp { "hw_stq_c/pa", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 140933965Sjdp { "hw_stq_c/pav", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 141033965Sjdp { "hw_stq_c/pv", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 141133965Sjdp { "hw_stq_c/v", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 141233965Sjdp { "hw_st", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, 141333965Sjdp { "hw_st", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, 141433965Sjdp { "hw_st/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, 141533965Sjdp { "hw_st/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, 141633965Sjdp { "hw_st/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 141733965Sjdp { "hw_st/aq", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, 141833965Sjdp { "hw_st/aq", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, 141933965Sjdp { "hw_st/aqc", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 142033965Sjdp { "hw_st/aqv", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, 142133965Sjdp { "hw_st/aqvc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 142233965Sjdp { "hw_st/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, 142333965Sjdp { "hw_st/arq", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, 142433965Sjdp { "hw_st/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, 142533965Sjdp { "hw_st/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 142633965Sjdp { "hw_st/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 142733965Sjdp { "hw_st/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, 142833965Sjdp { "hw_st/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, 142933965Sjdp { "hw_st/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, 143033965Sjdp { "hw_st/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, 143133965Sjdp { "hw_st/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 143233965Sjdp { "hw_st/paq", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, 143333965Sjdp { "hw_st/paq", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, 143433965Sjdp { "hw_st/paqc", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 143533965Sjdp { "hw_st/paqv", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, 143633965Sjdp { "hw_st/paqvc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 143733965Sjdp { "hw_st/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, 143833965Sjdp { "hw_st/parq", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, 143933965Sjdp { "hw_st/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, 144033965Sjdp { "hw_st/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 144133965Sjdp { "hw_st/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 144233965Sjdp { "hw_st/pq", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, 144333965Sjdp { "hw_st/pq", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, 144433965Sjdp { "hw_st/pqc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 144533965Sjdp { "hw_st/pqv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, 144633965Sjdp { "hw_st/pqvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 144733965Sjdp { "hw_st/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, 144833965Sjdp { "hw_st/prq", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, 144933965Sjdp { "hw_st/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, 145033965Sjdp { "hw_st/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 145133965Sjdp { "hw_st/q", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, 145233965Sjdp { "hw_st/q", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, 145333965Sjdp { "hw_st/qc", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 145433965Sjdp { "hw_st/qv", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, 145533965Sjdp { "hw_st/qvc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 145633965Sjdp { "hw_st/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, 145733965Sjdp { "hw_st/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, 145833965Sjdp { "hw_st/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 145933965Sjdp { "pal1f", PCD(0x1F), BASE, ARG_PCD }, 146033965Sjdp 146133965Sjdp { "ldf", MEM(0x20), BASE, ARG_FMEM }, 146233965Sjdp { "ldg", MEM(0x21), BASE, ARG_FMEM }, 146333965Sjdp { "lds", MEM(0x22), BASE, ARG_FMEM }, 146433965Sjdp { "ldt", MEM(0x23), BASE, ARG_FMEM }, 146533965Sjdp { "stf", MEM(0x24), BASE, ARG_FMEM }, 146633965Sjdp { "stg", MEM(0x25), BASE, ARG_FMEM }, 146733965Sjdp { "sts", MEM(0x26), BASE, ARG_FMEM }, 146833965Sjdp { "stt", MEM(0x27), BASE, ARG_FMEM }, 146933965Sjdp 147033965Sjdp { "ldl", MEM(0x28), BASE, ARG_MEM }, 147133965Sjdp { "ldq", MEM(0x29), BASE, ARG_MEM }, 147233965Sjdp { "ldl_l", MEM(0x2A), BASE, ARG_MEM }, 147333965Sjdp { "ldq_l", MEM(0x2B), BASE, ARG_MEM }, 147433965Sjdp { "stl", MEM(0x2C), BASE, ARG_MEM }, 147533965Sjdp { "stq", MEM(0x2D), BASE, ARG_MEM }, 147633965Sjdp { "stl_c", MEM(0x2E), BASE, ARG_MEM }, 147733965Sjdp { "stq_c", MEM(0x2F), BASE, ARG_MEM }, 147833965Sjdp 147933965Sjdp { "br", BRA(0x30), BASE, { ZA, BDISP } }, /* pseudo */ 148033965Sjdp { "br", BRA(0x30), BASE, ARG_BRA }, 148133965Sjdp { "fbeq", BRA(0x31), BASE, ARG_FBRA }, 148233965Sjdp { "fblt", BRA(0x32), BASE, ARG_FBRA }, 148333965Sjdp { "fble", BRA(0x33), BASE, ARG_FBRA }, 148433965Sjdp { "bsr", BRA(0x34), BASE, ARG_BRA }, 148533965Sjdp { "fbne", BRA(0x35), BASE, ARG_FBRA }, 148633965Sjdp { "fbge", BRA(0x36), BASE, ARG_FBRA }, 148733965Sjdp { "fbgt", BRA(0x37), BASE, ARG_FBRA }, 148833965Sjdp { "blbc", BRA(0x38), BASE, ARG_BRA }, 148933965Sjdp { "beq", BRA(0x39), BASE, ARG_BRA }, 149033965Sjdp { "blt", BRA(0x3A), BASE, ARG_BRA }, 149133965Sjdp { "ble", BRA(0x3B), BASE, ARG_BRA }, 149233965Sjdp { "blbs", BRA(0x3C), BASE, ARG_BRA }, 149333965Sjdp { "bne", BRA(0x3D), BASE, ARG_BRA }, 149433965Sjdp { "bge", BRA(0x3E), BASE, ARG_BRA }, 149533965Sjdp { "bgt", BRA(0x3F), BASE, ARG_BRA }, 149633965Sjdp}; 149733965Sjdp 149860484Sobrienconst unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes); 1499