1129794Stackerman/******************************************************************************* 2129794Stackerman 3129794Stackerman Copyright (c) 2001-2004, Intel Corporation 4129794Stackerman All rights reserved. 5129794Stackerman 6129794Stackerman Redistribution and use in source and binary forms, with or without 7129794Stackerman modification, are permitted provided that the following conditions are met: 8129794Stackerman 9129794Stackerman 1. Redistributions of source code must retain the above copyright notice, 10129794Stackerman this list of conditions and the following disclaimer. 11129794Stackerman 12129794Stackerman 2. Redistributions in binary form must reproduce the above copyright 13129794Stackerman notice, this list of conditions and the following disclaimer in the 14129794Stackerman documentation and/or other materials provided with the distribution. 15129794Stackerman 16129794Stackerman 3. Neither the name of the Intel Corporation nor the names of its 17129794Stackerman contributors may be used to endorse or promote products derived from 18129794Stackerman this software without specific prior written permission. 19129794Stackerman 20129794Stackerman THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21129794Stackerman AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22129794Stackerman IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23129794Stackerman ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24129794Stackerman LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25129794Stackerman CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26129794Stackerman SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27129794Stackerman INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28129794Stackerman CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29129794Stackerman ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30129794Stackerman POSSIBILITY OF SUCH DAMAGE. 31129794Stackerman 32129794Stackerman*******************************************************************************/ 33129794Stackerman 34129794Stackerman/*$FreeBSD: releng/10.2/sys/dev/ixgb/ixgb_hw.c 129794 2004-05-28 00:23:00Z tackerman $*/ 35129794Stackerman 36129794Stackerman/* ixgb_hw.c 37129794Stackerman * Shared functions for accessing and configuring the adapter 38129794Stackerman */ 39129794Stackerman 40129794Stackerman#include <dev/ixgb/ixgb_hw.h> 41129794Stackerman#include <dev/ixgb/ixgb_ids.h> 42129794Stackerman 43129794Stackerman/* Local function prototypes */ 44129794Stackerman 45129794Stackermanstatic uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw, 46129794Stackerman uint8_t *mc_addr); 47129794Stackerman 48129794Stackermanstatic void ixgb_mta_set(struct ixgb_hw *hw, 49129794Stackerman uint32_t hash_value); 50129794Stackerman 51129794Stackermanstatic void ixgb_get_bus_info(struct ixgb_hw *hw); 52129794Stackerman 53129794Stackermanstatic boolean_t ixgb_link_reset(struct ixgb_hw *hw); 54129794Stackerman 55129794Stackermanstatic void ixgb_optics_reset(struct ixgb_hw *hw); 56129794Stackerman 57129794Stackermanstatic ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw); 58129794Stackerman 59129794Stackermanuint32_t ixgb_mac_reset (struct ixgb_hw* hw); 60129794Stackerman 61129794Stackermanuint32_t ixgb_mac_reset (struct ixgb_hw* hw) 62129794Stackerman{ 63129794Stackerman uint32_t ctrl_reg; 64129794Stackerman 65129794Stackerman /* Setup up hardware to known state with RESET. 66129794Stackerman * SWDPIN settings as per Kemano EPS. 67129794Stackerman */ 68129794Stackerman ctrl_reg = IXGB_CTRL0_RST | 69129794Stackerman IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */ 70129794Stackerman IXGB_CTRL0_SDP2_DIR | 71129794Stackerman IXGB_CTRL0_SDP1_DIR | 72129794Stackerman IXGB_CTRL0_SDP0_DIR | 73129794Stackerman IXGB_CTRL0_SDP3 | /* Initial value 1101 */ 74129794Stackerman IXGB_CTRL0_SDP2 | 75129794Stackerman IXGB_CTRL0_SDP0; 76129794Stackerman 77129794Stackerman#ifdef HP_ZX1 78129794Stackerman /* Workaround for 82597EX reset errata */ 79129794Stackerman IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg); 80129794Stackerman#else 81129794Stackerman IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); 82129794Stackerman#endif 83129794Stackerman 84129794Stackerman /* Delay a few ms just to allow the reset to complete */ 85129794Stackerman msec_delay(IXGB_DELAY_AFTER_RESET); 86129794Stackerman ctrl_reg = IXGB_READ_REG(hw, CTRL0); 87129794Stackerman#if DBG 88129794Stackerman /* Make sure the self-clearing global reset bit did self clear */ 89129794Stackerman ASSERT(!(ctrl_reg & IXGB_CTRL0_RST)); 90129794Stackerman#endif 91129794Stackerman 92129794Stackerman if (hw->phy_type == ixgb_phy_type_txn17401) { 93129794Stackerman /* Now reset the optics. This reset is required to ensure link with 94129794Stackerman * the Kemano 003 optical module (TXN17401), as per instructions from 95129794Stackerman * the board designer. 96129794Stackerman */ 97129794Stackerman ixgb_optics_reset(hw); 98129794Stackerman } 99129794Stackerman 100129794Stackerman return ctrl_reg; 101129794Stackerman} 102129794Stackerman 103129794Stackerman 104129794Stackerman/****************************************************************************** 105129794Stackerman * Reset the transmit and receive units; mask and clear all interrupts. 106129794Stackerman * 107129794Stackerman * hw - Struct containing variables accessed by shared code 108129794Stackerman *****************************************************************************/ 109129794Stackermanboolean_t 110129794Stackermanixgb_adapter_stop(struct ixgb_hw *hw) 111129794Stackerman{ 112129794Stackerman uint32_t ctrl_reg; 113129794Stackerman uint32_t icr_reg; 114129794Stackerman 115129794Stackerman DEBUGFUNC("ixgb_adapter_stop"); 116129794Stackerman 117129794Stackerman /* If we are stopped or resetting exit gracefully and wait to be 118129794Stackerman * started again before accessing the hardware. 119129794Stackerman */ 120129794Stackerman if(hw->adapter_stopped) { 121129794Stackerman DEBUGOUT("Exiting because the adapter is already stopped!!!\n"); 122129794Stackerman return FALSE; 123129794Stackerman } 124129794Stackerman 125129794Stackerman /* Set the Adapter Stopped flag so other driver functions stop 126129794Stackerman * touching the Hardware. 127129794Stackerman */ 128129794Stackerman hw->adapter_stopped = TRUE; 129129794Stackerman 130129794Stackerman /* Clear interrupt mask to stop board from generating interrupts */ 131129794Stackerman DEBUGOUT("Masking off all interrupts\n"); 132129794Stackerman IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF); 133129794Stackerman 134129794Stackerman /* Disable the Transmit and Receive units. Then delay to allow 135129794Stackerman * any pending transactions to complete before we hit the MAC with 136129794Stackerman * the global reset. 137129794Stackerman */ 138129794Stackerman IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN); 139129794Stackerman IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN); 140129794Stackerman msec_delay(IXGB_DELAY_BEFORE_RESET); 141129794Stackerman 142129794Stackerman /* Issue a global reset to the MAC. This will reset the chip's 143129794Stackerman * transmit, receive, DMA, and link units. It will not effect 144129794Stackerman * the current PCI configuration. The global reset bit is self- 145129794Stackerman * clearing, and should clear within a microsecond. 146129794Stackerman */ 147129794Stackerman DEBUGOUT("Issuing a global reset to MAC\n"); 148129794Stackerman 149129794Stackerman ctrl_reg = ixgb_mac_reset(hw); 150129794Stackerman 151129794Stackerman /* Clear interrupt mask to stop board from generating interrupts */ 152129794Stackerman DEBUGOUT("Masking off all interrupts\n"); 153129794Stackerman IXGB_WRITE_REG(hw, IMC, 0xffffffff); 154129794Stackerman 155129794Stackerman /* Clear any pending interrupt events. */ 156129794Stackerman icr_reg = IXGB_READ_REG(hw, ICR); 157129794Stackerman 158129794Stackerman return (ctrl_reg & IXGB_CTRL0_RST); 159129794Stackerman} 160129794Stackerman 161129794Stackerman 162129794Stackerman/****************************************************************************** 163129794Stackerman * Identifies the vendor of the optics module on the adapter. The SR adapters 164129794Stackerman * support two different types of XPAK optics, so it is necessary to determine 165129794Stackerman * which optics are present before applying any optics-specific workarounds. 166129794Stackerman * 167129794Stackerman * hw - Struct containing variables accessed by shared code. 168129794Stackerman * 169129794Stackerman * Returns: the vendor of the XPAK optics module. 170129794Stackerman *****************************************************************************/ 171129794Stackermanstatic ixgb_xpak_vendor 172129794Stackermanixgb_identify_xpak_vendor(struct ixgb_hw *hw) 173129794Stackerman{ 174129794Stackerman uint32_t i; 175129794Stackerman uint16_t vendor_name[5]; 176129794Stackerman ixgb_xpak_vendor xpak_vendor; 177129794Stackerman 178129794Stackerman DEBUGFUNC("ixgb_identify_xpak_vendor"); 179129794Stackerman 180129794Stackerman /* Read the first few bytes of the vendor string from the XPAK NVR 181129794Stackerman * registers. These are standard XENPAK/XPAK registers, so all XPAK 182129794Stackerman * devices should implement them. */ 183129794Stackerman for (i = 0; i < 5; i++) { 184129794Stackerman vendor_name[i] = ixgb_read_phy_reg( hw, 185129794Stackerman MDIO_PMA_PMD_XPAK_VENDOR_NAME + i, 186129794Stackerman IXGB_PHY_ADDRESS, 187129794Stackerman MDIO_PMA_PMD_DID ); 188129794Stackerman } 189129794Stackerman 190129794Stackerman /* Determine the actual vendor */ 191129794Stackerman if (vendor_name[0] == 'I' && 192129794Stackerman vendor_name[1] == 'N' && 193129794Stackerman vendor_name[2] == 'T' && 194129794Stackerman vendor_name[3] == 'E' && 195129794Stackerman vendor_name[4] == 'L') { 196129794Stackerman xpak_vendor = ixgb_xpak_vendor_intel; 197129794Stackerman } 198129794Stackerman else { 199129794Stackerman xpak_vendor = ixgb_xpak_vendor_infineon; 200129794Stackerman } 201129794Stackerman 202129794Stackerman return (xpak_vendor); 203129794Stackerman} 204129794Stackerman 205129794Stackerman 206129794Stackerman/****************************************************************************** 207129794Stackerman * Determine the physical layer module on the adapter. 208129794Stackerman * 209129794Stackerman * hw - Struct containing variables accessed by shared code. The device_id 210129794Stackerman * field must be (correctly) populated before calling this routine. 211129794Stackerman * 212129794Stackerman * Returns: the phy type of the adapter. 213129794Stackerman *****************************************************************************/ 214129794Stackermanstatic ixgb_phy_type 215129794Stackermanixgb_identify_phy(struct ixgb_hw *hw) 216129794Stackerman{ 217129794Stackerman ixgb_phy_type phy_type; 218129794Stackerman ixgb_xpak_vendor xpak_vendor; 219129794Stackerman 220129794Stackerman DEBUGFUNC("ixgb_identify_phy"); 221129794Stackerman 222129794Stackerman /* Infer the transceiver/phy type from the device id */ 223129794Stackerman switch (hw->device_id) { 224129794Stackerman case IXGB_DEVICE_ID_82597EX: 225129794Stackerman DEBUGOUT("Identified TXN17401 optics\n"); 226129794Stackerman phy_type = ixgb_phy_type_txn17401; 227129794Stackerman break; 228129794Stackerman 229129794Stackerman case IXGB_DEVICE_ID_82597EX_SR: 230129794Stackerman /* The SR adapters carry two different types of XPAK optics 231129794Stackerman * modules; read the vendor identifier to determine the exact 232129794Stackerman * type of optics. */ 233129794Stackerman xpak_vendor = ixgb_identify_xpak_vendor(hw); 234129794Stackerman if (xpak_vendor == ixgb_xpak_vendor_intel) { 235129794Stackerman DEBUGOUT("Identified TXN17201 optics\n"); 236129794Stackerman phy_type = ixgb_phy_type_txn17201; 237129794Stackerman } 238129794Stackerman else { 239129794Stackerman DEBUGOUT("Identified G6005 optics\n"); 240129794Stackerman phy_type = ixgb_phy_type_g6005; 241129794Stackerman } 242129794Stackerman break; 243129794Stackerman 244129794Stackerman 245129794Stackerman default: 246129794Stackerman DEBUGOUT("Unknown physical layer module\n"); 247129794Stackerman phy_type = ixgb_phy_type_unknown; 248129794Stackerman break; 249129794Stackerman } 250129794Stackerman 251129794Stackerman return (phy_type); 252129794Stackerman} 253129794Stackerman 254129794Stackerman/****************************************************************************** 255129794Stackerman * Performs basic configuration of the adapter. 256129794Stackerman * 257129794Stackerman * hw - Struct containing variables accessed by shared code 258129794Stackerman * 259129794Stackerman * Resets the controller. 260129794Stackerman * Reads and validates the EEPROM. 261129794Stackerman * Initializes the receive address registers. 262129794Stackerman * Initializes the multicast table. 263129794Stackerman * Clears all on-chip counters. 264129794Stackerman * Calls routine to setup flow control settings. 265129794Stackerman * Leaves the transmit and receive units disabled and uninitialized. 266129794Stackerman * 267129794Stackerman * Returns: 268129794Stackerman * TRUE if successful, 269129794Stackerman * FALSE if unrecoverable problems were encountered. 270129794Stackerman *****************************************************************************/ 271129794Stackermanboolean_t 272129794Stackermanixgb_init_hw(struct ixgb_hw *hw) 273129794Stackerman{ 274129794Stackerman uint32_t i; 275129794Stackerman uint32_t ctrl_reg; 276129794Stackerman boolean_t status; 277129794Stackerman 278129794Stackerman DEBUGFUNC("ixgb_init_hw"); 279129794Stackerman 280129794Stackerman /* Issue a global reset to the MAC. This will reset the chip's 281129794Stackerman * transmit, receive, DMA, and link units. It will not effect 282129794Stackerman * the current PCI configuration. The global reset bit is self- 283129794Stackerman * clearing, and should clear within a microsecond. 284129794Stackerman */ 285129794Stackerman DEBUGOUT("Issuing a global reset to MAC\n"); 286129794Stackerman 287129794Stackerman ctrl_reg = ixgb_mac_reset(hw); 288129794Stackerman 289129794Stackerman DEBUGOUT("Issuing an EE reset to MAC\n"); 290129794Stackerman#ifdef HP_ZX1 291129794Stackerman /* Workaround for 82597EX reset errata */ 292129794Stackerman IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST); 293129794Stackerman#else 294129794Stackerman IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST); 295129794Stackerman#endif 296129794Stackerman 297129794Stackerman /* Delay a few ms just to allow the reset to complete */ 298129794Stackerman msec_delay(IXGB_DELAY_AFTER_EE_RESET); 299129794Stackerman 300129794Stackerman if (ixgb_get_eeprom_data(hw) == FALSE) { 301129794Stackerman return(FALSE); 302129794Stackerman } 303129794Stackerman 304129794Stackerman /* Use the device id to determine the type of phy/transceiver. */ 305129794Stackerman hw->device_id = ixgb_get_ee_device_id(hw); 306129794Stackerman hw->phy_type = ixgb_identify_phy(hw); 307129794Stackerman 308129794Stackerman /* Setup the receive addresses. 309129794Stackerman * Receive Address Registers (RARs 0 - 15). 310129794Stackerman */ 311129794Stackerman ixgb_init_rx_addrs(hw); 312129794Stackerman 313129794Stackerman /* 314129794Stackerman * Check that a valid MAC address has been set. 315129794Stackerman * If it is not valid, we fail hardware init. 316129794Stackerman */ 317129794Stackerman if (!mac_addr_valid(hw->curr_mac_addr)) { 318129794Stackerman DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n"); 319129794Stackerman return(FALSE); 320129794Stackerman } 321129794Stackerman 322129794Stackerman /* tell the routines in this file they can access hardware again */ 323129794Stackerman hw->adapter_stopped = FALSE; 324129794Stackerman 325129794Stackerman /* Fill in the bus_info structure */ 326129794Stackerman ixgb_get_bus_info(hw); 327129794Stackerman 328129794Stackerman /* Zero out the Multicast HASH table */ 329129794Stackerman DEBUGOUT("Zeroing the MTA\n"); 330129794Stackerman for(i = 0; i < IXGB_MC_TBL_SIZE; i++) 331129794Stackerman IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); 332129794Stackerman 333129794Stackerman /* Zero out the VLAN Filter Table Array */ 334129794Stackerman ixgb_clear_vfta(hw); 335129794Stackerman 336129794Stackerman /* Zero all of the hardware counters */ 337129794Stackerman ixgb_clear_hw_cntrs(hw); 338129794Stackerman 339129794Stackerman /* Call a subroutine to setup flow control. */ 340129794Stackerman status = ixgb_setup_fc(hw); 341129794Stackerman 342129794Stackerman /* 82597EX errata: Call check-for-link in case lane deskew is locked */ 343129794Stackerman ixgb_check_for_link(hw); 344129794Stackerman 345129794Stackerman return (status); 346129794Stackerman} 347129794Stackerman 348129794Stackerman/****************************************************************************** 349129794Stackerman * Initializes receive address filters. 350129794Stackerman * 351129794Stackerman * hw - Struct containing variables accessed by shared code 352129794Stackerman * 353129794Stackerman * Places the MAC address in receive address register 0 and clears the rest 354129794Stackerman * of the receive addresss registers. Clears the multicast table. Assumes 355129794Stackerman * the receiver is in reset when the routine is called. 356129794Stackerman *****************************************************************************/ 357129794Stackermanvoid 358129794Stackermanixgb_init_rx_addrs(struct ixgb_hw *hw) 359129794Stackerman{ 360129794Stackerman uint32_t i; 361129794Stackerman 362129794Stackerman DEBUGFUNC("ixgb_init_rx_addrs"); 363129794Stackerman 364129794Stackerman /* 365129794Stackerman * If the current mac address is valid, assume it is a software override 366129794Stackerman * to the permanent address. 367129794Stackerman * Otherwise, use the permanent address from the eeprom. 368129794Stackerman */ 369129794Stackerman if (!mac_addr_valid(hw->curr_mac_addr)) { 370129794Stackerman 371129794Stackerman /* Get the MAC address from the eeprom for later reference */ 372129794Stackerman ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr); 373129794Stackerman 374129794Stackerman DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ", 375129794Stackerman hw->curr_mac_addr[0], 376129794Stackerman hw->curr_mac_addr[1], 377129794Stackerman hw->curr_mac_addr[2]); 378129794Stackerman DEBUGOUT3("%.2X %.2X %.2X\n", 379129794Stackerman hw->curr_mac_addr[3], 380129794Stackerman hw->curr_mac_addr[4], 381129794Stackerman hw->curr_mac_addr[5]); 382129794Stackerman } else { 383129794Stackerman 384129794Stackerman /* Setup the receive address. */ 385129794Stackerman DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 386129794Stackerman DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 387129794Stackerman hw->curr_mac_addr[0], 388129794Stackerman hw->curr_mac_addr[1], 389129794Stackerman hw->curr_mac_addr[2]); 390129794Stackerman DEBUGOUT3("%.2X %.2X %.2X\n", 391129794Stackerman hw->curr_mac_addr[3], 392129794Stackerman hw->curr_mac_addr[4], 393129794Stackerman hw->curr_mac_addr[5]); 394129794Stackerman 395129794Stackerman 396129794Stackerman ixgb_rar_set(hw, hw->curr_mac_addr, 0); 397129794Stackerman } 398129794Stackerman 399129794Stackerman /* Zero out the other 15 receive addresses. */ 400129794Stackerman DEBUGOUT("Clearing RAR[1-15]\n"); 401129794Stackerman for(i = 1; i < IXGB_RAR_ENTRIES; i++) { 402129794Stackerman IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 403129794Stackerman IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 404129794Stackerman } 405129794Stackerman 406129794Stackerman return; 407129794Stackerman} 408129794Stackerman 409129794Stackerman/****************************************************************************** 410129794Stackerman * Updates the MAC's list of multicast addresses. 411129794Stackerman * 412129794Stackerman * hw - Struct containing variables accessed by shared code 413129794Stackerman * mc_addr_list - the list of new multicast addresses 414129794Stackerman * mc_addr_count - number of addresses 415129794Stackerman * pad - number of bytes between addresses in the list 416129794Stackerman * 417129794Stackerman * The given list replaces any existing list. Clears the last 15 receive 418129794Stackerman * address registers and the multicast table. Uses receive address registers 419129794Stackerman * for the first 15 multicast addresses, and hashes the rest into the 420129794Stackerman * multicast table. 421129794Stackerman *****************************************************************************/ 422129794Stackermanvoid 423129794Stackermanixgb_mc_addr_list_update(struct ixgb_hw *hw, 424129794Stackerman uint8_t *mc_addr_list, 425129794Stackerman uint32_t mc_addr_count, 426129794Stackerman uint32_t pad) 427129794Stackerman{ 428129794Stackerman uint32_t hash_value; 429129794Stackerman uint32_t i; 430129794Stackerman uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */ 431129794Stackerman 432129794Stackerman DEBUGFUNC("ixgb_mc_addr_list_update"); 433129794Stackerman 434129794Stackerman /* Set the new number of MC addresses that we are being requested to use. */ 435129794Stackerman hw->num_mc_addrs = mc_addr_count; 436129794Stackerman 437129794Stackerman /* Clear RAR[1-15] */ 438129794Stackerman DEBUGOUT(" Clearing RAR[1-15]\n"); 439129794Stackerman for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) { 440129794Stackerman IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 441129794Stackerman IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 442129794Stackerman } 443129794Stackerman 444129794Stackerman /* Clear the MTA */ 445129794Stackerman DEBUGOUT(" Clearing MTA\n"); 446129794Stackerman for(i = 0; i < IXGB_MC_TBL_SIZE; i++) { 447129794Stackerman IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); 448129794Stackerman } 449129794Stackerman 450129794Stackerman /* Add the new addresses */ 451129794Stackerman for(i = 0; i < mc_addr_count; i++) { 452129794Stackerman DEBUGOUT(" Adding the multicast addresses:\n"); 453129794Stackerman DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 454129794Stackerman mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)], 455129794Stackerman mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 1], 456129794Stackerman mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 2], 457129794Stackerman mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 3], 458129794Stackerman mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 4], 459129794Stackerman mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 5]); 460129794Stackerman 461129794Stackerman /* Place this multicast address in the RAR if there is room, * 462129794Stackerman * else put it in the MTA 463129794Stackerman */ 464129794Stackerman if(rar_used_count < IXGB_RAR_ENTRIES) { 465129794Stackerman ixgb_rar_set(hw, 466129794Stackerman mc_addr_list + (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)), 467129794Stackerman rar_used_count); 468129794Stackerman DEBUGOUT1("Added a multicast address to RAR[%d]\n", i); 469129794Stackerman rar_used_count++; 470129794Stackerman } else { 471129794Stackerman hash_value = ixgb_hash_mc_addr(hw, 472129794Stackerman mc_addr_list + 473129794Stackerman (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad))); 474129794Stackerman 475129794Stackerman DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 476129794Stackerman 477129794Stackerman ixgb_mta_set(hw, hash_value); 478129794Stackerman } 479129794Stackerman } 480129794Stackerman 481129794Stackerman DEBUGOUT("MC Update Complete\n"); 482129794Stackerman return; 483129794Stackerman} 484129794Stackerman 485129794Stackerman/****************************************************************************** 486129794Stackerman * Hashes an address to determine its location in the multicast table 487129794Stackerman * 488129794Stackerman * hw - Struct containing variables accessed by shared code 489129794Stackerman * mc_addr - the multicast address to hash 490129794Stackerman * 491129794Stackerman * Returns: 492129794Stackerman * The hash value 493129794Stackerman *****************************************************************************/ 494129794Stackermanstatic uint32_t 495129794Stackermanixgb_hash_mc_addr(struct ixgb_hw *hw, 496129794Stackerman uint8_t *mc_addr) 497129794Stackerman{ 498129794Stackerman uint32_t hash_value = 0; 499129794Stackerman 500129794Stackerman DEBUGFUNC("ixgb_hash_mc_addr"); 501129794Stackerman 502129794Stackerman /* The portion of the address that is used for the hash table is 503129794Stackerman * determined by the mc_filter_type setting. 504129794Stackerman */ 505129794Stackerman switch (hw->mc_filter_type) { 506129794Stackerman /* [0] [1] [2] [3] [4] [5] 507129794Stackerman * 01 AA 00 12 34 56 508129794Stackerman * LSB MSB - According to H/W docs */ 509129794Stackerman case 0: 510129794Stackerman /* [47:36] i.e. 0x563 for above example address */ 511129794Stackerman hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); 512129794Stackerman break; 513129794Stackerman case 1: /* [46:35] i.e. 0xAC6 for above example address */ 514129794Stackerman hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); 515129794Stackerman break; 516129794Stackerman case 2: /* [45:34] i.e. 0x5D8 for above example address */ 517129794Stackerman hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); 518129794Stackerman break; 519129794Stackerman case 3: /* [43:32] i.e. 0x634 for above example address */ 520129794Stackerman hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); 521129794Stackerman break; 522129794Stackerman default: 523129794Stackerman /* Invalid mc_filter_type, what should we do? */ 524129794Stackerman DEBUGOUT("MC filter type param set incorrectly\n"); 525129794Stackerman ASSERT(0); 526129794Stackerman break; 527129794Stackerman } 528129794Stackerman 529129794Stackerman hash_value &= 0xFFF; 530129794Stackerman return (hash_value); 531129794Stackerman} 532129794Stackerman 533129794Stackerman/****************************************************************************** 534129794Stackerman * Sets the bit in the multicast table corresponding to the hash value. 535129794Stackerman * 536129794Stackerman * hw - Struct containing variables accessed by shared code 537129794Stackerman * hash_value - Multicast address hash value 538129794Stackerman *****************************************************************************/ 539129794Stackermanstatic void 540129794Stackermanixgb_mta_set(struct ixgb_hw *hw, 541129794Stackerman uint32_t hash_value) 542129794Stackerman{ 543129794Stackerman uint32_t hash_bit, hash_reg; 544129794Stackerman uint32_t mta_reg; 545129794Stackerman 546129794Stackerman /* The MTA is a register array of 128 32-bit registers. 547129794Stackerman * It is treated like an array of 4096 bits. We want to set 548129794Stackerman * bit BitArray[hash_value]. So we figure out what register 549129794Stackerman * the bit is in, read it, OR in the new bit, then write 550129794Stackerman * back the new value. The register is determined by the 551129794Stackerman * upper 7 bits of the hash value and the bit within that 552129794Stackerman * register are determined by the lower 5 bits of the value. 553129794Stackerman */ 554129794Stackerman hash_reg = (hash_value >> 5) & 0x7F; 555129794Stackerman hash_bit = hash_value & 0x1F; 556129794Stackerman 557129794Stackerman mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg); 558129794Stackerman 559129794Stackerman mta_reg |= (1 << hash_bit); 560129794Stackerman 561129794Stackerman IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg); 562129794Stackerman 563129794Stackerman return; 564129794Stackerman} 565129794Stackerman 566129794Stackerman/****************************************************************************** 567129794Stackerman * Puts an ethernet address into a receive address register. 568129794Stackerman * 569129794Stackerman * hw - Struct containing variables accessed by shared code 570129794Stackerman * addr - Address to put into receive address register 571129794Stackerman * index - Receive address register to write 572129794Stackerman *****************************************************************************/ 573129794Stackermanvoid 574129794Stackermanixgb_rar_set(struct ixgb_hw *hw, 575129794Stackerman uint8_t *addr, 576129794Stackerman uint32_t index) 577129794Stackerman{ 578129794Stackerman uint32_t rar_low, rar_high; 579129794Stackerman 580129794Stackerman DEBUGFUNC("ixgb_rar_set"); 581129794Stackerman 582129794Stackerman /* HW expects these in little endian so we reverse the byte order 583129794Stackerman * from network order (big endian) to little endian 584129794Stackerman */ 585129794Stackerman rar_low = ((uint32_t) addr[0] | 586129794Stackerman ((uint32_t) addr[1] << 8) | 587129794Stackerman ((uint32_t) addr[2] << 16) | 588129794Stackerman ((uint32_t) addr[3] << 24)); 589129794Stackerman 590129794Stackerman rar_high = ((uint32_t) addr[4] | 591129794Stackerman ((uint32_t) addr[5] << 8) | 592129794Stackerman IXGB_RAH_AV); 593129794Stackerman 594129794Stackerman IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 595129794Stackerman IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 596129794Stackerman return; 597129794Stackerman} 598129794Stackerman 599129794Stackerman/****************************************************************************** 600129794Stackerman * Writes a value to the specified offset in the VLAN filter table. 601129794Stackerman * 602129794Stackerman * hw - Struct containing variables accessed by shared code 603129794Stackerman * offset - Offset in VLAN filer table to write 604129794Stackerman * value - Value to write into VLAN filter table 605129794Stackerman *****************************************************************************/ 606129794Stackermanvoid 607129794Stackermanixgb_write_vfta(struct ixgb_hw *hw, 608129794Stackerman uint32_t offset, 609129794Stackerman uint32_t value) 610129794Stackerman{ 611129794Stackerman IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value); 612129794Stackerman return; 613129794Stackerman} 614129794Stackerman 615129794Stackerman/****************************************************************************** 616129794Stackerman * Clears the VLAN filer table 617129794Stackerman * 618129794Stackerman * hw - Struct containing variables accessed by shared code 619129794Stackerman *****************************************************************************/ 620129794Stackermanvoid 621129794Stackermanixgb_clear_vfta(struct ixgb_hw *hw) 622129794Stackerman{ 623129794Stackerman uint32_t offset; 624129794Stackerman 625129794Stackerman for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++) 626129794Stackerman IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 627129794Stackerman return; 628129794Stackerman} 629129794Stackerman 630129794Stackerman/****************************************************************************** 631129794Stackerman * Configures the flow control settings based on SW configuration. 632129794Stackerman * 633129794Stackerman * hw - Struct containing variables accessed by shared code 634129794Stackerman *****************************************************************************/ 635129794Stackerman 636129794Stackermanboolean_t 637129794Stackermanixgb_setup_fc(struct ixgb_hw *hw) 638129794Stackerman{ 639129794Stackerman uint32_t ctrl_reg; 640129794Stackerman uint32_t pap_reg = 0; /* by default, assume no pause time */ 641129794Stackerman boolean_t status = TRUE; 642129794Stackerman 643129794Stackerman DEBUGFUNC("ixgb_setup_fc"); 644129794Stackerman 645129794Stackerman /* Get the current control reg 0 settings */ 646129794Stackerman ctrl_reg = IXGB_READ_REG(hw, CTRL0); 647129794Stackerman 648129794Stackerman /* Clear the Receive Pause Enable and Transmit Pause Enable bits */ 649129794Stackerman ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE); 650129794Stackerman 651129794Stackerman /* The possible values of the "flow_control" parameter are: 652129794Stackerman * 0: Flow control is completely disabled 653129794Stackerman * 1: Rx flow control is enabled (we can receive pause frames 654129794Stackerman * but not send pause frames). 655129794Stackerman * 2: Tx flow control is enabled (we can send pause frames 656129794Stackerman * but we do not support receiving pause frames). 657129794Stackerman * 3: Both Rx and TX flow control (symmetric) are enabled. 658129794Stackerman * other: Invalid. 659129794Stackerman */ 660129794Stackerman switch (hw->fc.type) { 661129794Stackerman case ixgb_fc_none: /* 0 */ 662129794Stackerman /* Set CMDC bit to disable Rx Flow control*/ 663129794Stackerman ctrl_reg |= (IXGB_CTRL0_CMDC); 664129794Stackerman break; 665129794Stackerman case ixgb_fc_rx_pause: /* 1 */ 666129794Stackerman /* RX Flow control is enabled, and TX Flow control is 667129794Stackerman * disabled. 668129794Stackerman */ 669129794Stackerman ctrl_reg |= (IXGB_CTRL0_RPE); 670129794Stackerman break; 671129794Stackerman case ixgb_fc_tx_pause: /* 2 */ 672129794Stackerman /* TX Flow control is enabled, and RX Flow control is 673129794Stackerman * disabled, by a software over-ride. 674129794Stackerman */ 675129794Stackerman ctrl_reg |= (IXGB_CTRL0_TPE); 676129794Stackerman pap_reg = hw->fc.pause_time; 677129794Stackerman break; 678129794Stackerman case ixgb_fc_full: /* 3 */ 679129794Stackerman /* Flow control (both RX and TX) is enabled by a software 680129794Stackerman * over-ride. 681129794Stackerman */ 682129794Stackerman ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE); 683129794Stackerman pap_reg = hw->fc.pause_time; 684129794Stackerman break; 685129794Stackerman default: 686129794Stackerman /* We should never get here. The value should be 0-3. */ 687129794Stackerman DEBUGOUT("Flow control param set incorrectly\n"); 688129794Stackerman ASSERT(0); 689129794Stackerman break; 690129794Stackerman } 691129794Stackerman 692129794Stackerman /* Write the new settings */ 693129794Stackerman IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); 694129794Stackerman 695129794Stackerman if (pap_reg != 0) { 696129794Stackerman IXGB_WRITE_REG(hw, PAP, pap_reg); 697129794Stackerman } 698129794Stackerman 699129794Stackerman /* Set the flow control receive threshold registers. Normally, 700129794Stackerman * these registers will be set to a default threshold that may be 701129794Stackerman * adjusted later by the driver's runtime code. However, if the 702129794Stackerman * ability to transmit pause frames in not enabled, then these 703129794Stackerman * registers will be set to 0. 704129794Stackerman */ 705129794Stackerman if(!(hw->fc.type & ixgb_fc_tx_pause)) { 706129794Stackerman IXGB_WRITE_REG(hw, FCRTL, 0); 707129794Stackerman IXGB_WRITE_REG(hw, FCRTH, 0); 708129794Stackerman } else { 709129794Stackerman /* We need to set up the Receive Threshold high and low water 710129794Stackerman * marks as well as (optionally) enabling the transmission of XON frames. 711129794Stackerman */ 712129794Stackerman if(hw->fc.send_xon) { 713129794Stackerman IXGB_WRITE_REG(hw, FCRTL, 714129794Stackerman (hw->fc.low_water | IXGB_FCRTL_XONE)); 715129794Stackerman } else { 716129794Stackerman IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water); 717129794Stackerman } 718129794Stackerman IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water); 719129794Stackerman } 720129794Stackerman return (status); 721129794Stackerman} 722129794Stackerman 723129794Stackerman/****************************************************************************** 724129794Stackerman * Reads a word from a device over the Management Data Interface (MDI) bus. 725129794Stackerman * This interface is used to manage Physical layer devices. 726129794Stackerman * 727129794Stackerman * hw - Struct containing variables accessed by hw code 728129794Stackerman * reg_address - Offset of device register being read. 729129794Stackerman * phy_address - Address of device on MDI. 730129794Stackerman * 731129794Stackerman * Returns: Data word (16 bits) from MDI device. 732129794Stackerman * 733129794Stackerman * The 82597EX has support for several MDI access methods. This routine 734129794Stackerman * uses the new protocol MDI Single Command and Address Operation. 735129794Stackerman * This requires that first an address cycle command is sent, followed by a 736129794Stackerman * read command. 737129794Stackerman *****************************************************************************/ 738129794Stackermanuint16_t 739129794Stackermanixgb_read_phy_reg(struct ixgb_hw *hw, 740129794Stackerman uint32_t reg_address, 741129794Stackerman uint32_t phy_address, 742129794Stackerman uint32_t device_type) 743129794Stackerman{ 744129794Stackerman uint32_t i; 745129794Stackerman uint32_t data; 746129794Stackerman uint32_t command = 0; 747129794Stackerman 748129794Stackerman ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS); 749129794Stackerman ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS); 750129794Stackerman ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE); 751129794Stackerman 752129794Stackerman /* Setup and write the address cycle command */ 753129794Stackerman command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 754129794Stackerman (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 755129794Stackerman (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 756129794Stackerman (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND)); 757129794Stackerman 758129794Stackerman IXGB_WRITE_REG(hw, MSCA, command); 759129794Stackerman 760129794Stackerman /************************************************************** 761129794Stackerman ** Check every 10 usec to see if the address cycle completed 762129794Stackerman ** The COMMAND bit will clear when the operation is complete. 763129794Stackerman ** This may take as long as 64 usecs (we'll wait 100 usecs max) 764129794Stackerman ** from the CPU Write to the Ready bit assertion. 765129794Stackerman **************************************************************/ 766129794Stackerman 767129794Stackerman for (i = 0; i < 10; i++) 768129794Stackerman { 769129794Stackerman usec_delay(10); 770129794Stackerman 771129794Stackerman command = IXGB_READ_REG(hw, MSCA); 772129794Stackerman 773129794Stackerman if ((command & IXGB_MSCA_MDI_COMMAND) == 0) 774129794Stackerman break; 775129794Stackerman } 776129794Stackerman 777129794Stackerman ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 778129794Stackerman 779129794Stackerman /* Address cycle complete, setup and write the read command */ 780129794Stackerman command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 781129794Stackerman (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 782129794Stackerman (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 783129794Stackerman (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND)); 784129794Stackerman 785129794Stackerman IXGB_WRITE_REG(hw, MSCA, command); 786129794Stackerman 787129794Stackerman /************************************************************** 788129794Stackerman ** Check every 10 usec to see if the read command completed 789129794Stackerman ** The COMMAND bit will clear when the operation is complete. 790129794Stackerman ** The read may take as long as 64 usecs (we'll wait 100 usecs max) 791129794Stackerman ** from the CPU Write to the Ready bit assertion. 792129794Stackerman **************************************************************/ 793129794Stackerman 794129794Stackerman for (i = 0; i < 10; i++) 795129794Stackerman { 796129794Stackerman usec_delay(10); 797129794Stackerman 798129794Stackerman command = IXGB_READ_REG(hw, MSCA); 799129794Stackerman 800129794Stackerman if ((command & IXGB_MSCA_MDI_COMMAND) == 0) 801129794Stackerman break; 802129794Stackerman } 803129794Stackerman 804129794Stackerman ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 805129794Stackerman 806129794Stackerman /* Operation is complete, get the data from the MDIO Read/Write Data 807129794Stackerman * register and return. 808129794Stackerman */ 809129794Stackerman data = IXGB_READ_REG(hw, MSRWD); 810129794Stackerman data >>= IXGB_MSRWD_READ_DATA_SHIFT; 811129794Stackerman return((uint16_t) data); 812129794Stackerman} 813129794Stackerman 814129794Stackerman/****************************************************************************** 815129794Stackerman * Writes a word to a device over the Management Data Interface (MDI) bus. 816129794Stackerman * This interface is used to manage Physical layer devices. 817129794Stackerman * 818129794Stackerman * hw - Struct containing variables accessed by hw code 819129794Stackerman * reg_address - Offset of device register being read. 820129794Stackerman * phy_address - Address of device on MDI. 821129794Stackerman * device_type - Also known as the Device ID or DID. 822129794Stackerman * data - 16-bit value to be written 823129794Stackerman * 824129794Stackerman * Returns: void. 825129794Stackerman * 826129794Stackerman * The 82597EX has support for several MDI access methods. This routine 827129794Stackerman * uses the new protocol MDI Single Command and Address Operation. 828129794Stackerman * This requires that first an address cycle command is sent, followed by a 829129794Stackerman * write command. 830129794Stackerman *****************************************************************************/ 831129794Stackermanvoid 832129794Stackermanixgb_write_phy_reg(struct ixgb_hw *hw, 833129794Stackerman uint32_t reg_address, 834129794Stackerman uint32_t phy_address, 835129794Stackerman uint32_t device_type, 836129794Stackerman uint16_t data) 837129794Stackerman{ 838129794Stackerman uint32_t i; 839129794Stackerman uint32_t command = 0; 840129794Stackerman 841129794Stackerman ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS); 842129794Stackerman ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS); 843129794Stackerman ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE); 844129794Stackerman 845129794Stackerman /* Put the data in the MDIO Read/Write Data register */ 846129794Stackerman IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data); 847129794Stackerman 848129794Stackerman /* Setup and write the address cycle command */ 849129794Stackerman command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 850129794Stackerman (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 851129794Stackerman (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 852129794Stackerman (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND)); 853129794Stackerman 854129794Stackerman IXGB_WRITE_REG(hw, MSCA, command); 855129794Stackerman 856129794Stackerman /************************************************************** 857129794Stackerman ** Check every 10 usec to see if the address cycle completed 858129794Stackerman ** The COMMAND bit will clear when the operation is complete. 859129794Stackerman ** This may take as long as 64 usecs (we'll wait 100 usecs max) 860129794Stackerman ** from the CPU Write to the Ready bit assertion. 861129794Stackerman **************************************************************/ 862129794Stackerman 863129794Stackerman for (i = 0; i < 10; i++) 864129794Stackerman { 865129794Stackerman usec_delay(10); 866129794Stackerman 867129794Stackerman command = IXGB_READ_REG(hw, MSCA); 868129794Stackerman 869129794Stackerman if ((command & IXGB_MSCA_MDI_COMMAND) == 0) 870129794Stackerman break; 871129794Stackerman } 872129794Stackerman 873129794Stackerman ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 874129794Stackerman 875129794Stackerman /* Address cycle complete, setup and write the write command */ 876129794Stackerman command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 877129794Stackerman (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 878129794Stackerman (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 879129794Stackerman (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND)); 880129794Stackerman 881129794Stackerman IXGB_WRITE_REG(hw, MSCA, command); 882129794Stackerman 883129794Stackerman /************************************************************** 884129794Stackerman ** Check every 10 usec to see if the read command completed 885129794Stackerman ** The COMMAND bit will clear when the operation is complete. 886129794Stackerman ** The write may take as long as 64 usecs (we'll wait 100 usecs max) 887129794Stackerman ** from the CPU Write to the Ready bit assertion. 888129794Stackerman **************************************************************/ 889129794Stackerman 890129794Stackerman for (i = 0; i < 10; i++) 891129794Stackerman { 892129794Stackerman usec_delay(10); 893129794Stackerman 894129794Stackerman command = IXGB_READ_REG(hw, MSCA); 895129794Stackerman 896129794Stackerman if ((command & IXGB_MSCA_MDI_COMMAND) == 0) 897129794Stackerman break; 898129794Stackerman } 899129794Stackerman 900129794Stackerman ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 901129794Stackerman 902129794Stackerman /* Operation is complete, return. */ 903129794Stackerman} 904129794Stackerman 905129794Stackerman 906129794Stackerman/****************************************************************************** 907129794Stackerman * Checks to see if the link status of the hardware has changed. 908129794Stackerman * 909129794Stackerman * hw - Struct containing variables accessed by hw code 910129794Stackerman * 911129794Stackerman * Called by any function that needs to check the link status of the adapter. 912129794Stackerman *****************************************************************************/ 913129794Stackermanvoid 914129794Stackermanixgb_check_for_link(struct ixgb_hw *hw) 915129794Stackerman{ 916129794Stackerman uint32_t status_reg; 917129794Stackerman uint32_t xpcss_reg; 918129794Stackerman 919129794Stackerman DEBUGFUNC("ixgb_check_for_link"); 920129794Stackerman 921129794Stackerman xpcss_reg = IXGB_READ_REG(hw, XPCSS); 922129794Stackerman status_reg = IXGB_READ_REG(hw, STATUS); 923129794Stackerman 924129794Stackerman if ((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) && 925129794Stackerman (status_reg & IXGB_STATUS_LU)) { 926129794Stackerman hw->link_up = TRUE; 927129794Stackerman } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) && 928129794Stackerman (status_reg & IXGB_STATUS_LU)) { 929129794Stackerman DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n"); 930129794Stackerman hw->link_up = ixgb_link_reset(hw); 931129794Stackerman } else { 932129794Stackerman /* 933129794Stackerman * 82597EX errata. Since the lane deskew problem may prevent 934129794Stackerman * link, reset the link before reporting link down. 935129794Stackerman */ 936129794Stackerman hw->link_up = ixgb_link_reset(hw); 937129794Stackerman } 938129794Stackerman /* Anything else for 10 Gig?? */ 939129794Stackerman} 940129794Stackerman 941129794Stackerman/****************************************************************************** 942129794Stackerman * Check for a bad link condition that may have occured. 943129794Stackerman * The indication is that the RFC / LFC registers may be incrementing 944129794Stackerman * continually. A full adapter reset is required to recover. 945129794Stackerman * 946129794Stackerman * hw - Struct containing variables accessed by hw code 947129794Stackerman * 948129794Stackerman * Called by any function that needs to check the link status of the adapter. 949129794Stackerman *****************************************************************************/ 950129794Stackermanboolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw) 951129794Stackerman{ 952129794Stackerman uint32_t newLFC, newRFC; 953129794Stackerman boolean_t bad_link_returncode = FALSE; 954129794Stackerman 955129794Stackerman if (hw->phy_type == ixgb_phy_type_txn17401) { 956129794Stackerman newLFC = IXGB_READ_REG(hw, LFC); 957129794Stackerman newRFC = IXGB_READ_REG(hw, RFC); 958129794Stackerman if ((hw->lastLFC + 250 < newLFC) || (hw->lastRFC + 250 < newRFC)) { 959129794Stackerman DEBUGOUT("BAD LINK! too many LFC/RFC since last check\n"); 960129794Stackerman bad_link_returncode = TRUE; 961129794Stackerman } 962129794Stackerman hw->lastLFC = newLFC; 963129794Stackerman hw->lastRFC = newRFC; 964129794Stackerman } 965129794Stackerman 966129794Stackerman return bad_link_returncode; 967129794Stackerman} 968129794Stackerman 969129794Stackerman 970129794Stackerman/****************************************************************************** 971129794Stackerman * Clears all hardware statistics counters. 972129794Stackerman * 973129794Stackerman * hw - Struct containing variables accessed by shared code 974129794Stackerman *****************************************************************************/ 975129794Stackermanvoid 976129794Stackermanixgb_clear_hw_cntrs(struct ixgb_hw *hw) 977129794Stackerman{ 978129794Stackerman volatile uint32_t temp_reg; 979129794Stackerman 980129794Stackerman DEBUGFUNC("ixgb_clear_hw_cntrs"); 981129794Stackerman 982129794Stackerman /* if we are stopped or resetting exit gracefully */ 983129794Stackerman if(hw->adapter_stopped) { 984129794Stackerman DEBUGOUT("Exiting because the adapter is stopped!!!\n"); 985129794Stackerman return; 986129794Stackerman } 987129794Stackerman 988129794Stackerman temp_reg = IXGB_READ_REG(hw, TPRL); 989129794Stackerman temp_reg = IXGB_READ_REG(hw, TPRH); 990129794Stackerman temp_reg = IXGB_READ_REG(hw, GPRCL); 991129794Stackerman temp_reg = IXGB_READ_REG(hw, GPRCH); 992129794Stackerman temp_reg = IXGB_READ_REG(hw, BPRCL); 993129794Stackerman temp_reg = IXGB_READ_REG(hw, BPRCH); 994129794Stackerman temp_reg = IXGB_READ_REG(hw, MPRCL); 995129794Stackerman temp_reg = IXGB_READ_REG(hw, MPRCH); 996129794Stackerman temp_reg = IXGB_READ_REG(hw, UPRCL); 997129794Stackerman temp_reg = IXGB_READ_REG(hw, UPRCH); 998129794Stackerman temp_reg = IXGB_READ_REG(hw, VPRCL); 999129794Stackerman temp_reg = IXGB_READ_REG(hw, VPRCH); 1000129794Stackerman temp_reg = IXGB_READ_REG(hw, JPRCL); 1001129794Stackerman temp_reg = IXGB_READ_REG(hw, JPRCH); 1002129794Stackerman temp_reg = IXGB_READ_REG(hw, GORCL); 1003129794Stackerman temp_reg = IXGB_READ_REG(hw, GORCH); 1004129794Stackerman temp_reg = IXGB_READ_REG(hw, TORL); 1005129794Stackerman temp_reg = IXGB_READ_REG(hw, TORH); 1006129794Stackerman temp_reg = IXGB_READ_REG(hw, RNBC); 1007129794Stackerman temp_reg = IXGB_READ_REG(hw, RUC); 1008129794Stackerman temp_reg = IXGB_READ_REG(hw, ROC); 1009129794Stackerman temp_reg = IXGB_READ_REG(hw, RLEC); 1010129794Stackerman temp_reg = IXGB_READ_REG(hw, CRCERRS); 1011129794Stackerman temp_reg = IXGB_READ_REG(hw, ICBC); 1012129794Stackerman temp_reg = IXGB_READ_REG(hw, ECBC); 1013129794Stackerman temp_reg = IXGB_READ_REG(hw, MPC); 1014129794Stackerman temp_reg = IXGB_READ_REG(hw, TPTL); 1015129794Stackerman temp_reg = IXGB_READ_REG(hw, TPTH); 1016129794Stackerman temp_reg = IXGB_READ_REG(hw, GPTCL); 1017129794Stackerman temp_reg = IXGB_READ_REG(hw, GPTCH); 1018129794Stackerman temp_reg = IXGB_READ_REG(hw, BPTCL); 1019129794Stackerman temp_reg = IXGB_READ_REG(hw, BPTCH); 1020129794Stackerman temp_reg = IXGB_READ_REG(hw, MPTCL); 1021129794Stackerman temp_reg = IXGB_READ_REG(hw, MPTCH); 1022129794Stackerman temp_reg = IXGB_READ_REG(hw, UPTCL); 1023129794Stackerman temp_reg = IXGB_READ_REG(hw, UPTCH); 1024129794Stackerman temp_reg = IXGB_READ_REG(hw, VPTCL); 1025129794Stackerman temp_reg = IXGB_READ_REG(hw, VPTCH); 1026129794Stackerman temp_reg = IXGB_READ_REG(hw, JPTCL); 1027129794Stackerman temp_reg = IXGB_READ_REG(hw, JPTCH); 1028129794Stackerman temp_reg = IXGB_READ_REG(hw, GOTCL); 1029129794Stackerman temp_reg = IXGB_READ_REG(hw, GOTCH); 1030129794Stackerman temp_reg = IXGB_READ_REG(hw, TOTL); 1031129794Stackerman temp_reg = IXGB_READ_REG(hw, TOTH); 1032129794Stackerman temp_reg = IXGB_READ_REG(hw, DC); 1033129794Stackerman temp_reg = IXGB_READ_REG(hw, PLT64C); 1034129794Stackerman temp_reg = IXGB_READ_REG(hw, TSCTC); 1035129794Stackerman temp_reg = IXGB_READ_REG(hw, TSCTFC); 1036129794Stackerman temp_reg = IXGB_READ_REG(hw, IBIC); 1037129794Stackerman temp_reg = IXGB_READ_REG(hw, RFC); 1038129794Stackerman temp_reg = IXGB_READ_REG(hw, LFC); 1039129794Stackerman temp_reg = IXGB_READ_REG(hw, PFRC); 1040129794Stackerman temp_reg = IXGB_READ_REG(hw, PFTC); 1041129794Stackerman temp_reg = IXGB_READ_REG(hw, MCFRC); 1042129794Stackerman temp_reg = IXGB_READ_REG(hw, MCFTC); 1043129794Stackerman temp_reg = IXGB_READ_REG(hw, XONRXC); 1044129794Stackerman temp_reg = IXGB_READ_REG(hw, XONTXC); 1045129794Stackerman temp_reg = IXGB_READ_REG(hw, XOFFRXC); 1046129794Stackerman temp_reg = IXGB_READ_REG(hw, XOFFTXC); 1047129794Stackerman temp_reg = IXGB_READ_REG(hw, RJC); 1048129794Stackerman return; 1049129794Stackerman} 1050129794Stackerman 1051129794Stackerman 1052129794Stackerman/****************************************************************************** 1053129794Stackerman * Turns on the software controllable LED 1054129794Stackerman * 1055129794Stackerman * hw - Struct containing variables accessed by shared code 1056129794Stackerman *****************************************************************************/ 1057129794Stackermanvoid 1058129794Stackermanixgb_led_on(struct ixgb_hw *hw) 1059129794Stackerman{ 1060129794Stackerman uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0); 1061129794Stackerman 1062129794Stackerman /* To turn on the LED, clear software-definable pin 0 (SDP0). */ 1063129794Stackerman ctrl0_reg &= ~IXGB_CTRL0_SDP0; 1064129794Stackerman IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); 1065129794Stackerman return; 1066129794Stackerman} 1067129794Stackerman 1068129794Stackerman/****************************************************************************** 1069129794Stackerman * Turns off the software controllable LED 1070129794Stackerman * 1071129794Stackerman * hw - Struct containing variables accessed by shared code 1072129794Stackerman *****************************************************************************/ 1073129794Stackermanvoid 1074129794Stackermanixgb_led_off(struct ixgb_hw *hw) 1075129794Stackerman{ 1076129794Stackerman uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0); 1077129794Stackerman 1078129794Stackerman /* To turn off the LED, set software-definable pin 0 (SDP0). */ 1079129794Stackerman ctrl0_reg |= IXGB_CTRL0_SDP0; 1080129794Stackerman IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); 1081129794Stackerman return; 1082129794Stackerman} 1083129794Stackerman 1084129794Stackerman 1085129794Stackerman/****************************************************************************** 1086129794Stackerman * Gets the current PCI bus type, speed, and width of the hardware 1087129794Stackerman * 1088129794Stackerman * hw - Struct containing variables accessed by shared code 1089129794Stackerman *****************************************************************************/ 1090129794Stackermanstatic void 1091129794Stackermanixgb_get_bus_info(struct ixgb_hw *hw) 1092129794Stackerman{ 1093129794Stackerman uint32_t status_reg; 1094129794Stackerman 1095129794Stackerman status_reg = IXGB_READ_REG(hw, STATUS); 1096129794Stackerman 1097129794Stackerman hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ? 1098129794Stackerman ixgb_bus_type_pcix : ixgb_bus_type_pci; 1099129794Stackerman 1100129794Stackerman if (hw->bus.type == ixgb_bus_type_pci) { 1101129794Stackerman hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ? 1102129794Stackerman ixgb_bus_speed_66 : ixgb_bus_speed_33; 1103129794Stackerman } else { 1104129794Stackerman switch (status_reg & IXGB_STATUS_PCIX_SPD_MASK) { 1105129794Stackerman case IXGB_STATUS_PCIX_SPD_66: 1106129794Stackerman hw->bus.speed = ixgb_bus_speed_66; 1107129794Stackerman break; 1108129794Stackerman case IXGB_STATUS_PCIX_SPD_100: 1109129794Stackerman hw->bus.speed = ixgb_bus_speed_100; 1110129794Stackerman break; 1111129794Stackerman case IXGB_STATUS_PCIX_SPD_133: 1112129794Stackerman hw->bus.speed = ixgb_bus_speed_133; 1113129794Stackerman break; 1114129794Stackerman default: 1115129794Stackerman hw->bus.speed = ixgb_bus_speed_reserved; 1116129794Stackerman break; 1117129794Stackerman } 1118129794Stackerman } 1119129794Stackerman 1120129794Stackerman hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ? 1121129794Stackerman ixgb_bus_width_64 : ixgb_bus_width_32; 1122129794Stackerman 1123129794Stackerman return; 1124129794Stackerman} 1125129794Stackerman 1126129794Stackerman 1127129794Stackerman 1128129794Stackerman/****************************************************************************** 1129129794Stackerman * Tests a MAC address to ensure it is a valid Individual Address 1130129794Stackerman * 1131129794Stackerman * mac_addr - pointer to MAC address. 1132129794Stackerman * 1133129794Stackerman *****************************************************************************/ 1134129794Stackermanboolean_t 1135129794Stackermanmac_addr_valid(uint8_t *mac_addr) 1136129794Stackerman{ 1137129794Stackerman boolean_t is_valid = TRUE; 1138129794Stackerman DEBUGFUNC("mac_addr_valid"); 1139129794Stackerman 1140129794Stackerman 1141129794Stackerman /* Make sure it is not a multicast address */ 1142129794Stackerman if (IS_MULTICAST(mac_addr)) { 1143129794Stackerman DEBUGOUT("MAC address is multicast\n"); 1144129794Stackerman is_valid = FALSE; 1145129794Stackerman } 1146129794Stackerman /* Not a broadcast address */ 1147129794Stackerman else if (IS_BROADCAST(mac_addr)) { 1148129794Stackerman DEBUGOUT("MAC address is broadcast\n"); 1149129794Stackerman is_valid = FALSE; 1150129794Stackerman } 1151129794Stackerman /* Reject the zero address */ 1152129794Stackerman else if (mac_addr[0] == 0 && 1153129794Stackerman mac_addr[1] == 0 && 1154129794Stackerman mac_addr[2] == 0 && 1155129794Stackerman mac_addr[3] == 0 && 1156129794Stackerman mac_addr[4] == 0 && 1157129794Stackerman mac_addr[5] == 0) { 1158129794Stackerman DEBUGOUT("MAC address is all zeros\n"); 1159129794Stackerman is_valid = FALSE; 1160129794Stackerman } 1161129794Stackerman return (is_valid); 1162129794Stackerman} 1163129794Stackerman 1164129794Stackerman/****************************************************************************** 1165129794Stackerman * Resets the 10GbE link. Waits the settle time and returns the state of 1166129794Stackerman * the link. 1167129794Stackerman * 1168129794Stackerman * hw - Struct containing variables accessed by shared code 1169129794Stackerman *****************************************************************************/ 1170129794Stackermanboolean_t 1171129794Stackermanixgb_link_reset(struct ixgb_hw *hw) 1172129794Stackerman{ 1173129794Stackerman boolean_t link_status = FALSE; 1174129794Stackerman uint8_t wait_retries = MAX_RESET_ITERATIONS; 1175129794Stackerman uint8_t lrst_retries = MAX_RESET_ITERATIONS; 1176129794Stackerman 1177129794Stackerman 1178129794Stackerman do { 1179129794Stackerman /* Reset the link */ 1180129794Stackerman IXGB_WRITE_REG(hw, CTRL0, IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST); 1181129794Stackerman 1182129794Stackerman /* Wait for link-up and lane re-alignment */ 1183129794Stackerman do { 1184129794Stackerman usec_delay(IXGB_DELAY_USECS_AFTER_LINK_RESET); 1185129794Stackerman link_status = ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU) && 1186129794Stackerman (IXGB_READ_REG(hw, XPCSS) & IXGB_XPCSS_ALIGN_STATUS)) ? 1187129794Stackerman TRUE : FALSE; 1188129794Stackerman } while (!link_status && -- wait_retries); 1189129794Stackerman 1190129794Stackerman } while (!link_status && --lrst_retries); 1191129794Stackerman 1192129794Stackerman return link_status; 1193129794Stackerman} 1194129794Stackerman 1195129794Stackerman 1196129794Stackerman 1197129794Stackerman/****************************************************************************** 1198129794Stackerman * Resets the 10GbE optics module. 1199129794Stackerman * 1200129794Stackerman * hw - Struct containing variables accessed by shared code 1201129794Stackerman *****************************************************************************/ 1202129794Stackermanvoid 1203129794Stackermanixgb_optics_reset(struct ixgb_hw *hw) 1204129794Stackerman{ 1205129794Stackerman if (hw->phy_type == ixgb_phy_type_txn17401) { 1206129794Stackerman uint16_t mdio_reg; 1207129794Stackerman 1208129794Stackerman ixgb_write_phy_reg( hw, 1209129794Stackerman MDIO_PMA_PMD_CR1, 1210129794Stackerman IXGB_PHY_ADDRESS, 1211129794Stackerman MDIO_PMA_PMD_DID, 1212129794Stackerman MDIO_PMA_PMD_CR1_RESET); 1213129794Stackerman 1214129794Stackerman mdio_reg = ixgb_read_phy_reg( hw, 1215129794Stackerman MDIO_PMA_PMD_CR1, 1216129794Stackerman IXGB_PHY_ADDRESS, 1217129794Stackerman MDIO_PMA_PMD_DID); 1218129794Stackerman } 1219129794Stackerman 1220129794Stackerman return; 1221129794Stackerman} 1222129794Stackerman 1223