/freebsd-10.2-release/sys/dev/drm/ |
H A D | r128_state.c | 53 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3)); 54 OUT_RING(boxes[0].x1); 55 OUT_RING(boxes[0].x2 - 1); 56 OUT_RING(boxes[0].y1); 57 OUT_RING(boxes[0].y2 - 1); 62 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3)); 63 OUT_RING(boxes[1].x1); 64 OUT_RING(boxes[1].x2 - 1); 65 OUT_RING(boxes[1].y1); 66 OUT_RING(boxe [all...] |
H A D | r600_blit.c | 1220 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 1221 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); 1222 OUT_RING(gpu_addr >> 8); 1223 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0)); 1224 OUT_RING(2 << 0); 1227 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 1228 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); 1229 OUT_RING(gpu_addr >> 8); 1232 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 1233 OUT_RING((R600_CB_COLOR0_SIZ [all...] |
H A D | radeon_state.c | 437 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); 438 OUT_RING((box->y1 << 16) | box->x1); 439 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); 440 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1)); 469 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6)); 470 OUT_RING(ctx->pp_misc); 471 OUT_RING(ctx->pp_fog_color); 472 OUT_RING(ctx->re_solid_color); 473 OUT_RING(ctx->rb3d_blendcntl); 474 OUT_RING(ct [all...] |
H A D | r300_cmdbuf.c | 74 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1)); 106 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) | 108 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) | 120 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1)); 121 OUT_RING(0); 122 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK); 147 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 148 OUT_RING(R300_RB3D_DC_FLUSH); 151 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); 152 OUT_RING(RADEON_WAIT_3D_IDLECLEA [all...] |
H A D | i915_dma.c | 375 OUT_RING(cmd); 382 OUT_RING(cmd); 387 OUT_RING(0); 414 OUT_RING(GFX_OP_DRAWRECT_INFO_I965); 415 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); 416 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); 417 OUT_RING(DR4); 421 OUT_RING(GFX_OP_DRAWRECT_INFO); 422 OUT_RING(DR1); 423 OUT_RING((bo [all...] |
H A D | radeon_drv.h | 1908 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1910 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1911 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1917 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1919 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1920 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1926 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1928 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1929 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1936 OUT_RING( CP_PACKET 2091 #define OUT_RING macro [all...] |
H A D | mach64_dma.c | 638 #define OUT_RING( x ) \ macro 641 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 681 OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); 682 OUT_RING( page ); 683 OUT_RING( MACH64_DMA_CHUNKSIZE | MACH64_DMA_HOLD_OFFSET ); 684 OUT_RING( 0 ); 696 OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); 697 OUT_RING( page ); 698 OUT_RING( remainder | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL ); 699 OUT_RING( [all...] |
H A D | i915_irq.c | 287 OUT_RING(MI_STORE_DWORD_INDEX); 288 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 289 OUT_RING(dev_priv->counter); 290 OUT_RING(MI_USER_INTERRUPT);
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H A D | r128_drv.h | 457 OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \ 458 OUT_RING( R128_EVENT_CRTC_OFFSET ); \ 520 #define OUT_RING( x ) do { \ macro 522 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
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H A D | r600_cp.c | 2133 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); 2134 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); 2136 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); 2137 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); 2138 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); 2155 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); 2156 OUT_RING(0x00000001); 2158 OUT_RING(0x00000003); 2160 OUT_RING(0x00000000); 2161 OUT_RING((dev_pri [all...] |
H A D | i915_drv.h | 590 #define OUT_RING(n) do { \ macro 591 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
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H A D | radeon_cp.c | 584 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); 585 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
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/freebsd-10.2-release/sys/dev/drm2/radeon/ |
H A D | r600_blit.c | 66 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 67 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); 68 OUT_RING(gpu_addr >> 8); 69 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0)); 70 OUT_RING(2 << 0); 73 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 74 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); 75 OUT_RING(gpu_addr >> 8); 78 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 79 OUT_RING((R600_CB_COLOR0_SIZ [all...] |
H A D | radeon_state.c | 459 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); 460 OUT_RING((box->y1 << 16) | box->x1); 461 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); 462 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1)); 491 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6)); 492 OUT_RING(ctx->pp_misc); 493 OUT_RING(ctx->pp_fog_color); 494 OUT_RING(ctx->re_solid_color); 495 OUT_RING(ctx->rb3d_blendcntl); 496 OUT_RING(ct [all...] |
H A D | r300_cmdbuf.c | 74 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1)); 106 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) | 108 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) | 120 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1)); 121 OUT_RING(0); 122 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK); 147 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 148 OUT_RING(R300_RB3D_DC_FLUSH); 151 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); 152 OUT_RING(RADEON_WAIT_3D_IDLECLEA [all...] |
H A D | radeon_drv.h | 1936 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1937 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1942 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1943 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1948 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1949 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1955 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1956 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1961 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1962 OUT_RING(RADEON_RB3D_DC_FLUS 2109 #define OUT_RING macro [all...] |
H A D | r600_cp.c | 2328 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); 2329 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); 2331 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); 2332 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); 2333 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); 2350 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); 2351 OUT_RING(0x00000001); 2353 OUT_RING(0x00000003); 2355 OUT_RING(0x00000000); 2356 OUT_RING((dev_pri [all...] |
H A D | radeon_cp.c | 619 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1)); 620 OUT_RING(5); /* scratch reg 5 */ 621 OUT_RING(0xdeadbeef); 628 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); 629 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D | 669 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 670 OUT_RING(R300_RB3D_DC_FINISH);
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/freebsd-10.2-release/sys/dev/drm2/i915/ |
H A D | i915_dma.c | 44 #define OUT_RING(x) \ macro 399 OUT_RING(cmd); 406 OUT_RING(cmd); 411 OUT_RING(0); 450 OUT_RING(GFX_OP_DRAWRECT_INFO_I965); 451 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); 452 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); 453 OUT_RING(DR4); 459 OUT_RING(GFX_OP_DRAWRECT_INFO); 460 OUT_RING(DR [all...] |