1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2008-2009 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2008 Red Hat Inc. 4254885Sdumbbell * 5254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 6254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 7254885Sdumbbell * to deal in the Software without restriction, including without limitation 8254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 10254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 11254885Sdumbbell * 12254885Sdumbbell * The above copyright notice and this permission notice (including the next 13254885Sdumbbell * paragraph) shall be included in all copies or substantial portions of the 14254885Sdumbbell * Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22254885Sdumbbell * DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell * Authors: 25254885Sdumbbell * Dave Airlie <airlied@redhat.com> 26254885Sdumbbell * Alex Deucher <alexander.deucher@amd.com> 27254885Sdumbbell */ 28254885Sdumbbell 29254885Sdumbbell#include <sys/cdefs.h> 30254885Sdumbbell__FBSDID("$FreeBSD: releng/10.2/sys/dev/drm2/radeon/r600_cp.c 282199 2015-04-28 19:35:05Z dumbbell $"); 31254885Sdumbbell 32254885Sdumbbell#include <sys/param.h> 33254885Sdumbbell#include <sys/systm.h> 34254885Sdumbbell#include <sys/linker.h> 35254885Sdumbbell#include <sys/firmware.h> 36254885Sdumbbell 37254885Sdumbbell#include <dev/drm2/drmP.h> 38254885Sdumbbell#include <dev/drm2/radeon/radeon_drm.h> 39254885Sdumbbell#include "radeon_drv.h" 40254885Sdumbbell#include "r600_cp.h" 41254885Sdumbbell 42254885Sdumbbell#define PFP_UCODE_SIZE 576 43254885Sdumbbell#define PM4_UCODE_SIZE 1792 44254885Sdumbbell#define R700_PFP_UCODE_SIZE 848 45254885Sdumbbell#define R700_PM4_UCODE_SIZE 1360 46254885Sdumbbell 47282199Sdumbbell#ifdef __linux__ 48282199Sdumbbell/* Firmware Names */ 49282199SdumbbellMODULE_FIRMWARE("radeon/R600_pfp.bin"); 50282199SdumbbellMODULE_FIRMWARE("radeon/R600_me.bin"); 51282199SdumbbellMODULE_FIRMWARE("radeon/RV610_pfp.bin"); 52282199SdumbbellMODULE_FIRMWARE("radeon/RV610_me.bin"); 53282199SdumbbellMODULE_FIRMWARE("radeon/RV630_pfp.bin"); 54282199SdumbbellMODULE_FIRMWARE("radeon/RV630_me.bin"); 55282199SdumbbellMODULE_FIRMWARE("radeon/RV620_pfp.bin"); 56282199SdumbbellMODULE_FIRMWARE("radeon/RV620_me.bin"); 57282199SdumbbellMODULE_FIRMWARE("radeon/RV635_pfp.bin"); 58282199SdumbbellMODULE_FIRMWARE("radeon/RV635_me.bin"); 59282199SdumbbellMODULE_FIRMWARE("radeon/RV670_pfp.bin"); 60282199SdumbbellMODULE_FIRMWARE("radeon/RV670_me.bin"); 61282199SdumbbellMODULE_FIRMWARE("radeon/RS780_pfp.bin"); 62282199SdumbbellMODULE_FIRMWARE("radeon/RS780_me.bin"); 63282199SdumbbellMODULE_FIRMWARE("radeon/RV770_pfp.bin"); 64282199SdumbbellMODULE_FIRMWARE("radeon/RV770_me.bin"); 65282199SdumbbellMODULE_FIRMWARE("radeon/RV730_pfp.bin"); 66282199SdumbbellMODULE_FIRMWARE("radeon/RV730_me.bin"); 67282199SdumbbellMODULE_FIRMWARE("radeon/RV710_pfp.bin"); 68282199SdumbbellMODULE_FIRMWARE("radeon/RV710_me.bin"); 69282199Sdumbbell#endif 70282199Sdumbbell 71282199Sdumbbell 72282199Sdumbbell#ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */ 73282199Sdumbbellint r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, 74282199Sdumbbell unsigned family, u32 *ib, int *l); 75282199Sdumbbellvoid r600_cs_legacy_init(void); 76282199Sdumbbell#endif 77282199Sdumbbell 78254885Sdumbbell# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ 79254885Sdumbbell# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) 80254885Sdumbbell 81254885Sdumbbell#define R600_PTE_VALID (1 << 0) 82254885Sdumbbell#define R600_PTE_SYSTEM (1 << 1) 83254885Sdumbbell#define R600_PTE_SNOOPED (1 << 2) 84254885Sdumbbell#define R600_PTE_READABLE (1 << 5) 85254885Sdumbbell#define R600_PTE_WRITEABLE (1 << 6) 86254885Sdumbbell 87254885Sdumbbell/* MAX values used for gfx init */ 88254885Sdumbbell#define R6XX_MAX_SH_GPRS 256 89254885Sdumbbell#define R6XX_MAX_TEMP_GPRS 16 90254885Sdumbbell#define R6XX_MAX_SH_THREADS 256 91254885Sdumbbell#define R6XX_MAX_SH_STACK_ENTRIES 4096 92254885Sdumbbell#define R6XX_MAX_BACKENDS 8 93254885Sdumbbell#define R6XX_MAX_BACKENDS_MASK 0xff 94254885Sdumbbell#define R6XX_MAX_SIMDS 8 95254885Sdumbbell#define R6XX_MAX_SIMDS_MASK 0xff 96254885Sdumbbell#define R6XX_MAX_PIPES 8 97254885Sdumbbell#define R6XX_MAX_PIPES_MASK 0xff 98254885Sdumbbell 99254885Sdumbbell#define R7XX_MAX_SH_GPRS 256 100254885Sdumbbell#define R7XX_MAX_TEMP_GPRS 16 101254885Sdumbbell#define R7XX_MAX_SH_THREADS 256 102254885Sdumbbell#define R7XX_MAX_SH_STACK_ENTRIES 4096 103254885Sdumbbell#define R7XX_MAX_BACKENDS 8 104254885Sdumbbell#define R7XX_MAX_BACKENDS_MASK 0xff 105254885Sdumbbell#define R7XX_MAX_SIMDS 16 106254885Sdumbbell#define R7XX_MAX_SIMDS_MASK 0xffff 107254885Sdumbbell#define R7XX_MAX_PIPES 8 108254885Sdumbbell#define R7XX_MAX_PIPES_MASK 0xff 109254885Sdumbbell 110254885Sdumbbellstatic int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) 111254885Sdumbbell{ 112254885Sdumbbell int i; 113254885Sdumbbell 114254885Sdumbbell dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 115254885Sdumbbell 116254885Sdumbbell for (i = 0; i < dev_priv->usec_timeout; i++) { 117254885Sdumbbell int slots; 118254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 119254885Sdumbbell slots = (RADEON_READ(R600_GRBM_STATUS) 120254885Sdumbbell & R700_CMDFIFO_AVAIL_MASK); 121254885Sdumbbell else 122254885Sdumbbell slots = (RADEON_READ(R600_GRBM_STATUS) 123254885Sdumbbell & R600_CMDFIFO_AVAIL_MASK); 124254885Sdumbbell if (slots >= entries) 125254885Sdumbbell return 0; 126254885Sdumbbell DRM_UDELAY(1); 127254885Sdumbbell } 128254885Sdumbbell DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n", 129254885Sdumbbell RADEON_READ(R600_GRBM_STATUS), 130254885Sdumbbell RADEON_READ(R600_GRBM_STATUS2)); 131254885Sdumbbell 132254885Sdumbbell return -EBUSY; 133254885Sdumbbell} 134254885Sdumbbell 135254885Sdumbbellstatic int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) 136254885Sdumbbell{ 137254885Sdumbbell int i, ret; 138254885Sdumbbell 139254885Sdumbbell dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 140254885Sdumbbell 141254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 142254885Sdumbbell ret = r600_do_wait_for_fifo(dev_priv, 8); 143254885Sdumbbell else 144254885Sdumbbell ret = r600_do_wait_for_fifo(dev_priv, 16); 145254885Sdumbbell if (ret) 146254885Sdumbbell return ret; 147254885Sdumbbell for (i = 0; i < dev_priv->usec_timeout; i++) { 148254885Sdumbbell if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE)) 149254885Sdumbbell return 0; 150254885Sdumbbell DRM_UDELAY(1); 151254885Sdumbbell } 152254885Sdumbbell DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n", 153254885Sdumbbell RADEON_READ(R600_GRBM_STATUS), 154254885Sdumbbell RADEON_READ(R600_GRBM_STATUS2)); 155254885Sdumbbell 156254885Sdumbbell return -EBUSY; 157254885Sdumbbell} 158254885Sdumbbell 159254885Sdumbbellvoid r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) 160254885Sdumbbell{ 161254885Sdumbbell struct drm_sg_mem *entry = dev->sg; 162254885Sdumbbell#ifdef __linux__ 163254885Sdumbbell int max_pages; 164254885Sdumbbell int pages; 165254885Sdumbbell int i; 166254885Sdumbbell#endif 167254885Sdumbbell 168254885Sdumbbell if (!entry) 169254885Sdumbbell return; 170254885Sdumbbell 171254885Sdumbbell if (gart_info->bus_addr) { 172254885Sdumbbell#ifdef __linux__ 173254885Sdumbbell max_pages = (gart_info->table_size / sizeof(u64)); 174254885Sdumbbell pages = (entry->pages <= max_pages) 175254885Sdumbbell ? entry->pages : max_pages; 176254885Sdumbbell 177254885Sdumbbell for (i = 0; i < pages; i++) { 178254885Sdumbbell if (!entry->busaddr[i]) 179254885Sdumbbell break; 180254885Sdumbbell pci_unmap_page(dev->pdev, entry->busaddr[i], 181254885Sdumbbell PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 182254885Sdumbbell } 183254885Sdumbbell#endif 184254885Sdumbbell if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) 185254885Sdumbbell gart_info->bus_addr = 0; 186254885Sdumbbell } 187254885Sdumbbell} 188254885Sdumbbell 189254885Sdumbbell/* R600 has page table setup */ 190254885Sdumbbellint r600_page_table_init(struct drm_device *dev) 191254885Sdumbbell{ 192254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 193254885Sdumbbell struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; 194254885Sdumbbell struct drm_local_map *map = &gart_info->mapping; 195254885Sdumbbell struct drm_sg_mem *entry = dev->sg; 196254885Sdumbbell int ret = 0; 197254885Sdumbbell int i, j; 198254885Sdumbbell int pages; 199254885Sdumbbell u64 page_base; 200254885Sdumbbell dma_addr_t entry_addr; 201254885Sdumbbell int max_ati_pages, max_real_pages, gart_idx; 202254885Sdumbbell 203254885Sdumbbell /* okay page table is available - lets rock */ 204254885Sdumbbell max_ati_pages = (gart_info->table_size / sizeof(u64)); 205254885Sdumbbell max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); 206254885Sdumbbell 207254885Sdumbbell pages = (entry->pages <= max_real_pages) ? 208254885Sdumbbell entry->pages : max_real_pages; 209254885Sdumbbell 210254885Sdumbbell memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64)); 211254885Sdumbbell 212254885Sdumbbell gart_idx = 0; 213254885Sdumbbell for (i = 0; i < pages; i++) { 214254885Sdumbbell#ifdef __linux__ 215254885Sdumbbell entry->busaddr[i] = pci_map_page(dev->pdev, 216254885Sdumbbell entry->pagelist[i], 0, 217254885Sdumbbell PAGE_SIZE, 218254885Sdumbbell PCI_DMA_BIDIRECTIONAL); 219254885Sdumbbell if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) { 220254885Sdumbbell DRM_ERROR("unable to map PCIGART pages!\n"); 221254885Sdumbbell r600_page_table_cleanup(dev, gart_info); 222254885Sdumbbell goto done; 223254885Sdumbbell } 224254885Sdumbbell#endif 225254885Sdumbbell entry_addr = entry->busaddr[i]; 226254885Sdumbbell for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { 227254885Sdumbbell page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK; 228254885Sdumbbell page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 229254885Sdumbbell page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 230254885Sdumbbell 231254885Sdumbbell DRM_WRITE64(map, gart_idx * sizeof(u64), page_base); 232254885Sdumbbell 233254885Sdumbbell gart_idx++; 234254885Sdumbbell 235254885Sdumbbell if ((i % 128) == 0) 236254885Sdumbbell DRM_DEBUG("page entry %d: 0x%016llx\n", 237254885Sdumbbell i, (unsigned long long)page_base); 238254885Sdumbbell entry_addr += ATI_PCIGART_PAGE_SIZE; 239254885Sdumbbell } 240254885Sdumbbell } 241254885Sdumbbell ret = 1; 242254885Sdumbbell#ifdef __linux__ 243254885Sdumbbelldone: 244254885Sdumbbell#endif 245254885Sdumbbell return ret; 246254885Sdumbbell} 247254885Sdumbbell 248254885Sdumbbellstatic void r600_vm_flush_gart_range(struct drm_device *dev) 249254885Sdumbbell{ 250254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 251254885Sdumbbell u32 resp, countdown = 1000; 252254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12); 253254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 254254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2); 255254885Sdumbbell 256254885Sdumbbell do { 257254885Sdumbbell resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE); 258254885Sdumbbell countdown--; 259254885Sdumbbell DRM_UDELAY(1); 260254885Sdumbbell } while (((resp & 0xf0) == 0) && countdown); 261254885Sdumbbell} 262254885Sdumbbell 263254885Sdumbbellstatic void r600_vm_init(struct drm_device *dev) 264254885Sdumbbell{ 265254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 266254885Sdumbbell /* initialise the VM to use the page table we constructed up there */ 267254885Sdumbbell u32 vm_c0, i; 268254885Sdumbbell u32 mc_rd_a; 269254885Sdumbbell u32 vm_l2_cntl, vm_l2_cntl3; 270254885Sdumbbell /* okay set up the PCIE aperture type thingo */ 271254885Sdumbbell RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 272254885Sdumbbell RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 273254885Sdumbbell RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 274254885Sdumbbell 275254885Sdumbbell /* setup MC RD a */ 276254885Sdumbbell mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS | 277254885Sdumbbell R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) | 278254885Sdumbbell R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY; 279254885Sdumbbell 280254885Sdumbbell RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a); 281254885Sdumbbell RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a); 282254885Sdumbbell 283254885Sdumbbell RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a); 284254885Sdumbbell RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a); 285254885Sdumbbell 286254885Sdumbbell RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a); 287254885Sdumbbell RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a); 288254885Sdumbbell 289254885Sdumbbell RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a); 290254885Sdumbbell RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a); 291254885Sdumbbell 292254885Sdumbbell RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING); 293254885Sdumbbell RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/); 294254885Sdumbbell 295254885Sdumbbell RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a); 296254885Sdumbbell RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a); 297254885Sdumbbell 298254885Sdumbbell RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE); 299254885Sdumbbell RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a); 300254885Sdumbbell 301254885Sdumbbell vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 302254885Sdumbbell vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7); 303254885Sdumbbell RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 304254885Sdumbbell 305254885Sdumbbell RADEON_WRITE(R600_VM_L2_CNTL2, 0); 306254885Sdumbbell vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) | 307254885Sdumbbell R600_VM_L2_CNTL3_BANK_SELECT_1(1) | 308254885Sdumbbell R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2)); 309254885Sdumbbell RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 310254885Sdumbbell 311254885Sdumbbell vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 312254885Sdumbbell 313254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 314254885Sdumbbell 315254885Sdumbbell vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 316254885Sdumbbell 317254885Sdumbbell /* disable all other contexts */ 318254885Sdumbbell for (i = 1; i < 8; i++) 319254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 320254885Sdumbbell 321254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 322254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 323254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 324254885Sdumbbell 325254885Sdumbbell r600_vm_flush_gart_range(dev); 326254885Sdumbbell} 327254885Sdumbbell 328254885Sdumbbellstatic int r600_cp_init_microcode(drm_radeon_private_t *dev_priv) 329254885Sdumbbell{ 330254885Sdumbbell const char *chip_name; 331254885Sdumbbell size_t pfp_req_size, me_req_size; 332254885Sdumbbell char fw_name[30]; 333254885Sdumbbell int err; 334254885Sdumbbell 335254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 336254885Sdumbbell case CHIP_R600: chip_name = "R600"; break; 337254885Sdumbbell case CHIP_RV610: chip_name = "RV610"; break; 338254885Sdumbbell case CHIP_RV630: chip_name = "RV630"; break; 339254885Sdumbbell case CHIP_RV620: chip_name = "RV620"; break; 340254885Sdumbbell case CHIP_RV635: chip_name = "RV635"; break; 341254885Sdumbbell case CHIP_RV670: chip_name = "RV670"; break; 342254885Sdumbbell case CHIP_RS780: 343254885Sdumbbell case CHIP_RS880: chip_name = "RS780"; break; 344254885Sdumbbell case CHIP_RV770: chip_name = "RV770"; break; 345254885Sdumbbell case CHIP_RV730: 346254885Sdumbbell case CHIP_RV740: chip_name = "RV730"; break; 347254885Sdumbbell case CHIP_RV710: chip_name = "RV710"; break; 348254885Sdumbbell default: panic("%s: Unsupported family %d", __func__, dev_priv->flags & RADEON_FAMILY_MASK); 349254885Sdumbbell } 350254885Sdumbbell 351254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { 352254885Sdumbbell pfp_req_size = R700_PFP_UCODE_SIZE * 4; 353254885Sdumbbell me_req_size = R700_PM4_UCODE_SIZE * 4; 354254885Sdumbbell } else { 355254885Sdumbbell pfp_req_size = PFP_UCODE_SIZE * 4; 356254885Sdumbbell me_req_size = PM4_UCODE_SIZE * 12; 357254885Sdumbbell } 358254885Sdumbbell 359254885Sdumbbell DRM_INFO("Loading %s CP Microcode\n", chip_name); 360254885Sdumbbell err = 0; 361254885Sdumbbell 362254885Sdumbbell snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name); 363254885Sdumbbell dev_priv->pfp_fw = firmware_get(fw_name); 364254885Sdumbbell if (dev_priv->pfp_fw == NULL) { 365254885Sdumbbell err = -ENOENT; 366254885Sdumbbell goto out; 367254885Sdumbbell } 368254885Sdumbbell if (dev_priv->pfp_fw->datasize != pfp_req_size) { 369254885Sdumbbell DRM_ERROR( 370254885Sdumbbell "r600_cp: Bogus length %zu in firmware \"%s\"\n", 371254885Sdumbbell dev_priv->pfp_fw->datasize, fw_name); 372254885Sdumbbell err = -EINVAL; 373254885Sdumbbell goto out; 374254885Sdumbbell } 375254885Sdumbbell 376254885Sdumbbell snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name); 377254885Sdumbbell dev_priv->me_fw = firmware_get(fw_name); 378254885Sdumbbell if (dev_priv->me_fw == NULL) { 379254885Sdumbbell err = -ENOENT; 380254885Sdumbbell goto out; 381254885Sdumbbell } 382254885Sdumbbell if (dev_priv->me_fw->datasize != me_req_size) { 383254885Sdumbbell DRM_ERROR( 384254885Sdumbbell "r600_cp: Bogus length %zu in firmware \"%s\"\n", 385254885Sdumbbell dev_priv->me_fw->datasize, fw_name); 386254885Sdumbbell err = -EINVAL; 387254885Sdumbbell } 388254885Sdumbbellout: 389254885Sdumbbell if (err) { 390254885Sdumbbell if (err != -EINVAL) 391254885Sdumbbell DRM_ERROR( 392254885Sdumbbell "r600_cp: Failed to load firmware \"%s\"\n", 393254885Sdumbbell fw_name); 394254885Sdumbbell if (dev_priv->pfp_fw != NULL) { 395254885Sdumbbell firmware_put(dev_priv->pfp_fw, FIRMWARE_UNLOAD); 396254885Sdumbbell dev_priv->pfp_fw = NULL; 397254885Sdumbbell } 398254885Sdumbbell if (dev_priv->me_fw != NULL) { 399254885Sdumbbell firmware_put(dev_priv->me_fw, FIRMWARE_UNLOAD); 400254885Sdumbbell dev_priv->me_fw = NULL; 401254885Sdumbbell } 402254885Sdumbbell } 403254885Sdumbbell return err; 404254885Sdumbbell} 405254885Sdumbbell 406254885Sdumbbellstatic void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) 407254885Sdumbbell{ 408254885Sdumbbell const __be32 *fw_data; 409254885Sdumbbell int i; 410254885Sdumbbell 411254885Sdumbbell if (!dev_priv->me_fw || !dev_priv->pfp_fw) 412254885Sdumbbell return; 413254885Sdumbbell 414254885Sdumbbell r600_do_cp_stop(dev_priv); 415254885Sdumbbell 416254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 417254885Sdumbbell#ifdef __BIG_ENDIAN 418254885Sdumbbell R600_BUF_SWAP_32BIT | 419254885Sdumbbell#endif 420254885Sdumbbell R600_RB_NO_UPDATE | 421254885Sdumbbell R600_RB_BLKSZ(15) | 422254885Sdumbbell R600_RB_BUFSZ(3)); 423254885Sdumbbell 424254885Sdumbbell RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 425254885Sdumbbell RADEON_READ(R600_GRBM_SOFT_RESET); 426282199Sdumbbell mdelay(15); 427254885Sdumbbell RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 428254885Sdumbbell 429254885Sdumbbell fw_data = (const __be32 *)dev_priv->me_fw->data; 430254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 431254885Sdumbbell for (i = 0; i < PM4_UCODE_SIZE * 3; i++) 432254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_DATA, 433254885Sdumbbell be32_to_cpup(fw_data++)); 434254885Sdumbbell 435254885Sdumbbell fw_data = (const __be32 *)dev_priv->pfp_fw->data; 436254885Sdumbbell RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 437254885Sdumbbell for (i = 0; i < PFP_UCODE_SIZE; i++) 438254885Sdumbbell RADEON_WRITE(R600_CP_PFP_UCODE_DATA, 439254885Sdumbbell be32_to_cpup(fw_data++)); 440254885Sdumbbell 441254885Sdumbbell RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 442254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 443254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 444254885Sdumbbell 445254885Sdumbbell} 446254885Sdumbbell 447254885Sdumbbellstatic void r700_vm_init(struct drm_device *dev) 448254885Sdumbbell{ 449254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 450254885Sdumbbell /* initialise the VM to use the page table we constructed up there */ 451254885Sdumbbell u32 vm_c0, i; 452254885Sdumbbell u32 mc_vm_md_l1; 453254885Sdumbbell u32 vm_l2_cntl, vm_l2_cntl3; 454254885Sdumbbell /* okay set up the PCIE aperture type thingo */ 455254885Sdumbbell RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 456254885Sdumbbell RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 457254885Sdumbbell RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 458254885Sdumbbell 459254885Sdumbbell mc_vm_md_l1 = R700_ENABLE_L1_TLB | 460254885Sdumbbell R700_ENABLE_L1_FRAGMENT_PROCESSING | 461254885Sdumbbell R700_SYSTEM_ACCESS_MODE_IN_SYS | 462254885Sdumbbell R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 463254885Sdumbbell R700_EFFECTIVE_L1_TLB_SIZE(5) | 464254885Sdumbbell R700_EFFECTIVE_L1_QUEUE_SIZE(5); 465254885Sdumbbell 466254885Sdumbbell RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1); 467254885Sdumbbell RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1); 468254885Sdumbbell RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1); 469254885Sdumbbell RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1); 470254885Sdumbbell RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1); 471254885Sdumbbell RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1); 472254885Sdumbbell RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1); 473254885Sdumbbell 474254885Sdumbbell vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 475254885Sdumbbell vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7); 476254885Sdumbbell RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 477254885Sdumbbell 478254885Sdumbbell RADEON_WRITE(R600_VM_L2_CNTL2, 0); 479254885Sdumbbell vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2); 480254885Sdumbbell RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 481254885Sdumbbell 482254885Sdumbbell vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 483254885Sdumbbell 484254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 485254885Sdumbbell 486254885Sdumbbell vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 487254885Sdumbbell 488254885Sdumbbell /* disable all other contexts */ 489254885Sdumbbell for (i = 1; i < 8; i++) 490254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 491254885Sdumbbell 492254885Sdumbbell RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 493254885Sdumbbell RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 494254885Sdumbbell RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 495254885Sdumbbell 496254885Sdumbbell r600_vm_flush_gart_range(dev); 497254885Sdumbbell} 498254885Sdumbbell 499254885Sdumbbellstatic void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) 500254885Sdumbbell{ 501254885Sdumbbell const __be32 *fw_data; 502254885Sdumbbell int i; 503254885Sdumbbell 504254885Sdumbbell if (!dev_priv->me_fw || !dev_priv->pfp_fw) 505254885Sdumbbell return; 506254885Sdumbbell 507254885Sdumbbell r600_do_cp_stop(dev_priv); 508254885Sdumbbell 509254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 510254885Sdumbbell#ifdef __BIG_ENDIAN 511254885Sdumbbell R600_BUF_SWAP_32BIT | 512254885Sdumbbell#endif 513254885Sdumbbell R600_RB_NO_UPDATE | 514254885Sdumbbell R600_RB_BLKSZ(15) | 515254885Sdumbbell R600_RB_BUFSZ(3)); 516254885Sdumbbell 517254885Sdumbbell RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 518254885Sdumbbell RADEON_READ(R600_GRBM_SOFT_RESET); 519282199Sdumbbell mdelay(15); 520254885Sdumbbell RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 521254885Sdumbbell 522254885Sdumbbell fw_data = (const __be32 *)dev_priv->pfp_fw->data; 523254885Sdumbbell RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 524254885Sdumbbell for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 525254885Sdumbbell RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 526254885Sdumbbell RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 527254885Sdumbbell 528254885Sdumbbell fw_data = (const __be32 *)dev_priv->me_fw->data; 529254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 530254885Sdumbbell for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 531254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 532254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 533254885Sdumbbell 534254885Sdumbbell RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 535254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 536254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 537254885Sdumbbell 538254885Sdumbbell} 539254885Sdumbbell 540254885Sdumbbellstatic void r600_test_writeback(drm_radeon_private_t *dev_priv) 541254885Sdumbbell{ 542254885Sdumbbell u32 tmp; 543254885Sdumbbell 544254885Sdumbbell /* Start with assuming that writeback doesn't work */ 545254885Sdumbbell dev_priv->writeback_works = 0; 546254885Sdumbbell 547254885Sdumbbell /* Writeback doesn't seem to work everywhere, test it here and possibly 548254885Sdumbbell * enable it if it appears to work 549254885Sdumbbell */ 550254885Sdumbbell radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 551254885Sdumbbell 552254885Sdumbbell RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef); 553254885Sdumbbell 554254885Sdumbbell for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { 555254885Sdumbbell u32 val; 556254885Sdumbbell 557254885Sdumbbell val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1)); 558254885Sdumbbell if (val == 0xdeadbeef) 559254885Sdumbbell break; 560254885Sdumbbell DRM_UDELAY(1); 561254885Sdumbbell } 562254885Sdumbbell 563254885Sdumbbell if (tmp < dev_priv->usec_timeout) { 564254885Sdumbbell dev_priv->writeback_works = 1; 565254885Sdumbbell DRM_INFO("writeback test succeeded in %d usecs\n", tmp); 566254885Sdumbbell } else { 567254885Sdumbbell dev_priv->writeback_works = 0; 568254885Sdumbbell DRM_INFO("writeback test failed\n"); 569254885Sdumbbell } 570254885Sdumbbell if (radeon_no_wb == 1) { 571254885Sdumbbell dev_priv->writeback_works = 0; 572254885Sdumbbell DRM_INFO("writeback forced off\n"); 573254885Sdumbbell } 574254885Sdumbbell 575254885Sdumbbell if (!dev_priv->writeback_works) { 576254885Sdumbbell /* Disable writeback to avoid unnecessary bus master transfer */ 577254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 578254885Sdumbbell#ifdef __BIG_ENDIAN 579254885Sdumbbell R600_BUF_SWAP_32BIT | 580254885Sdumbbell#endif 581254885Sdumbbell RADEON_READ(R600_CP_RB_CNTL) | 582254885Sdumbbell R600_RB_NO_UPDATE); 583254885Sdumbbell RADEON_WRITE(R600_SCRATCH_UMSK, 0); 584254885Sdumbbell } 585254885Sdumbbell} 586254885Sdumbbell 587254885Sdumbbellint r600_do_engine_reset(struct drm_device *dev) 588254885Sdumbbell{ 589254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 590254885Sdumbbell u32 cp_ptr, cp_me_cntl, cp_rb_cntl; 591254885Sdumbbell 592254885Sdumbbell DRM_INFO("Resetting GPU\n"); 593254885Sdumbbell 594254885Sdumbbell cp_ptr = RADEON_READ(R600_CP_RB_WPTR); 595254885Sdumbbell cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL); 596254885Sdumbbell RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT); 597254885Sdumbbell 598254885Sdumbbell RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff); 599254885Sdumbbell RADEON_READ(R600_GRBM_SOFT_RESET); 600254885Sdumbbell DRM_UDELAY(50); 601254885Sdumbbell RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 602254885Sdumbbell RADEON_READ(R600_GRBM_SOFT_RESET); 603254885Sdumbbell 604254885Sdumbbell RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 605254885Sdumbbell cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL); 606254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 607254885Sdumbbell#ifdef __BIG_ENDIAN 608254885Sdumbbell R600_BUF_SWAP_32BIT | 609254885Sdumbbell#endif 610254885Sdumbbell R600_RB_RPTR_WR_ENA); 611254885Sdumbbell 612254885Sdumbbell RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr); 613254885Sdumbbell RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr); 614254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl); 615254885Sdumbbell RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl); 616254885Sdumbbell 617254885Sdumbbell /* Reset the CP ring */ 618254885Sdumbbell r600_do_cp_reset(dev_priv); 619254885Sdumbbell 620254885Sdumbbell /* The CP is no longer running after an engine reset */ 621254885Sdumbbell dev_priv->cp_running = 0; 622254885Sdumbbell 623254885Sdumbbell /* Reset any pending vertex, indirect buffers */ 624254885Sdumbbell radeon_freelist_reset(dev); 625254885Sdumbbell 626254885Sdumbbell return 0; 627254885Sdumbbell 628254885Sdumbbell} 629254885Sdumbbell 630254885Sdumbbellstatic u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 631254885Sdumbbell u32 num_backends, 632254885Sdumbbell u32 backend_disable_mask) 633254885Sdumbbell{ 634254885Sdumbbell u32 backend_map = 0; 635254885Sdumbbell u32 enabled_backends_mask; 636254885Sdumbbell u32 enabled_backends_count; 637254885Sdumbbell u32 cur_pipe; 638254885Sdumbbell u32 swizzle_pipe[R6XX_MAX_PIPES]; 639254885Sdumbbell u32 cur_backend; 640254885Sdumbbell u32 i; 641254885Sdumbbell 642254885Sdumbbell if (num_tile_pipes > R6XX_MAX_PIPES) 643254885Sdumbbell num_tile_pipes = R6XX_MAX_PIPES; 644254885Sdumbbell if (num_tile_pipes < 1) 645254885Sdumbbell num_tile_pipes = 1; 646254885Sdumbbell if (num_backends > R6XX_MAX_BACKENDS) 647254885Sdumbbell num_backends = R6XX_MAX_BACKENDS; 648254885Sdumbbell if (num_backends < 1) 649254885Sdumbbell num_backends = 1; 650254885Sdumbbell 651254885Sdumbbell enabled_backends_mask = 0; 652254885Sdumbbell enabled_backends_count = 0; 653254885Sdumbbell for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { 654254885Sdumbbell if (((backend_disable_mask >> i) & 1) == 0) { 655254885Sdumbbell enabled_backends_mask |= (1 << i); 656254885Sdumbbell ++enabled_backends_count; 657254885Sdumbbell } 658254885Sdumbbell if (enabled_backends_count == num_backends) 659254885Sdumbbell break; 660254885Sdumbbell } 661254885Sdumbbell 662254885Sdumbbell if (enabled_backends_count == 0) { 663254885Sdumbbell enabled_backends_mask = 1; 664254885Sdumbbell enabled_backends_count = 1; 665254885Sdumbbell } 666254885Sdumbbell 667254885Sdumbbell if (enabled_backends_count != num_backends) 668254885Sdumbbell num_backends = enabled_backends_count; 669254885Sdumbbell 670254885Sdumbbell memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); 671254885Sdumbbell switch (num_tile_pipes) { 672254885Sdumbbell case 1: 673254885Sdumbbell swizzle_pipe[0] = 0; 674254885Sdumbbell break; 675254885Sdumbbell case 2: 676254885Sdumbbell swizzle_pipe[0] = 0; 677254885Sdumbbell swizzle_pipe[1] = 1; 678254885Sdumbbell break; 679254885Sdumbbell case 3: 680254885Sdumbbell swizzle_pipe[0] = 0; 681254885Sdumbbell swizzle_pipe[1] = 1; 682254885Sdumbbell swizzle_pipe[2] = 2; 683254885Sdumbbell break; 684254885Sdumbbell case 4: 685254885Sdumbbell swizzle_pipe[0] = 0; 686254885Sdumbbell swizzle_pipe[1] = 1; 687254885Sdumbbell swizzle_pipe[2] = 2; 688254885Sdumbbell swizzle_pipe[3] = 3; 689254885Sdumbbell break; 690254885Sdumbbell case 5: 691254885Sdumbbell swizzle_pipe[0] = 0; 692254885Sdumbbell swizzle_pipe[1] = 1; 693254885Sdumbbell swizzle_pipe[2] = 2; 694254885Sdumbbell swizzle_pipe[3] = 3; 695254885Sdumbbell swizzle_pipe[4] = 4; 696254885Sdumbbell break; 697254885Sdumbbell case 6: 698254885Sdumbbell swizzle_pipe[0] = 0; 699254885Sdumbbell swizzle_pipe[1] = 2; 700254885Sdumbbell swizzle_pipe[2] = 4; 701254885Sdumbbell swizzle_pipe[3] = 5; 702254885Sdumbbell swizzle_pipe[4] = 1; 703254885Sdumbbell swizzle_pipe[5] = 3; 704254885Sdumbbell break; 705254885Sdumbbell case 7: 706254885Sdumbbell swizzle_pipe[0] = 0; 707254885Sdumbbell swizzle_pipe[1] = 2; 708254885Sdumbbell swizzle_pipe[2] = 4; 709254885Sdumbbell swizzle_pipe[3] = 6; 710254885Sdumbbell swizzle_pipe[4] = 1; 711254885Sdumbbell swizzle_pipe[5] = 3; 712254885Sdumbbell swizzle_pipe[6] = 5; 713254885Sdumbbell break; 714254885Sdumbbell case 8: 715254885Sdumbbell swizzle_pipe[0] = 0; 716254885Sdumbbell swizzle_pipe[1] = 2; 717254885Sdumbbell swizzle_pipe[2] = 4; 718254885Sdumbbell swizzle_pipe[3] = 6; 719254885Sdumbbell swizzle_pipe[4] = 1; 720254885Sdumbbell swizzle_pipe[5] = 3; 721254885Sdumbbell swizzle_pipe[6] = 5; 722254885Sdumbbell swizzle_pipe[7] = 7; 723254885Sdumbbell break; 724254885Sdumbbell } 725254885Sdumbbell 726254885Sdumbbell cur_backend = 0; 727254885Sdumbbell for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 728254885Sdumbbell while (((1 << cur_backend) & enabled_backends_mask) == 0) 729254885Sdumbbell cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 730254885Sdumbbell 731254885Sdumbbell backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 732254885Sdumbbell 733254885Sdumbbell cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 734254885Sdumbbell } 735254885Sdumbbell 736254885Sdumbbell return backend_map; 737254885Sdumbbell} 738254885Sdumbbell 739254885Sdumbbellstatic int r600_count_pipe_bits(uint32_t val) 740254885Sdumbbell{ 741254885Sdumbbell return hweight32(val); 742254885Sdumbbell} 743254885Sdumbbell 744254885Sdumbbellstatic void r600_gfx_init(struct drm_device *dev, 745254885Sdumbbell drm_radeon_private_t *dev_priv) 746254885Sdumbbell{ 747254885Sdumbbell int i, j, num_qd_pipes; 748254885Sdumbbell u32 sx_debug_1; 749254885Sdumbbell u32 tc_cntl; 750254885Sdumbbell u32 arb_pop; 751254885Sdumbbell u32 num_gs_verts_per_thread; 752254885Sdumbbell u32 vgt_gs_per_es; 753254885Sdumbbell u32 gs_prim_buffer_depth = 0; 754254885Sdumbbell u32 sq_ms_fifo_sizes; 755254885Sdumbbell u32 sq_config; 756254885Sdumbbell u32 sq_gpr_resource_mgmt_1 = 0; 757254885Sdumbbell u32 sq_gpr_resource_mgmt_2 = 0; 758254885Sdumbbell u32 sq_thread_resource_mgmt = 0; 759254885Sdumbbell u32 sq_stack_resource_mgmt_1 = 0; 760254885Sdumbbell u32 sq_stack_resource_mgmt_2 = 0; 761254885Sdumbbell u32 hdp_host_path_cntl; 762254885Sdumbbell u32 backend_map; 763254885Sdumbbell u32 gb_tiling_config = 0; 764254885Sdumbbell u32 cc_rb_backend_disable; 765254885Sdumbbell u32 cc_gc_shader_pipe_config; 766254885Sdumbbell u32 ramcfg; 767254885Sdumbbell 768254885Sdumbbell /* setup chip specs */ 769254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 770254885Sdumbbell case CHIP_R600: 771254885Sdumbbell dev_priv->r600_max_pipes = 4; 772254885Sdumbbell dev_priv->r600_max_tile_pipes = 8; 773254885Sdumbbell dev_priv->r600_max_simds = 4; 774254885Sdumbbell dev_priv->r600_max_backends = 4; 775254885Sdumbbell dev_priv->r600_max_gprs = 256; 776254885Sdumbbell dev_priv->r600_max_threads = 192; 777254885Sdumbbell dev_priv->r600_max_stack_entries = 256; 778254885Sdumbbell dev_priv->r600_max_hw_contexts = 8; 779254885Sdumbbell dev_priv->r600_max_gs_threads = 16; 780254885Sdumbbell dev_priv->r600_sx_max_export_size = 128; 781254885Sdumbbell dev_priv->r600_sx_max_export_pos_size = 16; 782254885Sdumbbell dev_priv->r600_sx_max_export_smx_size = 128; 783254885Sdumbbell dev_priv->r600_sq_num_cf_insts = 2; 784254885Sdumbbell break; 785254885Sdumbbell case CHIP_RV630: 786254885Sdumbbell case CHIP_RV635: 787254885Sdumbbell dev_priv->r600_max_pipes = 2; 788254885Sdumbbell dev_priv->r600_max_tile_pipes = 2; 789254885Sdumbbell dev_priv->r600_max_simds = 3; 790254885Sdumbbell dev_priv->r600_max_backends = 1; 791254885Sdumbbell dev_priv->r600_max_gprs = 128; 792254885Sdumbbell dev_priv->r600_max_threads = 192; 793254885Sdumbbell dev_priv->r600_max_stack_entries = 128; 794254885Sdumbbell dev_priv->r600_max_hw_contexts = 8; 795254885Sdumbbell dev_priv->r600_max_gs_threads = 4; 796254885Sdumbbell dev_priv->r600_sx_max_export_size = 128; 797254885Sdumbbell dev_priv->r600_sx_max_export_pos_size = 16; 798254885Sdumbbell dev_priv->r600_sx_max_export_smx_size = 128; 799254885Sdumbbell dev_priv->r600_sq_num_cf_insts = 2; 800254885Sdumbbell break; 801254885Sdumbbell case CHIP_RV610: 802254885Sdumbbell case CHIP_RS780: 803254885Sdumbbell case CHIP_RS880: 804254885Sdumbbell case CHIP_RV620: 805254885Sdumbbell dev_priv->r600_max_pipes = 1; 806254885Sdumbbell dev_priv->r600_max_tile_pipes = 1; 807254885Sdumbbell dev_priv->r600_max_simds = 2; 808254885Sdumbbell dev_priv->r600_max_backends = 1; 809254885Sdumbbell dev_priv->r600_max_gprs = 128; 810254885Sdumbbell dev_priv->r600_max_threads = 192; 811254885Sdumbbell dev_priv->r600_max_stack_entries = 128; 812254885Sdumbbell dev_priv->r600_max_hw_contexts = 4; 813254885Sdumbbell dev_priv->r600_max_gs_threads = 4; 814254885Sdumbbell dev_priv->r600_sx_max_export_size = 128; 815254885Sdumbbell dev_priv->r600_sx_max_export_pos_size = 16; 816254885Sdumbbell dev_priv->r600_sx_max_export_smx_size = 128; 817254885Sdumbbell dev_priv->r600_sq_num_cf_insts = 1; 818254885Sdumbbell break; 819254885Sdumbbell case CHIP_RV670: 820254885Sdumbbell dev_priv->r600_max_pipes = 4; 821254885Sdumbbell dev_priv->r600_max_tile_pipes = 4; 822254885Sdumbbell dev_priv->r600_max_simds = 4; 823254885Sdumbbell dev_priv->r600_max_backends = 4; 824254885Sdumbbell dev_priv->r600_max_gprs = 192; 825254885Sdumbbell dev_priv->r600_max_threads = 192; 826254885Sdumbbell dev_priv->r600_max_stack_entries = 256; 827254885Sdumbbell dev_priv->r600_max_hw_contexts = 8; 828254885Sdumbbell dev_priv->r600_max_gs_threads = 16; 829254885Sdumbbell dev_priv->r600_sx_max_export_size = 128; 830254885Sdumbbell dev_priv->r600_sx_max_export_pos_size = 16; 831254885Sdumbbell dev_priv->r600_sx_max_export_smx_size = 128; 832254885Sdumbbell dev_priv->r600_sq_num_cf_insts = 2; 833254885Sdumbbell break; 834254885Sdumbbell default: 835254885Sdumbbell break; 836254885Sdumbbell } 837254885Sdumbbell 838254885Sdumbbell /* Initialize HDP */ 839254885Sdumbbell j = 0; 840254885Sdumbbell for (i = 0; i < 32; i++) { 841254885Sdumbbell RADEON_WRITE((0x2c14 + j), 0x00000000); 842254885Sdumbbell RADEON_WRITE((0x2c18 + j), 0x00000000); 843254885Sdumbbell RADEON_WRITE((0x2c1c + j), 0x00000000); 844254885Sdumbbell RADEON_WRITE((0x2c20 + j), 0x00000000); 845254885Sdumbbell RADEON_WRITE((0x2c24 + j), 0x00000000); 846254885Sdumbbell j += 0x18; 847254885Sdumbbell } 848254885Sdumbbell 849254885Sdumbbell RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 850254885Sdumbbell 851254885Sdumbbell /* setup tiling, simd, pipe config */ 852254885Sdumbbell ramcfg = RADEON_READ(R600_RAMCFG); 853254885Sdumbbell 854254885Sdumbbell switch (dev_priv->r600_max_tile_pipes) { 855254885Sdumbbell case 1: 856254885Sdumbbell gb_tiling_config |= R600_PIPE_TILING(0); 857254885Sdumbbell break; 858254885Sdumbbell case 2: 859254885Sdumbbell gb_tiling_config |= R600_PIPE_TILING(1); 860254885Sdumbbell break; 861254885Sdumbbell case 4: 862254885Sdumbbell gb_tiling_config |= R600_PIPE_TILING(2); 863254885Sdumbbell break; 864254885Sdumbbell case 8: 865254885Sdumbbell gb_tiling_config |= R600_PIPE_TILING(3); 866254885Sdumbbell break; 867254885Sdumbbell default: 868254885Sdumbbell break; 869254885Sdumbbell } 870254885Sdumbbell 871254885Sdumbbell gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK); 872254885Sdumbbell 873254885Sdumbbell gb_tiling_config |= R600_GROUP_SIZE(0); 874254885Sdumbbell 875254885Sdumbbell if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) { 876254885Sdumbbell gb_tiling_config |= R600_ROW_TILING(3); 877254885Sdumbbell gb_tiling_config |= R600_SAMPLE_SPLIT(3); 878254885Sdumbbell } else { 879254885Sdumbbell gb_tiling_config |= 880254885Sdumbbell R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 881254885Sdumbbell gb_tiling_config |= 882254885Sdumbbell R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 883254885Sdumbbell } 884254885Sdumbbell 885254885Sdumbbell gb_tiling_config |= R600_BANK_SWAPS(1); 886254885Sdumbbell 887254885Sdumbbell cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000; 888254885Sdumbbell cc_rb_backend_disable |= 889254885Sdumbbell R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK); 890254885Sdumbbell 891254885Sdumbbell cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 892254885Sdumbbell cc_gc_shader_pipe_config |= 893254885Sdumbbell R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK); 894254885Sdumbbell cc_gc_shader_pipe_config |= 895254885Sdumbbell R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK); 896254885Sdumbbell 897254885Sdumbbell backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, 898254885Sdumbbell (R6XX_MAX_BACKENDS - 899254885Sdumbbell r600_count_pipe_bits((cc_rb_backend_disable & 900254885Sdumbbell R6XX_MAX_BACKENDS_MASK) >> 16)), 901254885Sdumbbell (cc_rb_backend_disable >> 16)); 902254885Sdumbbell gb_tiling_config |= R600_BACKEND_MAP(backend_map); 903254885Sdumbbell 904254885Sdumbbell RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 905254885Sdumbbell RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 906254885Sdumbbell RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 907254885Sdumbbell if (gb_tiling_config & 0xc0) { 908254885Sdumbbell dev_priv->r600_group_size = 512; 909254885Sdumbbell } else { 910254885Sdumbbell dev_priv->r600_group_size = 256; 911254885Sdumbbell } 912254885Sdumbbell dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); 913254885Sdumbbell if (gb_tiling_config & 0x30) { 914254885Sdumbbell dev_priv->r600_nbanks = 8; 915254885Sdumbbell } else { 916254885Sdumbbell dev_priv->r600_nbanks = 4; 917254885Sdumbbell } 918254885Sdumbbell 919254885Sdumbbell RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 920254885Sdumbbell RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 921254885Sdumbbell RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 922254885Sdumbbell 923254885Sdumbbell num_qd_pipes = 924254885Sdumbbell R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8); 925254885Sdumbbell RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 926254885Sdumbbell RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 927254885Sdumbbell 928254885Sdumbbell /* set HW defaults for 3D engine */ 929254885Sdumbbell RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 930254885Sdumbbell R600_ROQ_IB2_START(0x2b))); 931254885Sdumbbell 932254885Sdumbbell RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) | 933254885Sdumbbell R600_ROQ_END(0x40))); 934254885Sdumbbell 935254885Sdumbbell RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | 936254885Sdumbbell R600_SYNC_GRADIENT | 937254885Sdumbbell R600_SYNC_WALKER | 938254885Sdumbbell R600_SYNC_ALIGNER)); 939254885Sdumbbell 940254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) 941254885Sdumbbell RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021); 942254885Sdumbbell 943254885Sdumbbell sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1); 944254885Sdumbbell sx_debug_1 |= R600_SMX_EVENT_RELEASE; 945254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600)) 946254885Sdumbbell sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS; 947254885Sdumbbell RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1); 948254885Sdumbbell 949254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 950254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 951254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 952254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 953254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 954254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) 955254885Sdumbbell RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE); 956254885Sdumbbell else 957254885Sdumbbell RADEON_WRITE(R600_DB_DEBUG, 0); 958254885Sdumbbell 959254885Sdumbbell RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) | 960254885Sdumbbell R600_DEPTH_FLUSH(16) | 961254885Sdumbbell R600_DEPTH_PENDING_FREE(4) | 962254885Sdumbbell R600_DEPTH_CACHELINE_FREE(16))); 963254885Sdumbbell RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 964254885Sdumbbell RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0); 965254885Sdumbbell 966254885Sdumbbell RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 967254885Sdumbbell RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0)); 968254885Sdumbbell 969254885Sdumbbell sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES); 970254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 971254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 972254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 973254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { 974254885Sdumbbell sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) | 975254885Sdumbbell R600_FETCH_FIFO_HIWATER(0xa) | 976254885Sdumbbell R600_DONE_FIFO_HIWATER(0xe0) | 977254885Sdumbbell R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 978254885Sdumbbell } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 979254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { 980254885Sdumbbell sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff); 981254885Sdumbbell sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4); 982254885Sdumbbell } 983254885Sdumbbell RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 984254885Sdumbbell 985254885Sdumbbell /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 986254885Sdumbbell * should be adjusted as needed by the 2D/3D drivers. This just sets default values 987254885Sdumbbell */ 988254885Sdumbbell sq_config = RADEON_READ(R600_SQ_CONFIG); 989254885Sdumbbell sq_config &= ~(R600_PS_PRIO(3) | 990254885Sdumbbell R600_VS_PRIO(3) | 991254885Sdumbbell R600_GS_PRIO(3) | 992254885Sdumbbell R600_ES_PRIO(3)); 993254885Sdumbbell sq_config |= (R600_DX9_CONSTS | 994254885Sdumbbell R600_VC_ENABLE | 995254885Sdumbbell R600_PS_PRIO(0) | 996254885Sdumbbell R600_VS_PRIO(1) | 997254885Sdumbbell R600_GS_PRIO(2) | 998254885Sdumbbell R600_ES_PRIO(3)); 999254885Sdumbbell 1000254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) { 1001254885Sdumbbell sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) | 1002254885Sdumbbell R600_NUM_VS_GPRS(124) | 1003254885Sdumbbell R600_NUM_CLAUSE_TEMP_GPRS(4)); 1004254885Sdumbbell sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) | 1005254885Sdumbbell R600_NUM_ES_GPRS(0)); 1006254885Sdumbbell sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) | 1007254885Sdumbbell R600_NUM_VS_THREADS(48) | 1008254885Sdumbbell R600_NUM_GS_THREADS(4) | 1009254885Sdumbbell R600_NUM_ES_THREADS(4)); 1010254885Sdumbbell sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) | 1011254885Sdumbbell R600_NUM_VS_STACK_ENTRIES(128)); 1012254885Sdumbbell sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) | 1013254885Sdumbbell R600_NUM_ES_STACK_ENTRIES(0)); 1014254885Sdumbbell } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 1015254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 1016254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 1017254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { 1018254885Sdumbbell /* no vertex cache */ 1019254885Sdumbbell sq_config &= ~R600_VC_ENABLE; 1020254885Sdumbbell 1021254885Sdumbbell sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1022254885Sdumbbell R600_NUM_VS_GPRS(44) | 1023254885Sdumbbell R600_NUM_CLAUSE_TEMP_GPRS(2)); 1024254885Sdumbbell sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 1025254885Sdumbbell R600_NUM_ES_GPRS(17)); 1026254885Sdumbbell sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1027254885Sdumbbell R600_NUM_VS_THREADS(78) | 1028254885Sdumbbell R600_NUM_GS_THREADS(4) | 1029254885Sdumbbell R600_NUM_ES_THREADS(31)); 1030254885Sdumbbell sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 1031254885Sdumbbell R600_NUM_VS_STACK_ENTRIES(40)); 1032254885Sdumbbell sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 1033254885Sdumbbell R600_NUM_ES_STACK_ENTRIES(16)); 1034254885Sdumbbell } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 1035254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { 1036254885Sdumbbell sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1037254885Sdumbbell R600_NUM_VS_GPRS(44) | 1038254885Sdumbbell R600_NUM_CLAUSE_TEMP_GPRS(2)); 1039254885Sdumbbell sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) | 1040254885Sdumbbell R600_NUM_ES_GPRS(18)); 1041254885Sdumbbell sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1042254885Sdumbbell R600_NUM_VS_THREADS(78) | 1043254885Sdumbbell R600_NUM_GS_THREADS(4) | 1044254885Sdumbbell R600_NUM_ES_THREADS(31)); 1045254885Sdumbbell sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 1046254885Sdumbbell R600_NUM_VS_STACK_ENTRIES(40)); 1047254885Sdumbbell sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 1048254885Sdumbbell R600_NUM_ES_STACK_ENTRIES(16)); 1049254885Sdumbbell } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) { 1050254885Sdumbbell sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1051254885Sdumbbell R600_NUM_VS_GPRS(44) | 1052254885Sdumbbell R600_NUM_CLAUSE_TEMP_GPRS(2)); 1053254885Sdumbbell sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 1054254885Sdumbbell R600_NUM_ES_GPRS(17)); 1055254885Sdumbbell sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1056254885Sdumbbell R600_NUM_VS_THREADS(78) | 1057254885Sdumbbell R600_NUM_GS_THREADS(4) | 1058254885Sdumbbell R600_NUM_ES_THREADS(31)); 1059254885Sdumbbell sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) | 1060254885Sdumbbell R600_NUM_VS_STACK_ENTRIES(64)); 1061254885Sdumbbell sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) | 1062254885Sdumbbell R600_NUM_ES_STACK_ENTRIES(64)); 1063254885Sdumbbell } 1064254885Sdumbbell 1065254885Sdumbbell RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1066254885Sdumbbell RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 1067254885Sdumbbell RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 1068254885Sdumbbell RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1069254885Sdumbbell RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 1070254885Sdumbbell RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 1071254885Sdumbbell 1072254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 1073254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 1074254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 1075254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) 1076254885Sdumbbell RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY)); 1077254885Sdumbbell else 1078254885Sdumbbell RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC)); 1079254885Sdumbbell 1080254885Sdumbbell RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) | 1081254885Sdumbbell R600_S0_Y(0x4) | 1082254885Sdumbbell R600_S1_X(0x4) | 1083254885Sdumbbell R600_S1_Y(0xc))); 1084254885Sdumbbell RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) | 1085254885Sdumbbell R600_S0_Y(0xe) | 1086254885Sdumbbell R600_S1_X(0x2) | 1087254885Sdumbbell R600_S1_Y(0x2) | 1088254885Sdumbbell R600_S2_X(0xa) | 1089254885Sdumbbell R600_S2_Y(0x6) | 1090254885Sdumbbell R600_S3_X(0x6) | 1091254885Sdumbbell R600_S3_Y(0xa))); 1092254885Sdumbbell RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) | 1093254885Sdumbbell R600_S0_Y(0xb) | 1094254885Sdumbbell R600_S1_X(0x4) | 1095254885Sdumbbell R600_S1_Y(0xc) | 1096254885Sdumbbell R600_S2_X(0x1) | 1097254885Sdumbbell R600_S2_Y(0x6) | 1098254885Sdumbbell R600_S3_X(0xa) | 1099254885Sdumbbell R600_S3_Y(0xe))); 1100254885Sdumbbell RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) | 1101254885Sdumbbell R600_S4_Y(0x1) | 1102254885Sdumbbell R600_S5_X(0x0) | 1103254885Sdumbbell R600_S5_Y(0x0) | 1104254885Sdumbbell R600_S6_X(0xb) | 1105254885Sdumbbell R600_S6_Y(0x4) | 1106254885Sdumbbell R600_S7_X(0x7) | 1107254885Sdumbbell R600_S7_Y(0x8))); 1108254885Sdumbbell 1109254885Sdumbbell 1110254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1111254885Sdumbbell case CHIP_R600: 1112254885Sdumbbell case CHIP_RV630: 1113254885Sdumbbell case CHIP_RV635: 1114254885Sdumbbell gs_prim_buffer_depth = 0; 1115254885Sdumbbell break; 1116254885Sdumbbell case CHIP_RV610: 1117254885Sdumbbell case CHIP_RS780: 1118254885Sdumbbell case CHIP_RS880: 1119254885Sdumbbell case CHIP_RV620: 1120254885Sdumbbell gs_prim_buffer_depth = 32; 1121254885Sdumbbell break; 1122254885Sdumbbell case CHIP_RV670: 1123254885Sdumbbell gs_prim_buffer_depth = 128; 1124254885Sdumbbell break; 1125254885Sdumbbell default: 1126254885Sdumbbell break; 1127254885Sdumbbell } 1128254885Sdumbbell 1129254885Sdumbbell num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1130254885Sdumbbell vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1131254885Sdumbbell /* Max value for this is 256 */ 1132254885Sdumbbell if (vgt_gs_per_es > 256) 1133254885Sdumbbell vgt_gs_per_es = 256; 1134254885Sdumbbell 1135254885Sdumbbell RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1136254885Sdumbbell RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1137254885Sdumbbell RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1138254885Sdumbbell RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1139254885Sdumbbell 1140254885Sdumbbell /* more default values. 2D/3D driver should adjust as needed */ 1141254885Sdumbbell RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1142254885Sdumbbell RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1143254885Sdumbbell RADEON_WRITE(R600_SX_MISC, 0); 1144254885Sdumbbell RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1145254885Sdumbbell RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1146254885Sdumbbell RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1147254885Sdumbbell RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1148254885Sdumbbell RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1149254885Sdumbbell RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1150254885Sdumbbell 1151254885Sdumbbell /* clear render buffer base addresses */ 1152254885Sdumbbell RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1153254885Sdumbbell RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1154254885Sdumbbell RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1155254885Sdumbbell RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1156254885Sdumbbell RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1157254885Sdumbbell RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1158254885Sdumbbell RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1159254885Sdumbbell RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1160254885Sdumbbell 1161254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1162254885Sdumbbell case CHIP_RV610: 1163254885Sdumbbell case CHIP_RS780: 1164254885Sdumbbell case CHIP_RS880: 1165254885Sdumbbell case CHIP_RV620: 1166254885Sdumbbell tc_cntl = R600_TC_L2_SIZE(8); 1167254885Sdumbbell break; 1168254885Sdumbbell case CHIP_RV630: 1169254885Sdumbbell case CHIP_RV635: 1170254885Sdumbbell tc_cntl = R600_TC_L2_SIZE(4); 1171254885Sdumbbell break; 1172254885Sdumbbell case CHIP_R600: 1173254885Sdumbbell tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT; 1174254885Sdumbbell break; 1175254885Sdumbbell default: 1176254885Sdumbbell tc_cntl = R600_TC_L2_SIZE(0); 1177254885Sdumbbell break; 1178254885Sdumbbell } 1179254885Sdumbbell 1180254885Sdumbbell RADEON_WRITE(R600_TC_CNTL, tc_cntl); 1181254885Sdumbbell 1182254885Sdumbbell hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1183254885Sdumbbell RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1184254885Sdumbbell 1185254885Sdumbbell arb_pop = RADEON_READ(R600_ARB_POP); 1186254885Sdumbbell arb_pop |= R600_ENABLE_TC128; 1187254885Sdumbbell RADEON_WRITE(R600_ARB_POP, arb_pop); 1188254885Sdumbbell 1189254885Sdumbbell RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1190254885Sdumbbell RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1191254885Sdumbbell R600_NUM_CLIP_SEQ(3))); 1192254885Sdumbbell RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095)); 1193254885Sdumbbell 1194254885Sdumbbell} 1195254885Sdumbbell 1196254885Sdumbbellstatic u32 r700_get_tile_pipe_to_backend_map(drm_radeon_private_t *dev_priv, 1197254885Sdumbbell u32 num_tile_pipes, 1198254885Sdumbbell u32 num_backends, 1199254885Sdumbbell u32 backend_disable_mask) 1200254885Sdumbbell{ 1201254885Sdumbbell u32 backend_map = 0; 1202254885Sdumbbell u32 enabled_backends_mask; 1203254885Sdumbbell u32 enabled_backends_count; 1204254885Sdumbbell u32 cur_pipe; 1205254885Sdumbbell u32 swizzle_pipe[R7XX_MAX_PIPES]; 1206254885Sdumbbell u32 cur_backend; 1207254885Sdumbbell u32 i; 1208254885Sdumbbell bool force_no_swizzle; 1209254885Sdumbbell 1210254885Sdumbbell if (num_tile_pipes > R7XX_MAX_PIPES) 1211254885Sdumbbell num_tile_pipes = R7XX_MAX_PIPES; 1212254885Sdumbbell if (num_tile_pipes < 1) 1213254885Sdumbbell num_tile_pipes = 1; 1214254885Sdumbbell if (num_backends > R7XX_MAX_BACKENDS) 1215254885Sdumbbell num_backends = R7XX_MAX_BACKENDS; 1216254885Sdumbbell if (num_backends < 1) 1217254885Sdumbbell num_backends = 1; 1218254885Sdumbbell 1219254885Sdumbbell enabled_backends_mask = 0; 1220254885Sdumbbell enabled_backends_count = 0; 1221254885Sdumbbell for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { 1222254885Sdumbbell if (((backend_disable_mask >> i) & 1) == 0) { 1223254885Sdumbbell enabled_backends_mask |= (1 << i); 1224254885Sdumbbell ++enabled_backends_count; 1225254885Sdumbbell } 1226254885Sdumbbell if (enabled_backends_count == num_backends) 1227254885Sdumbbell break; 1228254885Sdumbbell } 1229254885Sdumbbell 1230254885Sdumbbell if (enabled_backends_count == 0) { 1231254885Sdumbbell enabled_backends_mask = 1; 1232254885Sdumbbell enabled_backends_count = 1; 1233254885Sdumbbell } 1234254885Sdumbbell 1235254885Sdumbbell if (enabled_backends_count != num_backends) 1236254885Sdumbbell num_backends = enabled_backends_count; 1237254885Sdumbbell 1238254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1239254885Sdumbbell case CHIP_RV770: 1240254885Sdumbbell case CHIP_RV730: 1241254885Sdumbbell force_no_swizzle = false; 1242254885Sdumbbell break; 1243254885Sdumbbell case CHIP_RV710: 1244254885Sdumbbell case CHIP_RV740: 1245254885Sdumbbell default: 1246254885Sdumbbell force_no_swizzle = true; 1247254885Sdumbbell break; 1248254885Sdumbbell } 1249254885Sdumbbell 1250254885Sdumbbell memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); 1251254885Sdumbbell switch (num_tile_pipes) { 1252254885Sdumbbell case 1: 1253254885Sdumbbell swizzle_pipe[0] = 0; 1254254885Sdumbbell break; 1255254885Sdumbbell case 2: 1256254885Sdumbbell swizzle_pipe[0] = 0; 1257254885Sdumbbell swizzle_pipe[1] = 1; 1258254885Sdumbbell break; 1259254885Sdumbbell case 3: 1260254885Sdumbbell if (force_no_swizzle) { 1261254885Sdumbbell swizzle_pipe[0] = 0; 1262254885Sdumbbell swizzle_pipe[1] = 1; 1263254885Sdumbbell swizzle_pipe[2] = 2; 1264254885Sdumbbell } else { 1265254885Sdumbbell swizzle_pipe[0] = 0; 1266254885Sdumbbell swizzle_pipe[1] = 2; 1267254885Sdumbbell swizzle_pipe[2] = 1; 1268254885Sdumbbell } 1269254885Sdumbbell break; 1270254885Sdumbbell case 4: 1271254885Sdumbbell if (force_no_swizzle) { 1272254885Sdumbbell swizzle_pipe[0] = 0; 1273254885Sdumbbell swizzle_pipe[1] = 1; 1274254885Sdumbbell swizzle_pipe[2] = 2; 1275254885Sdumbbell swizzle_pipe[3] = 3; 1276254885Sdumbbell } else { 1277254885Sdumbbell swizzle_pipe[0] = 0; 1278254885Sdumbbell swizzle_pipe[1] = 2; 1279254885Sdumbbell swizzle_pipe[2] = 3; 1280254885Sdumbbell swizzle_pipe[3] = 1; 1281254885Sdumbbell } 1282254885Sdumbbell break; 1283254885Sdumbbell case 5: 1284254885Sdumbbell if (force_no_swizzle) { 1285254885Sdumbbell swizzle_pipe[0] = 0; 1286254885Sdumbbell swizzle_pipe[1] = 1; 1287254885Sdumbbell swizzle_pipe[2] = 2; 1288254885Sdumbbell swizzle_pipe[3] = 3; 1289254885Sdumbbell swizzle_pipe[4] = 4; 1290254885Sdumbbell } else { 1291254885Sdumbbell swizzle_pipe[0] = 0; 1292254885Sdumbbell swizzle_pipe[1] = 2; 1293254885Sdumbbell swizzle_pipe[2] = 4; 1294254885Sdumbbell swizzle_pipe[3] = 1; 1295254885Sdumbbell swizzle_pipe[4] = 3; 1296254885Sdumbbell } 1297254885Sdumbbell break; 1298254885Sdumbbell case 6: 1299254885Sdumbbell if (force_no_swizzle) { 1300254885Sdumbbell swizzle_pipe[0] = 0; 1301254885Sdumbbell swizzle_pipe[1] = 1; 1302254885Sdumbbell swizzle_pipe[2] = 2; 1303254885Sdumbbell swizzle_pipe[3] = 3; 1304254885Sdumbbell swizzle_pipe[4] = 4; 1305254885Sdumbbell swizzle_pipe[5] = 5; 1306254885Sdumbbell } else { 1307254885Sdumbbell swizzle_pipe[0] = 0; 1308254885Sdumbbell swizzle_pipe[1] = 2; 1309254885Sdumbbell swizzle_pipe[2] = 4; 1310254885Sdumbbell swizzle_pipe[3] = 5; 1311254885Sdumbbell swizzle_pipe[4] = 3; 1312254885Sdumbbell swizzle_pipe[5] = 1; 1313254885Sdumbbell } 1314254885Sdumbbell break; 1315254885Sdumbbell case 7: 1316254885Sdumbbell if (force_no_swizzle) { 1317254885Sdumbbell swizzle_pipe[0] = 0; 1318254885Sdumbbell swizzle_pipe[1] = 1; 1319254885Sdumbbell swizzle_pipe[2] = 2; 1320254885Sdumbbell swizzle_pipe[3] = 3; 1321254885Sdumbbell swizzle_pipe[4] = 4; 1322254885Sdumbbell swizzle_pipe[5] = 5; 1323254885Sdumbbell swizzle_pipe[6] = 6; 1324254885Sdumbbell } else { 1325254885Sdumbbell swizzle_pipe[0] = 0; 1326254885Sdumbbell swizzle_pipe[1] = 2; 1327254885Sdumbbell swizzle_pipe[2] = 4; 1328254885Sdumbbell swizzle_pipe[3] = 6; 1329254885Sdumbbell swizzle_pipe[4] = 3; 1330254885Sdumbbell swizzle_pipe[5] = 1; 1331254885Sdumbbell swizzle_pipe[6] = 5; 1332254885Sdumbbell } 1333254885Sdumbbell break; 1334254885Sdumbbell case 8: 1335254885Sdumbbell if (force_no_swizzle) { 1336254885Sdumbbell swizzle_pipe[0] = 0; 1337254885Sdumbbell swizzle_pipe[1] = 1; 1338254885Sdumbbell swizzle_pipe[2] = 2; 1339254885Sdumbbell swizzle_pipe[3] = 3; 1340254885Sdumbbell swizzle_pipe[4] = 4; 1341254885Sdumbbell swizzle_pipe[5] = 5; 1342254885Sdumbbell swizzle_pipe[6] = 6; 1343254885Sdumbbell swizzle_pipe[7] = 7; 1344254885Sdumbbell } else { 1345254885Sdumbbell swizzle_pipe[0] = 0; 1346254885Sdumbbell swizzle_pipe[1] = 2; 1347254885Sdumbbell swizzle_pipe[2] = 4; 1348254885Sdumbbell swizzle_pipe[3] = 6; 1349254885Sdumbbell swizzle_pipe[4] = 3; 1350254885Sdumbbell swizzle_pipe[5] = 1; 1351254885Sdumbbell swizzle_pipe[6] = 7; 1352254885Sdumbbell swizzle_pipe[7] = 5; 1353254885Sdumbbell } 1354254885Sdumbbell break; 1355254885Sdumbbell } 1356254885Sdumbbell 1357254885Sdumbbell cur_backend = 0; 1358254885Sdumbbell for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 1359254885Sdumbbell while (((1 << cur_backend) & enabled_backends_mask) == 0) 1360254885Sdumbbell cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1361254885Sdumbbell 1362254885Sdumbbell backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 1363254885Sdumbbell 1364254885Sdumbbell cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1365254885Sdumbbell } 1366254885Sdumbbell 1367254885Sdumbbell return backend_map; 1368254885Sdumbbell} 1369254885Sdumbbell 1370254885Sdumbbellstatic void r700_gfx_init(struct drm_device *dev, 1371254885Sdumbbell drm_radeon_private_t *dev_priv) 1372254885Sdumbbell{ 1373254885Sdumbbell int i, j, num_qd_pipes; 1374254885Sdumbbell u32 ta_aux_cntl; 1375254885Sdumbbell u32 sx_debug_1; 1376254885Sdumbbell u32 smx_dc_ctl0; 1377254885Sdumbbell u32 db_debug3; 1378254885Sdumbbell u32 num_gs_verts_per_thread; 1379254885Sdumbbell u32 vgt_gs_per_es; 1380254885Sdumbbell u32 gs_prim_buffer_depth = 0; 1381254885Sdumbbell u32 sq_ms_fifo_sizes; 1382254885Sdumbbell u32 sq_config; 1383254885Sdumbbell u32 sq_thread_resource_mgmt; 1384254885Sdumbbell u32 hdp_host_path_cntl; 1385254885Sdumbbell u32 sq_dyn_gpr_size_simd_ab_0; 1386254885Sdumbbell u32 backend_map; 1387254885Sdumbbell u32 gb_tiling_config = 0; 1388254885Sdumbbell u32 cc_rb_backend_disable; 1389254885Sdumbbell u32 cc_gc_shader_pipe_config; 1390254885Sdumbbell u32 mc_arb_ramcfg; 1391254885Sdumbbell u32 db_debug4; 1392254885Sdumbbell 1393254885Sdumbbell /* setup chip specs */ 1394254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1395254885Sdumbbell case CHIP_RV770: 1396254885Sdumbbell dev_priv->r600_max_pipes = 4; 1397254885Sdumbbell dev_priv->r600_max_tile_pipes = 8; 1398254885Sdumbbell dev_priv->r600_max_simds = 10; 1399254885Sdumbbell dev_priv->r600_max_backends = 4; 1400254885Sdumbbell dev_priv->r600_max_gprs = 256; 1401254885Sdumbbell dev_priv->r600_max_threads = 248; 1402254885Sdumbbell dev_priv->r600_max_stack_entries = 512; 1403254885Sdumbbell dev_priv->r600_max_hw_contexts = 8; 1404254885Sdumbbell dev_priv->r600_max_gs_threads = 16 * 2; 1405254885Sdumbbell dev_priv->r600_sx_max_export_size = 128; 1406254885Sdumbbell dev_priv->r600_sx_max_export_pos_size = 16; 1407254885Sdumbbell dev_priv->r600_sx_max_export_smx_size = 112; 1408254885Sdumbbell dev_priv->r600_sq_num_cf_insts = 2; 1409254885Sdumbbell 1410254885Sdumbbell dev_priv->r700_sx_num_of_sets = 7; 1411254885Sdumbbell dev_priv->r700_sc_prim_fifo_size = 0xF9; 1412254885Sdumbbell dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1413254885Sdumbbell dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1414254885Sdumbbell break; 1415254885Sdumbbell case CHIP_RV730: 1416254885Sdumbbell dev_priv->r600_max_pipes = 2; 1417254885Sdumbbell dev_priv->r600_max_tile_pipes = 4; 1418254885Sdumbbell dev_priv->r600_max_simds = 8; 1419254885Sdumbbell dev_priv->r600_max_backends = 2; 1420254885Sdumbbell dev_priv->r600_max_gprs = 128; 1421254885Sdumbbell dev_priv->r600_max_threads = 248; 1422254885Sdumbbell dev_priv->r600_max_stack_entries = 256; 1423254885Sdumbbell dev_priv->r600_max_hw_contexts = 8; 1424254885Sdumbbell dev_priv->r600_max_gs_threads = 16 * 2; 1425254885Sdumbbell dev_priv->r600_sx_max_export_size = 256; 1426254885Sdumbbell dev_priv->r600_sx_max_export_pos_size = 32; 1427254885Sdumbbell dev_priv->r600_sx_max_export_smx_size = 224; 1428254885Sdumbbell dev_priv->r600_sq_num_cf_insts = 2; 1429254885Sdumbbell 1430254885Sdumbbell dev_priv->r700_sx_num_of_sets = 7; 1431254885Sdumbbell dev_priv->r700_sc_prim_fifo_size = 0xf9; 1432254885Sdumbbell dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1433254885Sdumbbell dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1434254885Sdumbbell if (dev_priv->r600_sx_max_export_pos_size > 16) { 1435254885Sdumbbell dev_priv->r600_sx_max_export_pos_size -= 16; 1436254885Sdumbbell dev_priv->r600_sx_max_export_smx_size += 16; 1437254885Sdumbbell } 1438254885Sdumbbell break; 1439254885Sdumbbell case CHIP_RV710: 1440254885Sdumbbell dev_priv->r600_max_pipes = 2; 1441254885Sdumbbell dev_priv->r600_max_tile_pipes = 2; 1442254885Sdumbbell dev_priv->r600_max_simds = 2; 1443254885Sdumbbell dev_priv->r600_max_backends = 1; 1444254885Sdumbbell dev_priv->r600_max_gprs = 256; 1445254885Sdumbbell dev_priv->r600_max_threads = 192; 1446254885Sdumbbell dev_priv->r600_max_stack_entries = 256; 1447254885Sdumbbell dev_priv->r600_max_hw_contexts = 4; 1448254885Sdumbbell dev_priv->r600_max_gs_threads = 8 * 2; 1449254885Sdumbbell dev_priv->r600_sx_max_export_size = 128; 1450254885Sdumbbell dev_priv->r600_sx_max_export_pos_size = 16; 1451254885Sdumbbell dev_priv->r600_sx_max_export_smx_size = 112; 1452254885Sdumbbell dev_priv->r600_sq_num_cf_insts = 1; 1453254885Sdumbbell 1454254885Sdumbbell dev_priv->r700_sx_num_of_sets = 7; 1455254885Sdumbbell dev_priv->r700_sc_prim_fifo_size = 0x40; 1456254885Sdumbbell dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1457254885Sdumbbell dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1458254885Sdumbbell break; 1459254885Sdumbbell case CHIP_RV740: 1460254885Sdumbbell dev_priv->r600_max_pipes = 4; 1461254885Sdumbbell dev_priv->r600_max_tile_pipes = 4; 1462254885Sdumbbell dev_priv->r600_max_simds = 8; 1463254885Sdumbbell dev_priv->r600_max_backends = 4; 1464254885Sdumbbell dev_priv->r600_max_gprs = 256; 1465254885Sdumbbell dev_priv->r600_max_threads = 248; 1466254885Sdumbbell dev_priv->r600_max_stack_entries = 512; 1467254885Sdumbbell dev_priv->r600_max_hw_contexts = 8; 1468254885Sdumbbell dev_priv->r600_max_gs_threads = 16 * 2; 1469254885Sdumbbell dev_priv->r600_sx_max_export_size = 256; 1470254885Sdumbbell dev_priv->r600_sx_max_export_pos_size = 32; 1471254885Sdumbbell dev_priv->r600_sx_max_export_smx_size = 224; 1472254885Sdumbbell dev_priv->r600_sq_num_cf_insts = 2; 1473254885Sdumbbell 1474254885Sdumbbell dev_priv->r700_sx_num_of_sets = 7; 1475254885Sdumbbell dev_priv->r700_sc_prim_fifo_size = 0x100; 1476254885Sdumbbell dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1477254885Sdumbbell dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1478254885Sdumbbell 1479254885Sdumbbell if (dev_priv->r600_sx_max_export_pos_size > 16) { 1480254885Sdumbbell dev_priv->r600_sx_max_export_pos_size -= 16; 1481254885Sdumbbell dev_priv->r600_sx_max_export_smx_size += 16; 1482254885Sdumbbell } 1483254885Sdumbbell break; 1484254885Sdumbbell default: 1485254885Sdumbbell break; 1486254885Sdumbbell } 1487254885Sdumbbell 1488254885Sdumbbell /* Initialize HDP */ 1489254885Sdumbbell j = 0; 1490254885Sdumbbell for (i = 0; i < 32; i++) { 1491254885Sdumbbell RADEON_WRITE((0x2c14 + j), 0x00000000); 1492254885Sdumbbell RADEON_WRITE((0x2c18 + j), 0x00000000); 1493254885Sdumbbell RADEON_WRITE((0x2c1c + j), 0x00000000); 1494254885Sdumbbell RADEON_WRITE((0x2c20 + j), 0x00000000); 1495254885Sdumbbell RADEON_WRITE((0x2c24 + j), 0x00000000); 1496254885Sdumbbell j += 0x18; 1497254885Sdumbbell } 1498254885Sdumbbell 1499254885Sdumbbell RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 1500254885Sdumbbell 1501254885Sdumbbell /* setup tiling, simd, pipe config */ 1502254885Sdumbbell mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG); 1503254885Sdumbbell 1504254885Sdumbbell switch (dev_priv->r600_max_tile_pipes) { 1505254885Sdumbbell case 1: 1506254885Sdumbbell gb_tiling_config |= R600_PIPE_TILING(0); 1507254885Sdumbbell break; 1508254885Sdumbbell case 2: 1509254885Sdumbbell gb_tiling_config |= R600_PIPE_TILING(1); 1510254885Sdumbbell break; 1511254885Sdumbbell case 4: 1512254885Sdumbbell gb_tiling_config |= R600_PIPE_TILING(2); 1513254885Sdumbbell break; 1514254885Sdumbbell case 8: 1515254885Sdumbbell gb_tiling_config |= R600_PIPE_TILING(3); 1516254885Sdumbbell break; 1517254885Sdumbbell default: 1518254885Sdumbbell break; 1519254885Sdumbbell } 1520254885Sdumbbell 1521254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) 1522254885Sdumbbell gb_tiling_config |= R600_BANK_TILING(1); 1523254885Sdumbbell else 1524254885Sdumbbell gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK); 1525254885Sdumbbell 1526254885Sdumbbell gb_tiling_config |= R600_GROUP_SIZE(0); 1527254885Sdumbbell 1528254885Sdumbbell if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) { 1529254885Sdumbbell gb_tiling_config |= R600_ROW_TILING(3); 1530254885Sdumbbell gb_tiling_config |= R600_SAMPLE_SPLIT(3); 1531254885Sdumbbell } else { 1532254885Sdumbbell gb_tiling_config |= 1533254885Sdumbbell R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1534254885Sdumbbell gb_tiling_config |= 1535254885Sdumbbell R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1536254885Sdumbbell } 1537254885Sdumbbell 1538254885Sdumbbell gb_tiling_config |= R600_BANK_SWAPS(1); 1539254885Sdumbbell 1540254885Sdumbbell cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1541254885Sdumbbell cc_rb_backend_disable |= 1542254885Sdumbbell R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK); 1543254885Sdumbbell 1544254885Sdumbbell cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 1545254885Sdumbbell cc_gc_shader_pipe_config |= 1546254885Sdumbbell R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK); 1547254885Sdumbbell cc_gc_shader_pipe_config |= 1548254885Sdumbbell R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK); 1549254885Sdumbbell 1550254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740) 1551254885Sdumbbell backend_map = 0x28; 1552254885Sdumbbell else 1553254885Sdumbbell backend_map = r700_get_tile_pipe_to_backend_map(dev_priv, 1554254885Sdumbbell dev_priv->r600_max_tile_pipes, 1555254885Sdumbbell (R7XX_MAX_BACKENDS - 1556254885Sdumbbell r600_count_pipe_bits((cc_rb_backend_disable & 1557254885Sdumbbell R7XX_MAX_BACKENDS_MASK) >> 16)), 1558254885Sdumbbell (cc_rb_backend_disable >> 16)); 1559254885Sdumbbell gb_tiling_config |= R600_BACKEND_MAP(backend_map); 1560254885Sdumbbell 1561254885Sdumbbell RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 1562254885Sdumbbell RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1563254885Sdumbbell RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1564254885Sdumbbell if (gb_tiling_config & 0xc0) { 1565254885Sdumbbell dev_priv->r600_group_size = 512; 1566254885Sdumbbell } else { 1567254885Sdumbbell dev_priv->r600_group_size = 256; 1568254885Sdumbbell } 1569254885Sdumbbell dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); 1570254885Sdumbbell if (gb_tiling_config & 0x30) { 1571254885Sdumbbell dev_priv->r600_nbanks = 8; 1572254885Sdumbbell } else { 1573254885Sdumbbell dev_priv->r600_nbanks = 4; 1574254885Sdumbbell } 1575254885Sdumbbell 1576254885Sdumbbell RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1577254885Sdumbbell RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1578254885Sdumbbell RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1579254885Sdumbbell 1580254885Sdumbbell RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1581254885Sdumbbell RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0); 1582254885Sdumbbell RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0); 1583254885Sdumbbell RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0); 1584254885Sdumbbell RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0); 1585254885Sdumbbell 1586254885Sdumbbell num_qd_pipes = 1587254885Sdumbbell R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8); 1588254885Sdumbbell RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 1589254885Sdumbbell RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 1590254885Sdumbbell 1591254885Sdumbbell /* set HW defaults for 3D engine */ 1592254885Sdumbbell RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 1593254885Sdumbbell R600_ROQ_IB2_START(0x2b))); 1594254885Sdumbbell 1595254885Sdumbbell RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30)); 1596254885Sdumbbell 1597254885Sdumbbell ta_aux_cntl = RADEON_READ(R600_TA_CNTL_AUX); 1598254885Sdumbbell RADEON_WRITE(R600_TA_CNTL_AUX, ta_aux_cntl | R600_DISABLE_CUBE_ANISO); 1599254885Sdumbbell 1600254885Sdumbbell sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1); 1601254885Sdumbbell sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS; 1602254885Sdumbbell RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1); 1603254885Sdumbbell 1604254885Sdumbbell smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0); 1605254885Sdumbbell smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff); 1606254885Sdumbbell smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1); 1607254885Sdumbbell RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0); 1608254885Sdumbbell 1609254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV740) 1610254885Sdumbbell RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) | 1611254885Sdumbbell R700_GS_FLUSH_CTL(4) | 1612254885Sdumbbell R700_ACK_FLUSH_CTL(3) | 1613254885Sdumbbell R700_SYNC_FLUSH_CTL)); 1614254885Sdumbbell 1615254885Sdumbbell db_debug3 = RADEON_READ(R700_DB_DEBUG3); 1616254885Sdumbbell db_debug3 &= ~R700_DB_CLK_OFF_DELAY(0x1f); 1617254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1618254885Sdumbbell case CHIP_RV770: 1619254885Sdumbbell case CHIP_RV740: 1620254885Sdumbbell db_debug3 |= R700_DB_CLK_OFF_DELAY(0x1f); 1621254885Sdumbbell break; 1622254885Sdumbbell case CHIP_RV710: 1623254885Sdumbbell case CHIP_RV730: 1624254885Sdumbbell default: 1625254885Sdumbbell db_debug3 |= R700_DB_CLK_OFF_DELAY(2); 1626254885Sdumbbell break; 1627254885Sdumbbell } 1628254885Sdumbbell RADEON_WRITE(R700_DB_DEBUG3, db_debug3); 1629254885Sdumbbell 1630254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV770) { 1631254885Sdumbbell db_debug4 = RADEON_READ(RV700_DB_DEBUG4); 1632254885Sdumbbell db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER; 1633254885Sdumbbell RADEON_WRITE(RV700_DB_DEBUG4, db_debug4); 1634254885Sdumbbell } 1635254885Sdumbbell 1636254885Sdumbbell RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) | 1637254885Sdumbbell R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) | 1638254885Sdumbbell R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1))); 1639254885Sdumbbell 1640254885Sdumbbell RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) | 1641254885Sdumbbell R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) | 1642254885Sdumbbell R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize))); 1643254885Sdumbbell 1644254885Sdumbbell RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1645254885Sdumbbell 1646254885Sdumbbell RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1); 1647254885Sdumbbell 1648254885Sdumbbell RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 1649254885Sdumbbell 1650254885Sdumbbell RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4)); 1651254885Sdumbbell 1652254885Sdumbbell RADEON_WRITE(R600_CP_PERFMON_CNTL, 0); 1653254885Sdumbbell 1654254885Sdumbbell sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) | 1655254885Sdumbbell R600_DONE_FIFO_HIWATER(0xe0) | 1656254885Sdumbbell R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 1657254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1658254885Sdumbbell case CHIP_RV770: 1659254885Sdumbbell case CHIP_RV730: 1660254885Sdumbbell case CHIP_RV710: 1661254885Sdumbbell sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1); 1662254885Sdumbbell break; 1663254885Sdumbbell case CHIP_RV740: 1664254885Sdumbbell default: 1665254885Sdumbbell sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4); 1666254885Sdumbbell break; 1667254885Sdumbbell } 1668254885Sdumbbell RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 1669254885Sdumbbell 1670254885Sdumbbell /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1671254885Sdumbbell * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1672254885Sdumbbell */ 1673254885Sdumbbell sq_config = RADEON_READ(R600_SQ_CONFIG); 1674254885Sdumbbell sq_config &= ~(R600_PS_PRIO(3) | 1675254885Sdumbbell R600_VS_PRIO(3) | 1676254885Sdumbbell R600_GS_PRIO(3) | 1677254885Sdumbbell R600_ES_PRIO(3)); 1678254885Sdumbbell sq_config |= (R600_DX9_CONSTS | 1679254885Sdumbbell R600_VC_ENABLE | 1680254885Sdumbbell R600_EXPORT_SRC_C | 1681254885Sdumbbell R600_PS_PRIO(0) | 1682254885Sdumbbell R600_VS_PRIO(1) | 1683254885Sdumbbell R600_GS_PRIO(2) | 1684254885Sdumbbell R600_ES_PRIO(3)); 1685254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1686254885Sdumbbell /* no vertex cache */ 1687254885Sdumbbell sq_config &= ~R600_VC_ENABLE; 1688254885Sdumbbell 1689254885Sdumbbell RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1690254885Sdumbbell 1691254885Sdumbbell RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1692254885Sdumbbell R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1693254885Sdumbbell R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2))); 1694254885Sdumbbell 1695254885Sdumbbell RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) | 1696254885Sdumbbell R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64))); 1697254885Sdumbbell 1698254885Sdumbbell sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) | 1699254885Sdumbbell R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) | 1700254885Sdumbbell R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8)); 1701254885Sdumbbell if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads) 1702254885Sdumbbell sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads); 1703254885Sdumbbell else 1704254885Sdumbbell sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8); 1705254885Sdumbbell RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1706254885Sdumbbell 1707254885Sdumbbell RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1708254885Sdumbbell R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1709254885Sdumbbell 1710254885Sdumbbell RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1711254885Sdumbbell R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1712254885Sdumbbell 1713254885Sdumbbell sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) | 1714254885Sdumbbell R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) | 1715254885Sdumbbell R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) | 1716254885Sdumbbell R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64)); 1717254885Sdumbbell 1718254885Sdumbbell RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 1719254885Sdumbbell RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 1720254885Sdumbbell RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 1721254885Sdumbbell RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 1722254885Sdumbbell RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 1723254885Sdumbbell RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 1724254885Sdumbbell RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 1725254885Sdumbbell RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 1726254885Sdumbbell 1727254885Sdumbbell RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) | 1728254885Sdumbbell R700_FORCE_EOV_MAX_REZ_CNT(255))); 1729254885Sdumbbell 1730254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1731254885Sdumbbell RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) | 1732254885Sdumbbell R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1733254885Sdumbbell else 1734254885Sdumbbell RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) | 1735254885Sdumbbell R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1736254885Sdumbbell 1737254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1738254885Sdumbbell case CHIP_RV770: 1739254885Sdumbbell case CHIP_RV730: 1740254885Sdumbbell case CHIP_RV740: 1741254885Sdumbbell gs_prim_buffer_depth = 384; 1742254885Sdumbbell break; 1743254885Sdumbbell case CHIP_RV710: 1744254885Sdumbbell gs_prim_buffer_depth = 128; 1745254885Sdumbbell break; 1746254885Sdumbbell default: 1747254885Sdumbbell break; 1748254885Sdumbbell } 1749254885Sdumbbell 1750254885Sdumbbell num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1751254885Sdumbbell vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1752254885Sdumbbell /* Max value for this is 256 */ 1753254885Sdumbbell if (vgt_gs_per_es > 256) 1754254885Sdumbbell vgt_gs_per_es = 256; 1755254885Sdumbbell 1756254885Sdumbbell RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1757254885Sdumbbell RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1758254885Sdumbbell RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1759254885Sdumbbell 1760254885Sdumbbell /* more default values. 2D/3D driver should adjust as needed */ 1761254885Sdumbbell RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1762254885Sdumbbell RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1763254885Sdumbbell RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1764254885Sdumbbell RADEON_WRITE(R600_SX_MISC, 0); 1765254885Sdumbbell RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1766254885Sdumbbell RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa); 1767254885Sdumbbell RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1768254885Sdumbbell RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff); 1769254885Sdumbbell RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1770254885Sdumbbell RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1771254885Sdumbbell RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1772254885Sdumbbell RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1773254885Sdumbbell 1774254885Sdumbbell /* clear render buffer base addresses */ 1775254885Sdumbbell RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1776254885Sdumbbell RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1777254885Sdumbbell RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1778254885Sdumbbell RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1779254885Sdumbbell RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1780254885Sdumbbell RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1781254885Sdumbbell RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1782254885Sdumbbell RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1783254885Sdumbbell 1784254885Sdumbbell RADEON_WRITE(R700_TCP_CNTL, 0); 1785254885Sdumbbell 1786254885Sdumbbell hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1787254885Sdumbbell RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1788254885Sdumbbell 1789254885Sdumbbell RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1790254885Sdumbbell 1791254885Sdumbbell RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1792254885Sdumbbell R600_NUM_CLIP_SEQ(3))); 1793254885Sdumbbell 1794254885Sdumbbell} 1795254885Sdumbbell 1796254885Sdumbbellstatic void r600_cp_init_ring_buffer(struct drm_device *dev, 1797254885Sdumbbell drm_radeon_private_t *dev_priv, 1798254885Sdumbbell struct drm_file *file_priv) 1799254885Sdumbbell{ 1800254885Sdumbbell struct drm_radeon_master_private *master_priv; 1801254885Sdumbbell u32 ring_start; 1802254885Sdumbbell u64 rptr_addr; 1803254885Sdumbbell 1804254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 1805254885Sdumbbell r700_gfx_init(dev, dev_priv); 1806254885Sdumbbell else 1807254885Sdumbbell r600_gfx_init(dev, dev_priv); 1808254885Sdumbbell 1809254885Sdumbbell RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 1810254885Sdumbbell RADEON_READ(R600_GRBM_SOFT_RESET); 1811282199Sdumbbell mdelay(15); 1812254885Sdumbbell RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 1813254885Sdumbbell 1814254885Sdumbbell 1815254885Sdumbbell /* Set ring buffer size */ 1816254885Sdumbbell#ifdef __BIG_ENDIAN 1817254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 1818254885Sdumbbell R600_BUF_SWAP_32BIT | 1819254885Sdumbbell R600_RB_NO_UPDATE | 1820254885Sdumbbell (dev_priv->ring.rptr_update_l2qw << 8) | 1821254885Sdumbbell dev_priv->ring.size_l2qw); 1822254885Sdumbbell#else 1823254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 1824254885Sdumbbell RADEON_RB_NO_UPDATE | 1825254885Sdumbbell (dev_priv->ring.rptr_update_l2qw << 8) | 1826254885Sdumbbell dev_priv->ring.size_l2qw); 1827254885Sdumbbell#endif 1828254885Sdumbbell 1829254885Sdumbbell RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x0); 1830254885Sdumbbell 1831254885Sdumbbell /* Set the write pointer delay */ 1832254885Sdumbbell RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 1833254885Sdumbbell 1834254885Sdumbbell#ifdef __BIG_ENDIAN 1835254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 1836254885Sdumbbell R600_BUF_SWAP_32BIT | 1837254885Sdumbbell R600_RB_NO_UPDATE | 1838254885Sdumbbell R600_RB_RPTR_WR_ENA | 1839254885Sdumbbell (dev_priv->ring.rptr_update_l2qw << 8) | 1840254885Sdumbbell dev_priv->ring.size_l2qw); 1841254885Sdumbbell#else 1842254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 1843254885Sdumbbell R600_RB_NO_UPDATE | 1844254885Sdumbbell R600_RB_RPTR_WR_ENA | 1845254885Sdumbbell (dev_priv->ring.rptr_update_l2qw << 8) | 1846254885Sdumbbell dev_priv->ring.size_l2qw); 1847254885Sdumbbell#endif 1848254885Sdumbbell 1849254885Sdumbbell /* Initialize the ring buffer's read and write pointers */ 1850254885Sdumbbell RADEON_WRITE(R600_CP_RB_RPTR_WR, 0); 1851254885Sdumbbell RADEON_WRITE(R600_CP_RB_WPTR, 0); 1852254885Sdumbbell SET_RING_HEAD(dev_priv, 0); 1853254885Sdumbbell dev_priv->ring.tail = 0; 1854254885Sdumbbell 1855254885Sdumbbell#if __OS_HAS_AGP 1856254885Sdumbbell if (dev_priv->flags & RADEON_IS_AGP) { 1857254885Sdumbbell rptr_addr = dev_priv->ring_rptr->offset 1858254885Sdumbbell - dev->agp->base + 1859254885Sdumbbell dev_priv->gart_vm_start; 1860254885Sdumbbell } else 1861254885Sdumbbell#endif 1862254885Sdumbbell { 1863254885Sdumbbell rptr_addr = dev_priv->ring_rptr->offset 1864254885Sdumbbell - ((unsigned long) dev->sg->vaddr) 1865254885Sdumbbell + dev_priv->gart_vm_start; 1866254885Sdumbbell } 1867254885Sdumbbell RADEON_WRITE(R600_CP_RB_RPTR_ADDR, (rptr_addr & 0xfffffffc)); 1868254885Sdumbbell RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, upper_32_bits(rptr_addr)); 1869254885Sdumbbell 1870254885Sdumbbell#ifdef __BIG_ENDIAN 1871254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 1872254885Sdumbbell RADEON_BUF_SWAP_32BIT | 1873254885Sdumbbell (dev_priv->ring.rptr_update_l2qw << 8) | 1874254885Sdumbbell dev_priv->ring.size_l2qw); 1875254885Sdumbbell#else 1876254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 1877254885Sdumbbell (dev_priv->ring.rptr_update_l2qw << 8) | 1878254885Sdumbbell dev_priv->ring.size_l2qw); 1879254885Sdumbbell#endif 1880254885Sdumbbell 1881254885Sdumbbell#if __OS_HAS_AGP 1882254885Sdumbbell if (dev_priv->flags & RADEON_IS_AGP) { 1883254885Sdumbbell /* XXX */ 1884254885Sdumbbell radeon_write_agp_base(dev_priv, dev->agp->base); 1885254885Sdumbbell 1886254885Sdumbbell /* XXX */ 1887254885Sdumbbell radeon_write_agp_location(dev_priv, 1888254885Sdumbbell (((dev_priv->gart_vm_start - 1 + 1889254885Sdumbbell dev_priv->gart_size) & 0xffff0000) | 1890254885Sdumbbell (dev_priv->gart_vm_start >> 16))); 1891254885Sdumbbell 1892254885Sdumbbell ring_start = (dev_priv->cp_ring->offset 1893254885Sdumbbell - dev->agp->base 1894254885Sdumbbell + dev_priv->gart_vm_start); 1895254885Sdumbbell } else 1896254885Sdumbbell#endif 1897254885Sdumbbell ring_start = (dev_priv->cp_ring->offset 1898254885Sdumbbell - (unsigned long)dev->sg->vaddr> 1899254885Sdumbbell + dev_priv->gart_vm_start); 1900254885Sdumbbell 1901254885Sdumbbell RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8); 1902254885Sdumbbell 1903254885Sdumbbell RADEON_WRITE(R600_CP_ME_CNTL, 0xff); 1904254885Sdumbbell 1905254885Sdumbbell RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28)); 1906254885Sdumbbell 1907254885Sdumbbell /* Initialize the scratch register pointer. This will cause 1908254885Sdumbbell * the scratch register values to be written out to memory 1909254885Sdumbbell * whenever they are updated. 1910254885Sdumbbell * 1911254885Sdumbbell * We simply put this behind the ring read pointer, this works 1912254885Sdumbbell * with PCI GART as well as (whatever kind of) AGP GART 1913254885Sdumbbell */ 1914254885Sdumbbell { 1915254885Sdumbbell u64 scratch_addr; 1916254885Sdumbbell 1917254885Sdumbbell scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR) & 0xFFFFFFFC; 1918254885Sdumbbell scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32; 1919254885Sdumbbell scratch_addr += R600_SCRATCH_REG_OFFSET; 1920254885Sdumbbell scratch_addr >>= 8; 1921254885Sdumbbell scratch_addr &= 0xffffffff; 1922254885Sdumbbell 1923254885Sdumbbell RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr); 1924254885Sdumbbell } 1925254885Sdumbbell 1926254885Sdumbbell RADEON_WRITE(R600_SCRATCH_UMSK, 0x7); 1927254885Sdumbbell 1928254885Sdumbbell /* Turn on bus mastering */ 1929254885Sdumbbell radeon_enable_bm(dev_priv); 1930254885Sdumbbell 1931254885Sdumbbell radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0); 1932254885Sdumbbell RADEON_WRITE(R600_LAST_FRAME_REG, 0); 1933254885Sdumbbell 1934254885Sdumbbell radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 1935254885Sdumbbell RADEON_WRITE(R600_LAST_DISPATCH_REG, 0); 1936254885Sdumbbell 1937254885Sdumbbell radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0); 1938254885Sdumbbell RADEON_WRITE(R600_LAST_CLEAR_REG, 0); 1939254885Sdumbbell 1940254885Sdumbbell /* reset sarea copies of these */ 1941282199Sdumbbell master_priv = file_priv->master->driver_priv; 1942254885Sdumbbell if (master_priv->sarea_priv) { 1943254885Sdumbbell master_priv->sarea_priv->last_frame = 0; 1944254885Sdumbbell master_priv->sarea_priv->last_dispatch = 0; 1945254885Sdumbbell master_priv->sarea_priv->last_clear = 0; 1946254885Sdumbbell } 1947254885Sdumbbell 1948254885Sdumbbell r600_do_wait_for_idle(dev_priv); 1949254885Sdumbbell 1950254885Sdumbbell} 1951254885Sdumbbell 1952254885Sdumbbellint r600_do_cleanup_cp(struct drm_device *dev) 1953254885Sdumbbell{ 1954254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 1955254885Sdumbbell DRM_DEBUG("\n"); 1956254885Sdumbbell 1957254885Sdumbbell /* Make sure interrupts are disabled here because the uninstall ioctl 1958254885Sdumbbell * may not have been called from userspace and after dev_private 1959254885Sdumbbell * is freed, it's too late. 1960254885Sdumbbell */ 1961254885Sdumbbell if (dev->irq_enabled) 1962254885Sdumbbell drm_irq_uninstall(dev); 1963254885Sdumbbell 1964254885Sdumbbell#if __OS_HAS_AGP 1965254885Sdumbbell if (dev_priv->flags & RADEON_IS_AGP) { 1966254885Sdumbbell if (dev_priv->cp_ring != NULL) { 1967254885Sdumbbell drm_core_ioremapfree(dev_priv->cp_ring, dev); 1968254885Sdumbbell dev_priv->cp_ring = NULL; 1969254885Sdumbbell } 1970254885Sdumbbell if (dev_priv->ring_rptr != NULL) { 1971254885Sdumbbell drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1972254885Sdumbbell dev_priv->ring_rptr = NULL; 1973254885Sdumbbell } 1974254885Sdumbbell if (dev->agp_buffer_map != NULL) { 1975254885Sdumbbell drm_core_ioremapfree(dev->agp_buffer_map, dev); 1976254885Sdumbbell dev->agp_buffer_map = NULL; 1977254885Sdumbbell } 1978254885Sdumbbell } else 1979254885Sdumbbell#endif 1980254885Sdumbbell { 1981254885Sdumbbell 1982254885Sdumbbell if (dev_priv->gart_info.bus_addr) 1983254885Sdumbbell r600_page_table_cleanup(dev, &dev_priv->gart_info); 1984254885Sdumbbell 1985254885Sdumbbell if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { 1986254885Sdumbbell drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); 1987254885Sdumbbell dev_priv->gart_info.addr = NULL; 1988254885Sdumbbell } 1989254885Sdumbbell } 1990254885Sdumbbell /* only clear to the start of flags */ 1991254885Sdumbbell memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1992254885Sdumbbell 1993254885Sdumbbell return 0; 1994254885Sdumbbell} 1995254885Sdumbbell 1996254885Sdumbbellint r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 1997254885Sdumbbell struct drm_file *file_priv) 1998254885Sdumbbell{ 1999254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 2000282199Sdumbbell struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; 2001254885Sdumbbell 2002254885Sdumbbell DRM_DEBUG("\n"); 2003254885Sdumbbell 2004254885Sdumbbell sx_init(&dev_priv->cs_mutex, "drm__radeon_private__cs_mutex"); 2005254885Sdumbbell r600_cs_legacy_init(); 2006254885Sdumbbell /* if we require new memory map but we don't have it fail */ 2007254885Sdumbbell if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { 2008254885Sdumbbell DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); 2009254885Sdumbbell r600_do_cleanup_cp(dev); 2010254885Sdumbbell return -EINVAL; 2011254885Sdumbbell } 2012254885Sdumbbell 2013254885Sdumbbell if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { 2014254885Sdumbbell DRM_DEBUG("Forcing AGP card to PCI mode\n"); 2015254885Sdumbbell dev_priv->flags &= ~RADEON_IS_AGP; 2016254885Sdumbbell /* The writeback test succeeds, but when writeback is enabled, 2017254885Sdumbbell * the ring buffer read ptr update fails after first 128 bytes. 2018254885Sdumbbell */ 2019254885Sdumbbell radeon_no_wb = 1; 2020254885Sdumbbell } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) 2021254885Sdumbbell && !init->is_pci) { 2022254885Sdumbbell DRM_DEBUG("Restoring AGP flag\n"); 2023254885Sdumbbell dev_priv->flags |= RADEON_IS_AGP; 2024254885Sdumbbell } 2025254885Sdumbbell 2026254885Sdumbbell dev_priv->usec_timeout = init->usec_timeout; 2027254885Sdumbbell if (dev_priv->usec_timeout < 1 || 2028254885Sdumbbell dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 2029254885Sdumbbell DRM_DEBUG("TIMEOUT problem!\n"); 2030254885Sdumbbell r600_do_cleanup_cp(dev); 2031254885Sdumbbell return -EINVAL; 2032254885Sdumbbell } 2033254885Sdumbbell 2034254885Sdumbbell /* Enable vblank on CRTC1 for older X servers 2035254885Sdumbbell */ 2036254885Sdumbbell dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; 2037254885Sdumbbell dev_priv->do_boxes = 0; 2038254885Sdumbbell dev_priv->cp_mode = init->cp_mode; 2039254885Sdumbbell 2040254885Sdumbbell /* We don't support anything other than bus-mastering ring mode, 2041254885Sdumbbell * but the ring can be in either AGP or PCI space for the ring 2042254885Sdumbbell * read pointer. 2043254885Sdumbbell */ 2044254885Sdumbbell if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 2045254885Sdumbbell (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 2046254885Sdumbbell DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 2047254885Sdumbbell r600_do_cleanup_cp(dev); 2048254885Sdumbbell return -EINVAL; 2049254885Sdumbbell } 2050254885Sdumbbell 2051254885Sdumbbell switch (init->fb_bpp) { 2052254885Sdumbbell case 16: 2053254885Sdumbbell dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 2054254885Sdumbbell break; 2055254885Sdumbbell case 32: 2056254885Sdumbbell default: 2057254885Sdumbbell dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 2058254885Sdumbbell break; 2059254885Sdumbbell } 2060254885Sdumbbell dev_priv->front_offset = init->front_offset; 2061254885Sdumbbell dev_priv->front_pitch = init->front_pitch; 2062254885Sdumbbell dev_priv->back_offset = init->back_offset; 2063254885Sdumbbell dev_priv->back_pitch = init->back_pitch; 2064254885Sdumbbell 2065254885Sdumbbell dev_priv->ring_offset = init->ring_offset; 2066254885Sdumbbell dev_priv->ring_rptr_offset = init->ring_rptr_offset; 2067254885Sdumbbell dev_priv->buffers_offset = init->buffers_offset; 2068254885Sdumbbell dev_priv->gart_textures_offset = init->gart_textures_offset; 2069254885Sdumbbell 2070254885Sdumbbell master_priv->sarea = drm_getsarea(dev); 2071254885Sdumbbell if (!master_priv->sarea) { 2072254885Sdumbbell DRM_ERROR("could not find sarea!\n"); 2073254885Sdumbbell r600_do_cleanup_cp(dev); 2074254885Sdumbbell return -EINVAL; 2075254885Sdumbbell } 2076254885Sdumbbell 2077254885Sdumbbell dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 2078254885Sdumbbell if (!dev_priv->cp_ring) { 2079254885Sdumbbell DRM_ERROR("could not find cp ring region!\n"); 2080254885Sdumbbell r600_do_cleanup_cp(dev); 2081254885Sdumbbell return -EINVAL; 2082254885Sdumbbell } 2083254885Sdumbbell dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 2084254885Sdumbbell if (!dev_priv->ring_rptr) { 2085254885Sdumbbell DRM_ERROR("could not find ring read pointer!\n"); 2086254885Sdumbbell r600_do_cleanup_cp(dev); 2087254885Sdumbbell return -EINVAL; 2088254885Sdumbbell } 2089254885Sdumbbell dev->agp_buffer_token = init->buffers_offset; 2090254885Sdumbbell dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 2091254885Sdumbbell if (!dev->agp_buffer_map) { 2092254885Sdumbbell DRM_ERROR("could not find dma buffer region!\n"); 2093254885Sdumbbell r600_do_cleanup_cp(dev); 2094254885Sdumbbell return -EINVAL; 2095254885Sdumbbell } 2096254885Sdumbbell 2097254885Sdumbbell if (init->gart_textures_offset) { 2098254885Sdumbbell dev_priv->gart_textures = 2099254885Sdumbbell drm_core_findmap(dev, init->gart_textures_offset); 2100254885Sdumbbell if (!dev_priv->gart_textures) { 2101254885Sdumbbell DRM_ERROR("could not find GART texture region!\n"); 2102254885Sdumbbell r600_do_cleanup_cp(dev); 2103254885Sdumbbell return -EINVAL; 2104254885Sdumbbell } 2105254885Sdumbbell } 2106254885Sdumbbell 2107254885Sdumbbell#if __OS_HAS_AGP 2108254885Sdumbbell /* XXX */ 2109254885Sdumbbell if (dev_priv->flags & RADEON_IS_AGP) { 2110254885Sdumbbell drm_core_ioremap_wc(dev_priv->cp_ring, dev); 2111254885Sdumbbell drm_core_ioremap_wc(dev_priv->ring_rptr, dev); 2112254885Sdumbbell drm_core_ioremap_wc(dev->agp_buffer_map, dev); 2113254885Sdumbbell if (!dev_priv->cp_ring->handle || 2114254885Sdumbbell !dev_priv->ring_rptr->handle || 2115254885Sdumbbell !dev->agp_buffer_map->handle) { 2116254885Sdumbbell DRM_ERROR("could not find ioremap agp regions!\n"); 2117254885Sdumbbell r600_do_cleanup_cp(dev); 2118254885Sdumbbell return -EINVAL; 2119254885Sdumbbell } 2120254885Sdumbbell } else 2121254885Sdumbbell#endif 2122254885Sdumbbell { 2123254885Sdumbbell dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset; 2124254885Sdumbbell dev_priv->ring_rptr->handle = 2125254885Sdumbbell (void *)(unsigned long)dev_priv->ring_rptr->offset; 2126254885Sdumbbell dev->agp_buffer_map->handle = 2127254885Sdumbbell (void *)(unsigned long)dev->agp_buffer_map->offset; 2128254885Sdumbbell 2129254885Sdumbbell DRM_DEBUG("dev_priv->cp_ring->handle %p\n", 2130254885Sdumbbell dev_priv->cp_ring->handle); 2131254885Sdumbbell DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", 2132254885Sdumbbell dev_priv->ring_rptr->handle); 2133254885Sdumbbell DRM_DEBUG("dev->agp_buffer_map->handle %p\n", 2134254885Sdumbbell dev->agp_buffer_map->handle); 2135254885Sdumbbell } 2136254885Sdumbbell 2137254885Sdumbbell dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24; 2138254885Sdumbbell dev_priv->fb_size = 2139254885Sdumbbell (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000) 2140254885Sdumbbell - dev_priv->fb_location; 2141254885Sdumbbell 2142254885Sdumbbell dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | 2143254885Sdumbbell ((dev_priv->front_offset 2144254885Sdumbbell + dev_priv->fb_location) >> 10)); 2145254885Sdumbbell 2146254885Sdumbbell dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | 2147254885Sdumbbell ((dev_priv->back_offset 2148254885Sdumbbell + dev_priv->fb_location) >> 10)); 2149254885Sdumbbell 2150254885Sdumbbell dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | 2151254885Sdumbbell ((dev_priv->depth_offset 2152254885Sdumbbell + dev_priv->fb_location) >> 10)); 2153254885Sdumbbell 2154254885Sdumbbell dev_priv->gart_size = init->gart_size; 2155254885Sdumbbell 2156254885Sdumbbell /* New let's set the memory map ... */ 2157254885Sdumbbell if (dev_priv->new_memmap) { 2158254885Sdumbbell u32 base = 0; 2159254885Sdumbbell 2160254885Sdumbbell DRM_INFO("Setting GART location based on new memory map\n"); 2161254885Sdumbbell 2162254885Sdumbbell /* If using AGP, try to locate the AGP aperture at the same 2163254885Sdumbbell * location in the card and on the bus, though we have to 2164254885Sdumbbell * align it down. 2165254885Sdumbbell */ 2166254885Sdumbbell#if __OS_HAS_AGP 2167254885Sdumbbell /* XXX */ 2168254885Sdumbbell if (dev_priv->flags & RADEON_IS_AGP) { 2169254885Sdumbbell base = dev->agp->base; 2170254885Sdumbbell /* Check if valid */ 2171254885Sdumbbell if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && 2172254885Sdumbbell base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { 2173254885Sdumbbell DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", 2174254885Sdumbbell dev->agp->base); 2175254885Sdumbbell base = 0; 2176254885Sdumbbell } 2177254885Sdumbbell } 2178254885Sdumbbell#endif 2179254885Sdumbbell /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ 2180254885Sdumbbell if (base == 0) { 2181254885Sdumbbell base = dev_priv->fb_location + dev_priv->fb_size; 2182254885Sdumbbell if (base < dev_priv->fb_location || 2183254885Sdumbbell ((base + dev_priv->gart_size) & 0xfffffffful) < base) 2184254885Sdumbbell base = dev_priv->fb_location 2185254885Sdumbbell - dev_priv->gart_size; 2186254885Sdumbbell } 2187254885Sdumbbell dev_priv->gart_vm_start = base & 0xffc00000u; 2188254885Sdumbbell if (dev_priv->gart_vm_start != base) 2189254885Sdumbbell DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", 2190254885Sdumbbell base, dev_priv->gart_vm_start); 2191254885Sdumbbell } 2192254885Sdumbbell 2193254885Sdumbbell#if __OS_HAS_AGP 2194254885Sdumbbell /* XXX */ 2195254885Sdumbbell if (dev_priv->flags & RADEON_IS_AGP) 2196254885Sdumbbell dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2197254885Sdumbbell - dev->agp->base 2198254885Sdumbbell + dev_priv->gart_vm_start); 2199254885Sdumbbell else 2200254885Sdumbbell#endif 2201254885Sdumbbell dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2202254885Sdumbbell - (unsigned long)dev->sg->vaddr 2203254885Sdumbbell + dev_priv->gart_vm_start); 2204254885Sdumbbell 2205254885Sdumbbell DRM_DEBUG("fb 0x%08x size %d\n", 2206254885Sdumbbell (unsigned int) dev_priv->fb_location, 2207254885Sdumbbell (unsigned int) dev_priv->fb_size); 2208254885Sdumbbell DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); 2209254885Sdumbbell DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n", 2210254885Sdumbbell (unsigned int) dev_priv->gart_vm_start); 2211254885Sdumbbell DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n", 2212254885Sdumbbell dev_priv->gart_buffers_offset); 2213254885Sdumbbell 2214254885Sdumbbell dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; 2215254885Sdumbbell dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle 2216254885Sdumbbell + init->ring_size / sizeof(u32)); 2217254885Sdumbbell dev_priv->ring.size = init->ring_size; 2218254885Sdumbbell dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 2219254885Sdumbbell 2220254885Sdumbbell dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; 2221254885Sdumbbell dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8); 2222254885Sdumbbell 2223254885Sdumbbell dev_priv->ring.fetch_size = /* init->fetch_size */ 32; 2224254885Sdumbbell dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16); 2225254885Sdumbbell 2226254885Sdumbbell dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 2227254885Sdumbbell 2228254885Sdumbbell dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 2229254885Sdumbbell 2230254885Sdumbbell#if __OS_HAS_AGP 2231254885Sdumbbell if (dev_priv->flags & RADEON_IS_AGP) { 2232254885Sdumbbell /* XXX turn off pcie gart */ 2233254885Sdumbbell } else 2234254885Sdumbbell#endif 2235254885Sdumbbell { 2236254885Sdumbbell dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); 2237254885Sdumbbell /* if we have an offset set from userspace */ 2238254885Sdumbbell if (!dev_priv->pcigart_offset_set) { 2239254885Sdumbbell DRM_ERROR("Need gart offset from userspace\n"); 2240254885Sdumbbell r600_do_cleanup_cp(dev); 2241254885Sdumbbell return -EINVAL; 2242254885Sdumbbell } 2243254885Sdumbbell 2244254885Sdumbbell DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset); 2245254885Sdumbbell 2246254885Sdumbbell dev_priv->gart_info.bus_addr = 2247254885Sdumbbell dev_priv->pcigart_offset + dev_priv->fb_location; 2248254885Sdumbbell dev_priv->gart_info.mapping.offset = 2249254885Sdumbbell dev_priv->pcigart_offset + dev_priv->fb_aper_offset; 2250254885Sdumbbell dev_priv->gart_info.mapping.size = 2251254885Sdumbbell dev_priv->gart_info.table_size; 2252254885Sdumbbell 2253254885Sdumbbell drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); 2254254885Sdumbbell if (!dev_priv->gart_info.mapping.handle) { 2255254885Sdumbbell DRM_ERROR("ioremap failed.\n"); 2256254885Sdumbbell r600_do_cleanup_cp(dev); 2257254885Sdumbbell return -EINVAL; 2258254885Sdumbbell } 2259254885Sdumbbell 2260254885Sdumbbell dev_priv->gart_info.addr = 2261254885Sdumbbell dev_priv->gart_info.mapping.handle; 2262254885Sdumbbell 2263254885Sdumbbell DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", 2264254885Sdumbbell dev_priv->gart_info.addr, 2265254885Sdumbbell dev_priv->pcigart_offset); 2266254885Sdumbbell 2267254885Sdumbbell if (!r600_page_table_init(dev)) { 2268254885Sdumbbell DRM_ERROR("Failed to init GART table\n"); 2269254885Sdumbbell r600_do_cleanup_cp(dev); 2270254885Sdumbbell return -EINVAL; 2271254885Sdumbbell } 2272254885Sdumbbell 2273254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2274254885Sdumbbell r700_vm_init(dev); 2275254885Sdumbbell else 2276254885Sdumbbell r600_vm_init(dev); 2277254885Sdumbbell } 2278254885Sdumbbell 2279254885Sdumbbell if (!dev_priv->me_fw || !dev_priv->pfp_fw) { 2280254885Sdumbbell int err = r600_cp_init_microcode(dev_priv); 2281254885Sdumbbell if (err) { 2282254885Sdumbbell DRM_ERROR("Failed to load firmware!\n"); 2283254885Sdumbbell r600_do_cleanup_cp(dev); 2284254885Sdumbbell return err; 2285254885Sdumbbell } 2286254885Sdumbbell } 2287254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2288254885Sdumbbell r700_cp_load_microcode(dev_priv); 2289254885Sdumbbell else 2290254885Sdumbbell r600_cp_load_microcode(dev_priv); 2291254885Sdumbbell 2292254885Sdumbbell r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2293254885Sdumbbell 2294254885Sdumbbell dev_priv->last_buf = 0; 2295254885Sdumbbell 2296254885Sdumbbell r600_do_engine_reset(dev); 2297254885Sdumbbell r600_test_writeback(dev_priv); 2298254885Sdumbbell 2299254885Sdumbbell return 0; 2300254885Sdumbbell} 2301254885Sdumbbell 2302254885Sdumbbellint r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv) 2303254885Sdumbbell{ 2304254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 2305254885Sdumbbell 2306254885Sdumbbell DRM_DEBUG("\n"); 2307254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) { 2308254885Sdumbbell r700_vm_init(dev); 2309254885Sdumbbell r700_cp_load_microcode(dev_priv); 2310254885Sdumbbell } else { 2311254885Sdumbbell r600_vm_init(dev); 2312254885Sdumbbell r600_cp_load_microcode(dev_priv); 2313254885Sdumbbell } 2314254885Sdumbbell r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2315254885Sdumbbell r600_do_engine_reset(dev); 2316254885Sdumbbell 2317254885Sdumbbell return 0; 2318254885Sdumbbell} 2319254885Sdumbbell 2320254885Sdumbbell/* Wait for the CP to go idle. 2321254885Sdumbbell */ 2322254885Sdumbbellint r600_do_cp_idle(drm_radeon_private_t *dev_priv) 2323254885Sdumbbell{ 2324254885Sdumbbell RING_LOCALS; 2325254885Sdumbbell DRM_DEBUG("\n"); 2326254885Sdumbbell 2327254885Sdumbbell BEGIN_RING(5); 2328254885Sdumbbell OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); 2329254885Sdumbbell OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); 2330254885Sdumbbell /* wait for 3D idle clean */ 2331254885Sdumbbell OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); 2332254885Sdumbbell OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); 2333254885Sdumbbell OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); 2334254885Sdumbbell 2335254885Sdumbbell ADVANCE_RING(); 2336254885Sdumbbell COMMIT_RING(); 2337254885Sdumbbell 2338254885Sdumbbell return r600_do_wait_for_idle(dev_priv); 2339254885Sdumbbell} 2340254885Sdumbbell 2341254885Sdumbbell/* Start the Command Processor. 2342254885Sdumbbell */ 2343254885Sdumbbellvoid r600_do_cp_start(drm_radeon_private_t *dev_priv) 2344254885Sdumbbell{ 2345254885Sdumbbell u32 cp_me; 2346254885Sdumbbell RING_LOCALS; 2347254885Sdumbbell DRM_DEBUG("\n"); 2348254885Sdumbbell 2349254885Sdumbbell BEGIN_RING(7); 2350254885Sdumbbell OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); 2351254885Sdumbbell OUT_RING(0x00000001); 2352254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) 2353254885Sdumbbell OUT_RING(0x00000003); 2354254885Sdumbbell else 2355254885Sdumbbell OUT_RING(0x00000000); 2356254885Sdumbbell OUT_RING((dev_priv->r600_max_hw_contexts - 1)); 2357254885Sdumbbell OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1)); 2358254885Sdumbbell OUT_RING(0x00000000); 2359254885Sdumbbell OUT_RING(0x00000000); 2360254885Sdumbbell ADVANCE_RING(); 2361254885Sdumbbell COMMIT_RING(); 2362254885Sdumbbell 2363254885Sdumbbell /* set the mux and reset the halt bit */ 2364254885Sdumbbell cp_me = 0xff; 2365254885Sdumbbell RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2366254885Sdumbbell 2367254885Sdumbbell dev_priv->cp_running = 1; 2368254885Sdumbbell 2369254885Sdumbbell} 2370254885Sdumbbell 2371254885Sdumbbellvoid r600_do_cp_reset(drm_radeon_private_t *dev_priv) 2372254885Sdumbbell{ 2373254885Sdumbbell u32 cur_read_ptr; 2374254885Sdumbbell DRM_DEBUG("\n"); 2375254885Sdumbbell 2376254885Sdumbbell cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR); 2377254885Sdumbbell RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr); 2378254885Sdumbbell SET_RING_HEAD(dev_priv, cur_read_ptr); 2379254885Sdumbbell dev_priv->ring.tail = cur_read_ptr; 2380254885Sdumbbell} 2381254885Sdumbbell 2382254885Sdumbbellvoid r600_do_cp_stop(drm_radeon_private_t *dev_priv) 2383254885Sdumbbell{ 2384254885Sdumbbell uint32_t cp_me; 2385254885Sdumbbell 2386254885Sdumbbell DRM_DEBUG("\n"); 2387254885Sdumbbell 2388254885Sdumbbell cp_me = 0xff | R600_CP_ME_HALT; 2389254885Sdumbbell 2390254885Sdumbbell RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2391254885Sdumbbell 2392254885Sdumbbell dev_priv->cp_running = 0; 2393254885Sdumbbell} 2394254885Sdumbbell 2395254885Sdumbbellint r600_cp_dispatch_indirect(struct drm_device *dev, 2396254885Sdumbbell struct drm_buf *buf, int start, int end) 2397254885Sdumbbell{ 2398254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 2399254885Sdumbbell RING_LOCALS; 2400254885Sdumbbell 2401254885Sdumbbell if (start != end) { 2402254885Sdumbbell unsigned long offset = (dev_priv->gart_buffers_offset 2403254885Sdumbbell + buf->offset + start); 2404254885Sdumbbell int dwords = (end - start + 3) / sizeof(u32); 2405254885Sdumbbell 2406254885Sdumbbell DRM_DEBUG("dwords:%d\n", dwords); 2407254885Sdumbbell DRM_DEBUG("offset 0x%lx\n", offset); 2408254885Sdumbbell 2409254885Sdumbbell 2410254885Sdumbbell /* Indirect buffer data must be a multiple of 16 dwords. 2411254885Sdumbbell * pad the data with a Type-2 CP packet. 2412254885Sdumbbell */ 2413254885Sdumbbell while (dwords & 0xf) { 2414254885Sdumbbell u32 *data = (u32 *) 2415254885Sdumbbell ((char *)dev->agp_buffer_map->handle 2416254885Sdumbbell + buf->offset + start); 2417254885Sdumbbell data[dwords++] = RADEON_CP_PACKET2; 2418254885Sdumbbell } 2419254885Sdumbbell 2420254885Sdumbbell /* Fire off the indirect buffer */ 2421254885Sdumbbell BEGIN_RING(4); 2422254885Sdumbbell OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2)); 2423254885Sdumbbell OUT_RING((offset & 0xfffffffc)); 2424254885Sdumbbell OUT_RING((upper_32_bits(offset) & 0xff)); 2425254885Sdumbbell OUT_RING(dwords); 2426254885Sdumbbell ADVANCE_RING(); 2427254885Sdumbbell } 2428254885Sdumbbell 2429254885Sdumbbell return 0; 2430254885Sdumbbell} 2431254885Sdumbbell 2432254885Sdumbbellvoid r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv) 2433254885Sdumbbell{ 2434254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 2435282199Sdumbbell struct drm_master *master = file_priv->master; 2436254885Sdumbbell struct drm_radeon_master_private *master_priv = master->driver_priv; 2437254885Sdumbbell drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; 2438254885Sdumbbell int nbox = sarea_priv->nbox; 2439254885Sdumbbell struct drm_clip_rect *pbox = sarea_priv->boxes; 2440254885Sdumbbell int i, cpp, src_pitch, dst_pitch; 2441254885Sdumbbell uint64_t src, dst; 2442254885Sdumbbell RING_LOCALS; 2443254885Sdumbbell DRM_DEBUG("\n"); 2444254885Sdumbbell 2445254885Sdumbbell if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888) 2446254885Sdumbbell cpp = 4; 2447254885Sdumbbell else 2448254885Sdumbbell cpp = 2; 2449254885Sdumbbell 2450254885Sdumbbell if (sarea_priv->pfCurrentPage == 0) { 2451254885Sdumbbell src_pitch = dev_priv->back_pitch; 2452254885Sdumbbell dst_pitch = dev_priv->front_pitch; 2453254885Sdumbbell src = dev_priv->back_offset + dev_priv->fb_location; 2454254885Sdumbbell dst = dev_priv->front_offset + dev_priv->fb_location; 2455254885Sdumbbell } else { 2456254885Sdumbbell src_pitch = dev_priv->front_pitch; 2457254885Sdumbbell dst_pitch = dev_priv->back_pitch; 2458254885Sdumbbell src = dev_priv->front_offset + dev_priv->fb_location; 2459254885Sdumbbell dst = dev_priv->back_offset + dev_priv->fb_location; 2460254885Sdumbbell } 2461254885Sdumbbell 2462254885Sdumbbell if (r600_prepare_blit_copy(dev, file_priv)) { 2463254885Sdumbbell DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); 2464254885Sdumbbell return; 2465254885Sdumbbell } 2466254885Sdumbbell for (i = 0; i < nbox; i++) { 2467254885Sdumbbell int x = pbox[i].x1; 2468254885Sdumbbell int y = pbox[i].y1; 2469254885Sdumbbell int w = pbox[i].x2 - x; 2470254885Sdumbbell int h = pbox[i].y2 - y; 2471254885Sdumbbell 2472254885Sdumbbell DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h); 2473254885Sdumbbell 2474254885Sdumbbell r600_blit_swap(dev, 2475254885Sdumbbell src, dst, 2476254885Sdumbbell x, y, x, y, w, h, 2477254885Sdumbbell src_pitch, dst_pitch, cpp); 2478254885Sdumbbell } 2479254885Sdumbbell r600_done_blit_copy(dev); 2480254885Sdumbbell 2481254885Sdumbbell /* Increment the frame counter. The client-side 3D driver must 2482254885Sdumbbell * throttle the framerate by waiting for this value before 2483254885Sdumbbell * performing the swapbuffer ioctl. 2484254885Sdumbbell */ 2485254885Sdumbbell sarea_priv->last_frame++; 2486254885Sdumbbell 2487254885Sdumbbell BEGIN_RING(3); 2488254885Sdumbbell R600_FRAME_AGE(sarea_priv->last_frame); 2489254885Sdumbbell ADVANCE_RING(); 2490254885Sdumbbell} 2491254885Sdumbbell 2492254885Sdumbbellint r600_cp_dispatch_texture(struct drm_device *dev, 2493254885Sdumbbell struct drm_file *file_priv, 2494254885Sdumbbell drm_radeon_texture_t *tex, 2495254885Sdumbbell drm_radeon_tex_image_t *image) 2496254885Sdumbbell{ 2497254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 2498254885Sdumbbell struct drm_buf *buf; 2499254885Sdumbbell u32 *buffer; 2500254885Sdumbbell const u8 __user *data; 2501254885Sdumbbell int size, pass_size; 2502254885Sdumbbell u64 src_offset, dst_offset; 2503254885Sdumbbell 2504254885Sdumbbell if (!radeon_check_offset(dev_priv, tex->offset)) { 2505254885Sdumbbell DRM_ERROR("Invalid destination offset\n"); 2506254885Sdumbbell return -EINVAL; 2507254885Sdumbbell } 2508254885Sdumbbell 2509254885Sdumbbell /* this might fail for zero-sized uploads - are those illegal? */ 2510254885Sdumbbell if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) { 2511254885Sdumbbell DRM_ERROR("Invalid final destination offset\n"); 2512254885Sdumbbell return -EINVAL; 2513254885Sdumbbell } 2514254885Sdumbbell 2515254885Sdumbbell size = tex->height * tex->pitch; 2516254885Sdumbbell 2517254885Sdumbbell if (size == 0) 2518254885Sdumbbell return 0; 2519254885Sdumbbell 2520254885Sdumbbell dst_offset = tex->offset; 2521254885Sdumbbell 2522254885Sdumbbell if (r600_prepare_blit_copy(dev, file_priv)) { 2523254885Sdumbbell DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); 2524254885Sdumbbell return -EAGAIN; 2525254885Sdumbbell } 2526254885Sdumbbell do { 2527254885Sdumbbell data = (const u8 __user *)image->data; 2528254885Sdumbbell pass_size = size; 2529254885Sdumbbell 2530254885Sdumbbell buf = radeon_freelist_get(dev); 2531254885Sdumbbell if (!buf) { 2532254885Sdumbbell DRM_DEBUG("EAGAIN\n"); 2533254885Sdumbbell if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) 2534254885Sdumbbell return -EFAULT; 2535254885Sdumbbell return -EAGAIN; 2536254885Sdumbbell } 2537254885Sdumbbell 2538254885Sdumbbell if (pass_size > buf->total) 2539254885Sdumbbell pass_size = buf->total; 2540254885Sdumbbell 2541254885Sdumbbell /* Dispatch the indirect buffer. 2542254885Sdumbbell */ 2543254885Sdumbbell buffer = 2544254885Sdumbbell (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); 2545254885Sdumbbell 2546254885Sdumbbell if (DRM_COPY_FROM_USER(buffer, data, pass_size)) { 2547254885Sdumbbell DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size); 2548254885Sdumbbell return -EFAULT; 2549254885Sdumbbell } 2550254885Sdumbbell 2551254885Sdumbbell buf->file_priv = file_priv; 2552254885Sdumbbell buf->used = pass_size; 2553254885Sdumbbell src_offset = dev_priv->gart_buffers_offset + buf->offset; 2554254885Sdumbbell 2555254885Sdumbbell r600_blit_copy(dev, src_offset, dst_offset, pass_size); 2556254885Sdumbbell 2557282199Sdumbbell radeon_cp_discard_buffer(dev, file_priv->master, buf); 2558254885Sdumbbell 2559254885Sdumbbell /* Update the input parameters for next time */ 2560254885Sdumbbell image->data = (const u8 __user *)image->data + pass_size; 2561254885Sdumbbell dst_offset += pass_size; 2562254885Sdumbbell size -= pass_size; 2563254885Sdumbbell } while (size > 0); 2564254885Sdumbbell r600_done_blit_copy(dev); 2565254885Sdumbbell 2566254885Sdumbbell return 0; 2567254885Sdumbbell} 2568254885Sdumbbell 2569254885Sdumbbell/* 2570254885Sdumbbell * Legacy cs ioctl 2571254885Sdumbbell */ 2572254885Sdumbbellstatic u32 radeon_cs_id_get(struct drm_radeon_private *radeon) 2573254885Sdumbbell{ 2574254885Sdumbbell /* FIXME: check if wrap affect last reported wrap & sequence */ 2575254885Sdumbbell radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF; 2576254885Sdumbbell if (!radeon->cs_id_scnt) { 2577254885Sdumbbell /* increment wrap counter */ 2578254885Sdumbbell radeon->cs_id_wcnt += 0x01000000; 2579254885Sdumbbell /* valid sequence counter start at 1 */ 2580254885Sdumbbell radeon->cs_id_scnt = 1; 2581254885Sdumbbell } 2582254885Sdumbbell return (radeon->cs_id_scnt | radeon->cs_id_wcnt); 2583254885Sdumbbell} 2584254885Sdumbbell 2585254885Sdumbbellstatic void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id) 2586254885Sdumbbell{ 2587254885Sdumbbell RING_LOCALS; 2588254885Sdumbbell 2589254885Sdumbbell *id = radeon_cs_id_get(dev_priv); 2590254885Sdumbbell 2591254885Sdumbbell /* SCRATCH 2 */ 2592254885Sdumbbell BEGIN_RING(3); 2593254885Sdumbbell R600_CLEAR_AGE(*id); 2594254885Sdumbbell ADVANCE_RING(); 2595254885Sdumbbell COMMIT_RING(); 2596254885Sdumbbell} 2597254885Sdumbbell 2598254885Sdumbbellstatic int r600_ib_get(struct drm_device *dev, 2599254885Sdumbbell struct drm_file *fpriv, 2600254885Sdumbbell struct drm_buf **buffer) 2601254885Sdumbbell{ 2602254885Sdumbbell struct drm_buf *buf; 2603254885Sdumbbell 2604254885Sdumbbell *buffer = NULL; 2605254885Sdumbbell buf = radeon_freelist_get(dev); 2606254885Sdumbbell if (!buf) { 2607254885Sdumbbell return -EBUSY; 2608254885Sdumbbell } 2609254885Sdumbbell buf->file_priv = fpriv; 2610254885Sdumbbell *buffer = buf; 2611254885Sdumbbell return 0; 2612254885Sdumbbell} 2613254885Sdumbbell 2614254885Sdumbbellstatic void r600_ib_free(struct drm_device *dev, struct drm_buf *buf, 2615254885Sdumbbell struct drm_file *fpriv, int l, int r) 2616254885Sdumbbell{ 2617254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 2618254885Sdumbbell 2619254885Sdumbbell if (buf) { 2620254885Sdumbbell if (!r) 2621254885Sdumbbell r600_cp_dispatch_indirect(dev, buf, 0, l * 4); 2622282199Sdumbbell radeon_cp_discard_buffer(dev, fpriv->master, buf); 2623254885Sdumbbell COMMIT_RING(); 2624254885Sdumbbell } 2625254885Sdumbbell} 2626254885Sdumbbell 2627254885Sdumbbellint r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv) 2628254885Sdumbbell{ 2629254885Sdumbbell struct drm_radeon_private *dev_priv = dev->dev_private; 2630254885Sdumbbell struct drm_radeon_cs *cs = data; 2631254885Sdumbbell struct drm_buf *buf; 2632254885Sdumbbell unsigned family; 2633254885Sdumbbell int l, r = 0; 2634254885Sdumbbell u32 *ib, cs_id = 0; 2635254885Sdumbbell 2636254885Sdumbbell if (dev_priv == NULL) { 2637254885Sdumbbell DRM_ERROR("called with no initialization\n"); 2638254885Sdumbbell return -EINVAL; 2639254885Sdumbbell } 2640254885Sdumbbell family = dev_priv->flags & RADEON_FAMILY_MASK; 2641254885Sdumbbell if (family < CHIP_R600) { 2642254885Sdumbbell DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n"); 2643254885Sdumbbell return -EINVAL; 2644254885Sdumbbell } 2645254885Sdumbbell sx_xlock(&dev_priv->cs_mutex); 2646254885Sdumbbell /* get ib */ 2647254885Sdumbbell l = 0; 2648254885Sdumbbell r = r600_ib_get(dev, fpriv, &buf); 2649254885Sdumbbell if (r) { 2650254885Sdumbbell DRM_ERROR("ib_get failed\n"); 2651254885Sdumbbell goto out; 2652254885Sdumbbell } 2653254885Sdumbbell ib = (u32 *)((uintptr_t)dev->agp_buffer_map->handle + buf->offset); 2654254885Sdumbbell /* now parse command stream */ 2655254885Sdumbbell r = r600_cs_legacy(dev, data, fpriv, family, ib, &l); 2656254885Sdumbbell if (r) { 2657254885Sdumbbell goto out; 2658254885Sdumbbell } 2659254885Sdumbbell 2660254885Sdumbbellout: 2661254885Sdumbbell r600_ib_free(dev, buf, fpriv, l, r); 2662254885Sdumbbell /* emit cs id sequence */ 2663254885Sdumbbell r600_cs_id_emit(dev_priv, &cs_id); 2664254885Sdumbbell cs->cs_id = cs_id; 2665254885Sdumbbell sx_xunlock(&dev_priv->cs_mutex); 2666254885Sdumbbell return r; 2667254885Sdumbbell} 2668254885Sdumbbell 2669254885Sdumbbellvoid r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size) 2670254885Sdumbbell{ 2671254885Sdumbbell struct drm_radeon_private *dev_priv = dev->dev_private; 2672254885Sdumbbell 2673254885Sdumbbell *npipes = dev_priv->r600_npipes; 2674254885Sdumbbell *nbanks = dev_priv->r600_nbanks; 2675254885Sdumbbell *group_size = dev_priv->r600_group_size; 2676254885Sdumbbell} 2677