drm2/radeon/r600_blit.c

66 		OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
67 		OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
68 		OUT_RING(gpu_addr >> 8);
69 		OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
70 		OUT_RING(2 << 0);
73 		OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
74 		OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
75 		OUT_RING(gpu_addr >> 8);
78 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
79 	OUT_RING((R600_CB_COLOR0_SIZE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
80 	OUT_RING((pitch << 0) | (slice << 10));
82 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
83 	OUT_RING((R600_CB_COLOR0_VIEW - R600_SET_CONTEXT_REG_OFFSET) >> 2);
84 	OUT_RING(0);
86 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
87 	OUT_RING((R600_CB_COLOR0_INFO - R600_SET_CONTEXT_REG_OFFSET) >> 2);
88 	OUT_RING(cb_color_info);
90 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
91 	OUT_RING((R600_CB_COLOR0_TILE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
92 	OUT_RING(0);
94 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
95 	OUT_RING((R600_CB_COLOR0_FRAG - R600_SET_CONTEXT_REG_OFFSET) >> 2);
96 	OUT_RING(0);
98 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
99 	OUT_RING((R600_CB_COLOR0_MASK - R600_SET_CONTEXT_REG_OFFSET) >> 2);
100 	OUT_RING(0);
119 	OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
120 	OUT_RING(sync_type);
121 	OUT_RING(cp_coher_size);
122 	OUT_RING((mc_addr >> 8));
123 	OUT_RING(10); /* poll interval */
156 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
157 	OUT_RING((R600_SQ_PGM_START_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
158 	OUT_RING(gpu_addr >> 8);
160 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
161 	OUT_RING((R600_SQ_PGM_RESOURCES_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
162 	OUT_RING(sq_pgm_resources);
164 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
165 	OUT_RING((R600_SQ_PGM_CF_OFFSET_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
166 	OUT_RING(0);
169 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
170 	OUT_RING((R600_SQ_PGM_START_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
171 	OUT_RING((gpu_addr + 256) >> 8);
173 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
174 	OUT_RING((R600_SQ_PGM_RESOURCES_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
175 	OUT_RING(sq_pgm_resources | (1 << 28));
177 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
178 	OUT_RING((R600_SQ_PGM_EXPORTS_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
179 	OUT_RING(2);
181 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
182 	OUT_RING((R600_SQ_PGM_CF_OFFSET_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
183 	OUT_RING(0);
203 	OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
204 	OUT_RING(0x460);
205 	OUT_RING(gpu_addr & 0xffffffff);
206 	OUT_RING(48 - 1);
207 	OUT_RING(sq_vtx_constant_word2);
208 	OUT_RING(1 << 0);
209 	OUT_RING(0);
210 	OUT_RING(0);
211 	OUT_RING(R600_SQ_TEX_VTX_VALID_BUFFER << 30);
251 	OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
252 	OUT_RING(0);
253 	OUT_RING(sq_tex_resource_word0);
254 	OUT_RING(sq_tex_resource_word1);
255 	OUT_RING(gpu_addr >> 8);
256 	OUT_RING(gpu_addr >> 8);
257 	OUT_RING(sq_tex_resource_word4);
258 	OUT_RING(0);
259 	OUT_RING(R600_SQ_TEX_VTX_VALID_TEXTURE << 30);
271 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
272 	OUT_RING((R600_PA_SC_SCREEN_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
273 	OUT_RING((x1 << 0) | (y1 << 16));
274 	OUT_RING((x2 << 0) | (y2 << 16));
276 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
277 	OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
278 	OUT_RING((x1 << 0) | (y1 << 16) | (1U << 31));
279 	OUT_RING((x2 << 0) | (y2 << 16));
281 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
282 	OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
283 	OUT_RING((x1 << 0) | (y1 << 16) | (1U << 31));
284 	OUT_RING((x2 << 0) | (y2 << 16));
295 	OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
296 	OUT_RING((R600_VGT_PRIMITIVE_TYPE - R600_SET_CONFIG_REG_OFFSET) >> 2);
297 	OUT_RING(DI_PT_RECTLIST);
299 	OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
301 	OUT_RING((2 << 2) | DI_INDEX_SIZE_16_BIT);
303 	OUT_RING(DI_INDEX_SIZE_16_BIT);
306 	OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
307 	OUT_RING(1);
309 	OUT_RING(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
310 	OUT_RING(3);
311 	OUT_RING(DI_SRC_SEL_AUTO_INDEX);
475 			OUT_RING(r7xx_default_state[i]);
479 			OUT_RING(r6xx_default_state[i]);
481 	OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
482 	OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
484 	OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 6));
485 	OUT_RING((R600_SQ_CONFIG - R600_SET_CONFIG_REG_OFFSET) >> 2);
486 	OUT_RING(sq_config);
487 	OUT_RING(sq_gpr_resource_mgmt_1);
488 	OUT_RING(sq_gpr_resource_mgmt_2);
489 	OUT_RING(sq_thread_resource_mgmt);
490 	OUT_RING(sq_stack_resource_mgmt_1);
491 	OUT_RING(sq_stack_resource_mgmt_2);
580 	OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
581 	OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
583 	OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
584 	OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
585 	OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);