Searched refs:SRA (Results 1 - 25 of 40) sorted by relevance

12

/freebsd-10.1-release/contrib/telnet/libtelnet/
H A Dauth-proto.h102 #ifdef SRA
H A Dauth.c172 #ifdef SRA
H A Dsra.c35 #ifdef SRA
143 printf("Trying SRA secure login:\r\n");
153 /* server received an IS -- could be SRA KEY, USER, or PASS */
169 printf("SRA user rejected for bad PKB\r\n");
218 printf("SRA user accepted\r\n");
229 printf("SRA user failed\r\n");
236 printf("Unknown SRA option %d\r\n", data[-1]);
244 /* client received REPLY -- could be SRA KEY, CONTINUE, ACCEPT, or REJECT */
260 printf("SRA user rejected for bad PKB\r\n");
302 printf("[ SRA logi
[all...]
/freebsd-10.1-release/contrib/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h28 case ISD::SRA: return ARM_AM::asr;
/freebsd-10.1-release/crypto/heimdal/appl/telnet/libtelnet/
H A Dauth-proto.h91 #ifdef SRA
H A Dauth.c119 #ifdef SRA
/freebsd-10.1-release/contrib/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp185 { ISD::SRA, MVT::v4i32, 1 },
188 { ISD::SRA, MVT::v8i32, 1 },
200 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized.
201 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized.
202 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
237 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
238 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
239 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
269 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
270 { ISD::SRA, MV
[all...]
H A DX86ISelLowering.cpp844 setOperationAction(ISD::SRA, VT, Expand);
1099 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1100 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1110 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1172 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1173 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1257 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1399 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1400 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1509 setTargetDAGCombine(ISD::SRA);
12557 SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD, local
[all...]
/freebsd-10.1-release/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h306 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
370 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
/freebsd-10.1-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL enumerator in enum:llvm::MSP430ISD::__anon2503
H A DMSP430ISelLowering.cpp95 setOperationAction(ISD::SRA, MVT::i8, Custom);
98 setOperationAction(ISD::SRA, MVT::i16, Custom);
192 case ISD::SRA: return LowerShifts(Op, DAG);
756 case ISD::SRA:
757 return DAG.getNode(MSP430ISD::SRA, dl,
976 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
1160 case MSP430ISD::SRA: return "MSP430ISD::SRA";
/freebsd-10.1-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp74 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
570 return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt);
805 case ISD::SRA:
1159 case ISD::SRA:
1335 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1337 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1340 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1342 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1346 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1354 Hi = DAG.getNode(ISD::SRA, D
[all...]
H A DLegalizeVectorOps.cpp18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
64 // Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
209 case ISD::SRA:
490 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
638 // Make sure that the SRA and SHL instructions are available.
639 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
652 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
H A DDAGCombiner.cpp908 if (Opc == ISD::SRA)
1149 case ISD::SRA: return visitSRA(N);
1232 case ISD::SRA:
1959 SDValue SGN = DAG.getNode(ISD::SRA, SDLoc(N), VT, N0,
1971 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), VT, ADD, local
1977 return SRA;
1979 AddToWorkList(SRA.getNode());
1981 DAG.getConstant(0, VT), SRA);
2160 return DAG.getNode(ISD::SRA, SDLo
3914 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), LargeVT, local
[all...]
H A DFastISel.cpp413 ISDOpcode = ISD::SRA;
1011 return SelectBinaryOp(I, ISD::SRA);
1180 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
H A DSelectionDAGBuilder.h708 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
H A DSelectionDAGDumper.cpp170 case ISD::SRA: return "sra";
H A DLegalizeDAG.cpp1287 case ISD::SRA:
2966 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3577 // The high part is obtained by SRA'ing all but one of the bits of low
3580 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3582 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3604 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3825 case ISD::SRA:
3828 // Scalarize vector SRA/SRL/SHL.
/freebsd-10.1-release/contrib/llvm/lib/Target/R600/
H A DAMDILISelLowering.cpp347 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift);
414 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
/freebsd-10.1-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h101 SRL, SRA, SHL, enumerator in enum:llvm::PPCISD::NodeType
/freebsd-10.1-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp808 case ISD::SRA: {
819 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) {
/freebsd-10.1-release/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp78 setTargetDAGCombine(ISD::SRA);
98 setTargetDAGCombine(ISD::SRA);
183 setOperationAction(ISD::SRA, Ty, Legal);
789 // the ISD::SRA and ISD::SHL nodes.
790 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
986 case ISD::SRA:
1974 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
1980 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
H A DMipsISelLowering.cpp566 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
1110 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1338 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1909 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
1913 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
/freebsd-10.1-release/contrib/llvm/lib/TableGen/
H A DRecord.cpp950 case SRA:
961 case SRA: Result = LHSv >> RHSv; break;
987 case SRA: Result = "!sra"; break;
/freebsd-10.1-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp84 setTargetDAGCombine(ISD::SRA);
3047 // We're looking for an SRA/SHL pair which form an SBFX.
3427 /// Target-specific dag combine xforms for ISD::SRA
3435 // We're looking for an SRA/SHL pair which form an SBFX.
3511 if (N->getOpcode() == ISD::SRA && (VT == MVT::i32 || VT == MVT::i64))
3535 case ISD::SRA:
3803 case ISD::SRA:

Completed in 203 milliseconds

12