Target/X86/X86ISelLowering.cpp

844     setOperationAction(ISD::SRA, VT, Expand);
1099     setOperationAction(ISD::SRA,               MVT::v8i16, Custom);
1100     setOperationAction(ISD::SRA,               MVT::v16i8, Custom);
1110     setOperationAction(ISD::SRA,               MVT::v4i32, Custom);
1172     setOperationAction(ISD::SRA,               MVT::v16i16, Custom);
1173     setOperationAction(ISD::SRA,               MVT::v32i8, Custom);
1257     setOperationAction(ISD::SRA,               MVT::v8i32, Custom);
1399     setOperationAction(ISD::SRA,                MVT::v8i64, Custom);
1400     setOperationAction(ISD::SRA,                MVT::v16i32, Custom);
1509   setTargetDAGCombine(ISD::SRA);
8439   SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8449     Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11352       Opcode = ISD::SRA;
12545     SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
12557     SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
12564       return SRA;
12568     return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12597         if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12629         if (Op.getOpcode() == ISD::SRA) {
12675         if (Op.getOpcode() == ISD::SRA) {
12736     case ISD::SRA:
12752   if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12755        ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12829       case ISD::SRA:
12881     case ISD::SRA:
12921     if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
13462   case ISD::SRA:
17515   if (N->getOpcode() != ISD::SRA) {
17802         (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
17899       if (Mask.getOpcode() == ISD::SRA) {
18011   // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
18016       N1.getOpcode() == ISD::SRA &&
18226       if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18243       Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
19159   case ISD::SRA: