Searched refs:u64 (Results 1 - 25 of 458) sorted by relevance

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/freebsd-10.0-release/sys/ofed/include/linux/
H A Dclocksource.h14 typedef u64 cycle_t;
/freebsd-10.0-release/sys/dev/vxge/vxgehal/
H A Dvxgehal-memrepair-reg.h39 u64 unused1;
40 u64 unused2;
H A Dvxgehal-legacy-reg.h42 /* 0x00010 */ u64 toc_swapper_fb;
44 /* 0x00018 */ u64 pifm_rd_swap_en;
46 /* 0x00020 */ u64 pifm_rd_flip_en;
48 /* 0x00028 */ u64 pifm_wr_swap_en;
50 /* 0x00030 */ u64 pifm_wr_flip_en;
52 /* 0x00038 */ u64 toc_first_pointer;
54 /* 0x00040 */ u64 host_access_en;
H A Dvxgehal-pcicfgmgmt-reg.h40 /* 0x00000 */ u64 resource_no;
42 /* 0x00008 */ u64 bargrp_pf_or_vf_bar0_mask;
45 /* 0x00010 */ u64 bargrp_pf_or_vf_bar1_mask;
48 /* 0x00018 */ u64 bargrp_pf_or_vf_bar2_mask;
51 /* 0x00020 */ u64 msixgrp_no;
H A Dvxgehal-common-reg.h42 /* 0x00a00 */ u64 prc_status1;
44 /* 0x00a08 */ u64 rxdcm_reset_in_progress;
46 /* 0x00a10 */ u64 replicq_flush_in_progress;
48 /* 0x00a18 */ u64 rxpe_cmds_reset_in_progress;
50 /* 0x00a20 */ u64 mxp_cmds_reset_in_progress;
52 /* 0x00a28 */ u64 noffload_reset_in_progress;
54 /* 0x00a30 */ u64 rd_req_in_progress;
56 /* 0x00a38 */ u64 rd_req_outstanding;
58 /* 0x00a40 */ u64 kdfc_reset_in_progress;
62 /* 0x00b00 */ u64 one_cfg_v
[all...]
H A Dvxgehal-srpcim-reg.h40 /* 0x00000 */ u64 tim_mr2sr_resource_assignment_vh;
45 /* 0x00100 */ u64 srpcim_pcipif_int_status;
50 /* 0x00108 */ u64 srpcim_pcipif_int_mask;
51 /* 0x00110 */ u64 mrpcim_msg_reg;
53 /* 0x00118 */ u64 mrpcim_msg_mask;
54 /* 0x00120 */ u64 mrpcim_msg_alarm;
55 /* 0x00128 */ u64 vpath_msg_reg;
73 /* 0x00130 */ u64 vpath_msg_mask;
74 /* 0x00138 */ u64 vpath_msg_alarm;
77 /* 0x00158 */ u64 vf_bargrp_n
[all...]
H A Dvxgehal-toc-reg.h42 /* 0x00050 */ u64 toc_common_pointer;
44 /* 0x00058 */ u64 toc_memrepair_pointer;
46 /* 0x00060 */ u64 toc_pcicfgmgmt_pointer[17];
50 /* 0x001e0 */ u64 toc_mrpcim_pointer;
52 /* 0x001e8 */ u64 toc_srpcim_pointer[17];
56 /* 0x00278 */ u64 toc_vpmgmt_pointer[17];
60 /* 0x00390 */ u64 toc_vpath_pointer[17];
64 /* 0x004a0 */ u64 toc_kdfc;
67 /* 0x004a8 */ u64 toc_usdc;
70 /* 0x004b0 */ u64 toc_kdfc_vpath_strid
[all...]
H A Dvxgehal-vpath-reg.h42 /* 0x00300 */ u64 usdc_vpath;
46 /* 0x00a00 */ u64 wrdma_alarm_status;
48 /* 0x00a08 */ u64 wrdma_alarm_mask;
51 /* 0x00a30 */ u64 prc_alarm_reg;
56 /* 0x00a38 */ u64 prc_alarm_mask;
57 /* 0x00a40 */ u64 prc_alarm_alarm;
58 /* 0x00a48 */ u64 prc_cfg1;
68 /* 0x00a60 */ u64 prc_cfg4;
78 /* 0x00a68 */ u64 prc_cfg5;
80 /* 0x00a70 */ u64 prc_cfg
[all...]
H A Dvxgehal-vpmgmt-reg.h40 /* 0x00000 */ u64 one_cfg_sr_rdy;
42 /* 0x00008 */ u64 sgrp_own;
46 /* 0x00040 */ u64 vpath_to_func_map_cfg1;
49 /* 0x00048 */ u64 vpath_is_first;
51 /* 0x00050 */ u64 srpcim_to_vpath_wmsg;
54 /* 0x00058 */ u64 srpcim_to_vpath_wmsg_trig;
58 /* 0x00100 */ u64 tim_vpath_assignment;
62 /* 0x00140 */ u64 rqa_top_prty_for_vp;
66 /* 0x00180 */ u64 usdc_vpath_own;
70 /* 0x001c0 */ u64 rxmac_rx_pa_cfg0_vpmgmt_clon
[all...]
/freebsd-10.0-release/sys/dev/nxge/include/
H A Dxgehal-stats.h416 u64 tmac_drop_frms;
419 u64 tmac_pause_ctrl_frms;
424 u64 tmac_ttl_less_fb_octets;
425 u64 tmac_vld_ip_octets;
430 u64 tmac_tcp;
437 u64 rmac_fcs_err_frms;
438 u64 rmac_drop_frms;
443 u64 rmac_long_frms;
444 u64 rmac_pause_ctrl_frms;
445 u64 rmac_unsup_ctrl_frm
[all...]
H A Dxgehal-regs.h37 u64 general_int_status;
59 u64 general_int_mask;
63 u64 sw_reset;
85 u64 adapter_status;
103 u64 adapter_control;
111 u64 serr_source;
125 u64 pci_info;
131 u64 ric_status;
135 u64 mbist_status;
140 u64 pic_int_statu
[all...]
/freebsd-10.0-release/sys/contrib/octeon-sdk/
H A Dcvmx-gpio.h78 multi_cast.u64 = cvmx_read_csr(CVMX_GPIO_MULTI_CAST);
79 gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(core));
87 ciu_sum0.u64 = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core * 2));
89 cvmx_write_csr(CVMX_CIU_INTX_SUM0(core * 2), ciu_sum0.u64);
98 gpio_int_clr.u64 = 0;
100 cvmx_write_csr(CVMX_GPIO_INT_CLR, gpio_int_clr.u64);
118 gpio_xbit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(bit));
123 cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(bit), gpio_xbit.u64);
131 gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(bit));
136 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), gpio_bit.u64);
[all...]
H A Dcvmx-ilk.c178 mio_qlmx_cfg.u64 = cvmx_read_csr (CVMX_MIO_QLMX_CFG(this_qlm));
179 other_mio_qlmx_cfg.u64 = cvmx_read_csr (CVMX_MIO_QLMX_CFG(other_qlm));
190 ilk_ser_cfg.u64 = cvmx_read_csr (CVMX_ILK_SER_CFG);
201 cvmx_write_csr (CVMX_ILK_SER_CFG, ilk_ser_cfg.u64);
204 ilk_txx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_TXX_CFG0(interface));
205 ilk_rxx_cfg0.u64 = cvmx_read_csr (CVMX_ILK_RXX_CFG0(interface));
207 cvmx_write_csr (CVMX_ILK_TXX_CFG0(interface), ilk_txx_cfg0.u64);
208 cvmx_write_csr (CVMX_ILK_RXX_CFG0(interface), ilk_rxx_cfg0.u64);
253 ilk_txx_pipe.u64 = cvmx_read_csr (CVMX_ILK_TXX_PIPE(interface));
256 cvmx_write_csr (CVMX_ILK_TXX_PIPE(interface), ilk_txx_pipe.u64);
[all...]
H A Dcvmx-dfa.c77 control.u64 = 0;
82 cvmx_write_csr(CVMX_DFA_DIFCTL, control.u64);
86 initial_state.u64 = 0;
88 cvmx_fau_atomic_write64(CVMX_FAU_DFA_STATE, initial_state.u64);
107 final_state.u64 = cvmx_fau_fetch_and_add64(CVMX_FAU_DFA_STATE, 0);
118 final_state.u64 = 0;
119 cvmx_fau_atomic_write64(CVMX_FAU_DFA_STATE, final_state.u64);
H A Dcvmx-ipd.h122 first_skip.u64 = 0;
124 cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64);
126 not_first_skip.u64 = 0;
128 cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64);
130 size.u64 = 0;
132 cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64);
134 first_back_struct.u64 = 0;
136 cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64);
138 second_back_struct.u64 = 0;
140 cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK,second_back_struct.u64);
[all...]
H A Dcvmx-zip.c77 zip_cmd_buf.u64 = 0;
82 cvmx_write_csr(CVMX_ZIP_CMD_BUF, zip_cmd_buf.u64);
118 zip_que_buf.u64 = 0;
123 cvmx_write_csr(CVMX_ZIP_QUEX_BUF(queue), zip_que_buf.u64);
126 que_map.u64 = cvmx_read_csr(CVMX_ZIP_QUEX_MAP(queue));
128 cvmx_write_csr(CVMX_ZIP_QUEX_MAP(queue), que_map.u64);
131 que_ena.u64 = cvmx_read_csr(CVMX_ZIP_QUE_ENA);
133 cvmx_write_csr(CVMX_ZIP_QUE_ENA, que_ena.u64);
138 int_reg.u64 = cvmx_read_csr(CVMX_ZIP_INT_REG);
144 cvmx_write_csr(CVMX_ZIP_INT_REG, int_reg.u64);
[all...]
H A Dcvmx-ipd.c96 ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
101 ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
109 ipd_wqe_ptr_valid.u64 = cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID);
120 ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
124 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
125 ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
132 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
138 ipd_pkt_ptr_valid.u64 = cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID);
146 ipd_prc_port_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
151 cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, ipd_prc_port_ptr_fifo_ctl.u64);
[all...]
H A Dcvmx-crypto.c61 cvmx_write_csr(CVMX_RNM_EER_KEY, v.u64);
74 dbg.u64 = cvmx_read_csr(CVMX_RNM_EER_DBG);
H A Dcvmx-gmx.h83 gmxx_tx_ovr_bp.u64 = 0;
86 cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmxx_tx_ovr_bp.u64);
H A Dcvmx-helper-xaui.c93 gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
119 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM2);
123 cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64);
133 mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
138 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM2);
142 cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64);
161 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
163 cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
175 pko_mem_port_ptrs.u64 = 0;
183 cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
[all...]
/freebsd-10.0-release/tools/tools/nxge/
H A Dxge_cmn.h49 #define u64 unsigned long long macro
81 u64 offset;
82 u64 value;
89 u64 offset; /* Offset from base address */
90 u64 value; /* Value */
98 u64 be_offset; /* Offset from base address (BE) */
99 u64 le_offset; /* Offset from base address (LE) */
101 u64 value; /* Value */
108 u64 be_offset; /* Offset from base address (BE) */
109 u64 le_offse
[all...]
/freebsd-10.0-release/sys/ofed/drivers/net/mlx4/
H A Dfw.h74 u64 def_mac[MLX4_MAX_PORTS + 1];
79 u64 trans_code[MLX4_MAX_PORTS + 1];
83 u64 flags;
84 u64 flags2;
114 u64 max_icm_sz;
154 u64 qpc_base;
155 u64 rdmarc_base;
156 u64 auxc_base;
157 u64 altc_base;
158 u64 srqc_bas
[all...]
/freebsd-10.0-release/sys/dev/cxgbe/common/
H A Dcommon.h76 u64 tx_octets; /* total # of octets in good frames */
77 u64 tx_frames; /* all good frames */
78 u64 tx_bcast_frames; /* all broadcast frames */
79 u64 tx_mcast_frames; /* all multicast frames */
80 u64 tx_ucast_frames; /* all unicast frames */
81 u64 tx_error_frames; /* all error frames */
83 u64 tx_frames_64; /* # of Tx frames in a particular range */
84 u64 tx_frames_65_127;
85 u64 tx_frames_128_255;
86 u64 tx_frames_256_51
[all...]
/freebsd-10.0-release/sys/dev/ixgbe/
H A Dixgbe_vf.h90 u64 base_vfgprc;
91 u64 base_vfgptc;
92 u64 base_vfgorc;
93 u64 base_vfgotc;
94 u64 base_vfmprc;
96 u64 last_vfgprc;
97 u64 last_vfgptc;
98 u64 last_vfgorc;
99 u64 last_vfgotc;
100 u64 last_vfmpr
[all...]
/freebsd-10.0-release/sys/dev/vxge/include/
H A Dvxge-defs.h62 #define vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz)))
68 #define bVAL1(bits, loc) ((((u64)bits) >> (64-(loc+1))) & 0x1)
69 #define bVAL2(bits, loc) ((((u64)bits) >> (64-(loc+2))) & 0x3)
70 #define bVAL3(bits, loc) ((((u64)bits) >> (64-(loc+3))) & 0x7)
71 #define bVAL4(bits, loc) ((((u64)bits) >> (64-(loc+4))) & 0xF)
72 #define bVAL5(bits, loc) ((((u64)bits) >> (64-(loc+5))) & 0x1F)
73 #define bVAL6(bits, loc) ((((u64)bits) >> (64-(loc+6))) & 0x3F)
74 #define bVAL7(bits, loc) ((((u64)bits) >> (64-(loc+7))) & 0x7F)
75 #define bVAL8(bits, loc) ((((u64)bits) >> (64-(loc+8))) & 0xFF)
76 #define bVAL9(bits, loc) ((((u64)bit
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