1210284Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3215990Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions are 8215990Sjmallett * met: 9210284Sjmallett * 10215990Sjmallett * * Redistributions of source code must retain the above copyright 11215990Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13215990Sjmallett * * Redistributions in binary form must reproduce the above 14215990Sjmallett * copyright notice, this list of conditions and the following 15215990Sjmallett * disclaimer in the documentation and/or other materials provided 16215990Sjmallett * with the distribution. 17215990Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215990Sjmallett * its contributors may be used to endorse or promote products 20215990Sjmallett * derived from this software without specific prior written 21215990Sjmallett * permission. 22215990Sjmallett 23215990Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215990Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215990Sjmallett * regulations, and may be subject to export or import regulations in other 26215990Sjmallett * countries. 27215990Sjmallett 28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38210284Sjmallett ***********************license end**************************************/ 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett 45215990Sjmallett 46210284Sjmallett/** 47210284Sjmallett * @file 48210284Sjmallett * 49210284Sjmallett * General Purpose IO interface. 50210284Sjmallett * 51232812Sjmallett * <hr>$Revision: 70030 $<hr> 52210284Sjmallett */ 53210284Sjmallett 54210284Sjmallett#ifndef __CVMX_GPIO_H__ 55210284Sjmallett#define __CVMX_GPIO_H__ 56210284Sjmallett 57210284Sjmallett#ifdef __cplusplus 58210284Sjmallettextern "C" { 59210284Sjmallett#endif 60210284Sjmallett 61215990Sjmallett/* CSR typedefs have been moved to cvmx-gpio-defs.h */ 62210284Sjmallett 63210284Sjmallett/** 64210284Sjmallett * Clear the interrupt rising edge detector for the supplied 65210284Sjmallett * pins in the mask. Chips which have more than 16 GPIO pins 66210284Sjmallett * can't use them for interrupts. 67232812Sjmallett e 68210284Sjmallett * @param clear_mask Mask of pins to clear 69210284Sjmallett */ 70210284Sjmallettstatic inline void cvmx_gpio_interrupt_clear(uint16_t clear_mask) 71210284Sjmallett{ 72232812Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN61XX)) 73232812Sjmallett { 74232812Sjmallett cvmx_gpio_multi_cast_t multi_cast; 75232812Sjmallett cvmx_gpio_bit_cfgx_t gpio_bit; 76232812Sjmallett int core = cvmx_get_core_num(); 77232812Sjmallett 78232812Sjmallett multi_cast.u64 = cvmx_read_csr(CVMX_GPIO_MULTI_CAST); 79232812Sjmallett gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(core)); 80232812Sjmallett 81232812Sjmallett /* If Multicast mode is enabled, and GPIO interrupt is enabled for 82232812Sjmallett edge detection, then GPIO<4..7> interrupts are per core */ 83232812Sjmallett if (multi_cast.s.en && gpio_bit.s.int_en && gpio_bit.s.int_type) 84232812Sjmallett { 85232812Sjmallett /* Clear GPIO<4..7> per core */ 86232812Sjmallett cvmx_ciu_intx_sum0_t ciu_sum0; 87232812Sjmallett ciu_sum0.u64 = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core * 2)); 88232812Sjmallett ciu_sum0.s.gpio = clear_mask & 0xf0; 89232812Sjmallett cvmx_write_csr(CVMX_CIU_INTX_SUM0(core * 2), ciu_sum0.u64); 90232812Sjmallett 91232812Sjmallett /* Clear other GPIO pins for all cores. */ 92232812Sjmallett cvmx_write_csr(CVMX_GPIO_INT_CLR, (clear_mask & ~0xf0)); 93232812Sjmallett return; 94232812Sjmallett } 95232812Sjmallett } 96232812Sjmallett /* Clear GPIO pins state across all cores and common interrupt states. */ 97210284Sjmallett cvmx_gpio_int_clr_t gpio_int_clr; 98210284Sjmallett gpio_int_clr.u64 = 0; 99210284Sjmallett gpio_int_clr.s.type = clear_mask; 100210284Sjmallett cvmx_write_csr(CVMX_GPIO_INT_CLR, gpio_int_clr.u64); 101210284Sjmallett} 102210284Sjmallett 103232812Sjmallett/** 104232812Sjmallett * GPIO Output Pin 105232812Sjmallett * 106232812Sjmallett * @param bit The GPIO to use 107232812Sjmallett * @param mode Drive GPIO as output pin or not. 108232812Sjmallett * 109232812Sjmallett */ 110232812Sjmallettstatic inline void cvmx_gpio_cfg(int bit, int mode) 111232812Sjmallett{ 112232812Sjmallett if (bit > 15 && bit < 20) 113232812Sjmallett { 114232812Sjmallett /* CN61XX/CN66XX has 20 GPIO pins and only 16 are interruptable. */ 115232812Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)) 116232812Sjmallett { 117232812Sjmallett cvmx_gpio_xbit_cfgx_t gpio_xbit; 118232812Sjmallett gpio_xbit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(bit)); 119232812Sjmallett if (mode) 120232812Sjmallett gpio_xbit.s.tx_oe = 1; 121232812Sjmallett else 122232812Sjmallett gpio_xbit.s.tx_oe = 0; 123232812Sjmallett cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(bit), gpio_xbit.u64); 124232812Sjmallett } 125232812Sjmallett else 126232812Sjmallett cvmx_dprintf("cvmx_gpio_cfg: Invalid GPIO bit(%d)\n", bit); 127232812Sjmallett } 128232812Sjmallett else 129232812Sjmallett { 130232812Sjmallett cvmx_gpio_bit_cfgx_t gpio_bit; 131232812Sjmallett gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(bit)); 132232812Sjmallett if (mode) 133232812Sjmallett gpio_bit.s.tx_oe = 1; 134232812Sjmallett else 135232812Sjmallett gpio_bit.s.tx_oe = 0; 136232812Sjmallett cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), gpio_bit.u64); 137232812Sjmallett } 138232812Sjmallett} 139210284Sjmallett 140210284Sjmallett/** 141210284Sjmallett * GPIO Read Data 142210284Sjmallett * 143210284Sjmallett * @return Status of the GPIO pins 144210284Sjmallett */ 145210284Sjmallettstatic inline uint32_t cvmx_gpio_read(void) 146210284Sjmallett{ 147210284Sjmallett cvmx_gpio_rx_dat_t gpio_rx_dat; 148210284Sjmallett gpio_rx_dat.u64 = cvmx_read_csr(CVMX_GPIO_RX_DAT); 149210284Sjmallett return gpio_rx_dat.s.dat; 150210284Sjmallett} 151210284Sjmallett 152210284Sjmallett 153210284Sjmallett/** 154210284Sjmallett * GPIO Clear pin 155210284Sjmallett * 156210284Sjmallett * @param clear_mask Bit mask to indicate which bits to drive to '0'. 157210284Sjmallett */ 158210284Sjmallettstatic inline void cvmx_gpio_clear(uint32_t clear_mask) 159210284Sjmallett{ 160210284Sjmallett cvmx_gpio_tx_clr_t gpio_tx_clr; 161210284Sjmallett gpio_tx_clr.u64 = 0; 162210284Sjmallett gpio_tx_clr.s.clr = clear_mask; 163210284Sjmallett cvmx_write_csr(CVMX_GPIO_TX_CLR, gpio_tx_clr.u64); 164210284Sjmallett} 165210284Sjmallett 166210284Sjmallett 167210284Sjmallett/** 168210284Sjmallett * GPIO Set pin 169210284Sjmallett * 170210284Sjmallett * @param set_mask Bit mask to indicate which bits to drive to '1'. 171210284Sjmallett */ 172210284Sjmallettstatic inline void cvmx_gpio_set(uint32_t set_mask) 173210284Sjmallett{ 174210284Sjmallett cvmx_gpio_tx_set_t gpio_tx_set; 175210284Sjmallett gpio_tx_set.u64 = 0; 176210284Sjmallett gpio_tx_set.s.set = set_mask; 177210284Sjmallett cvmx_write_csr(CVMX_GPIO_TX_SET, gpio_tx_set.u64); 178210284Sjmallett} 179210284Sjmallett 180210284Sjmallett#ifdef __cplusplus 181210284Sjmallett} 182210284Sjmallett#endif 183210284Sjmallett 184210284Sjmallett#endif 185210284Sjmallett 186