1181834Sroberto/*- 2181834Sroberto * Copyright(c) 2002-2011 Exar Corp. 3285612Sdelphij * All rights reserved. 4285612Sdelphij * 5285612Sdelphij * Redistribution and use in source and binary forms, with or without 6285612Sdelphij * modification are permitted provided the following conditions are met: 7285612Sdelphij * 8285612Sdelphij * 1. Redistributions of source code must retain the above copyright notice, 9285612Sdelphij * this list of conditions and the following disclaimer. 10181834Sroberto * 11181834Sroberto * 2. Redistributions in binary form must reproduce the above copyright 12181834Sroberto * notice, this list of conditions and the following disclaimer in the 13181834Sroberto * documentation and/or other materials provided with the distribution. 14285612Sdelphij * 15181834Sroberto * 3. Neither the name of the Exar Corporation nor the names of its 16181834Sroberto * contributors may be used to endorse or promote products derived from 17181834Sroberto * this software without specific prior written permission. 18181834Sroberto * 19181834Sroberto * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20181834Sroberto * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21181834Sroberto * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22181834Sroberto * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23181834Sroberto * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24181834Sroberto * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25285612Sdelphij * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26181834Sroberto * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27181834Sroberto * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28181834Sroberto * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29181834Sroberto * POSSIBILITY OF SUCH DAMAGE. 30181834Sroberto */ 31181834Sroberto/*$FreeBSD$*/ 32181834Sroberto 33181834Sroberto#ifndef VXGE_HAL_VPATH_REGS_H 34181834Sroberto#define VXGE_HAL_VPATH_REGS_H 35181834Sroberto 36181834Sroberto__EXTERN_BEGIN_DECLS 37181834Sroberto 38181834Srobertotypedef struct vxge_hal_vpath_reg_t { 39181834Sroberto 40181834Sroberto u8 unused00300[0x00300]; 41181834Sroberto 42181834Sroberto/* 0x00300 */ u64 usdc_vpath; 43181834Sroberto#define VXGE_HAL_USDC_VPATH_SGRP_ASSIGN(val) vBIT(val, 0, 32) 44181834Sroberto u8 unused00a00[0x00a00 - 0x00308]; 45181834Sroberto 46181834Sroberto/* 0x00a00 */ u64 wrdma_alarm_status; 47181834Sroberto#define VXGE_HAL_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT mBIT(1) 48181834Sroberto/* 0x00a08 */ u64 wrdma_alarm_mask; 49181834Sroberto u8 unused00a30[0x00a30 - 0x00a10]; 50181834Sroberto 51181834Sroberto/* 0x00a30 */ u64 prc_alarm_reg; 52181834Sroberto#define VXGE_HAL_PRC_ALARM_REG_PRC_RING_BUMP mBIT(0) 53181834Sroberto#define VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ERR mBIT(1) 54181834Sroberto#define VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT mBIT(2) 55181834Sroberto#define VXGE_HAL_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR mBIT(3) 56181834Sroberto/* 0x00a38 */ u64 prc_alarm_mask; 57181834Sroberto/* 0x00a40 */ u64 prc_alarm_alarm; 58181834Sroberto/* 0x00a48 */ u64 prc_cfg1; 59181834Sroberto#define VXGE_HAL_PRC_CFG1_RX_TIMER_VAL(val) vBIT(val, 3, 29) 60181834Sroberto#define VXGE_HAL_PRC_CFG1_TIM_RING_BUMP_INT_ENABLE mBIT(34) 61181834Sroberto#define VXGE_HAL_PRC_CFG1_RTI_TINT_DISABLE mBIT(35) 62181834Sroberto#define VXGE_HAL_PRC_CFG1_GREEDY_RETURN mBIT(36) 63181834Sroberto#define VXGE_HAL_PRC_CFG1_QUICK_SHOT mBIT(37) 64181834Sroberto#define VXGE_HAL_PRC_CFG1_RX_TIMER_CI mBIT(39) 65181834Sroberto#define VXGE_HAL_PRC_CFG1_RESET_TIMER_ON_RXD_RET(val) vBIT(val, 40, 2) 66181834Sroberto u8 unused00a60[0x00a60 - 0x00a50]; 67181834Sroberto 68181834Sroberto/* 0x00a60 */ u64 prc_cfg4; 69181834Sroberto#define VXGE_HAL_PRC_CFG4_IN_SVC mBIT(7) 70181834Sroberto#define VXGE_HAL_PRC_CFG4_RING_MODE(val) vBIT(val, 14, 2) 71181834Sroberto#define VXGE_HAL_PRC_CFG4_RXD_NO_SNOOP mBIT(22) 72285612Sdelphij#define VXGE_HAL_PRC_CFG4_FRM_NO_SNOOP mBIT(23) 73181834Sroberto#define VXGE_HAL_PRC_CFG4_RTH_DISABLE mBIT(31) 74181834Sroberto#define VXGE_HAL_PRC_CFG4_IGNORE_OWNERSHIP mBIT(32) 75181834Sroberto#define VXGE_HAL_PRC_CFG4_SIGNAL_BENIGN_OVFLW mBIT(36) 76181834Sroberto#define VXGE_HAL_PRC_CFG4_BIMODAL_INTERRUPT mBIT(37) 77181834Sroberto#define VXGE_HAL_PRC_CFG4_BACKOFF_INTERVAL(val) vBIT(val, 40, 24) 78181834Sroberto/* 0x00a68 */ u64 prc_cfg5; 79181834Sroberto#define VXGE_HAL_PRC_CFG5_RXD0_ADD(val) vBIT(val, 0, 61) 80181834Sroberto/* 0x00a70 */ u64 prc_cfg6; 81181834Sroberto#define VXGE_HAL_PRC_CFG6_FRM_PAD_EN mBIT(0) 82181834Sroberto#define VXGE_HAL_PRC_CFG6_QSIZE_ALIGNED_RXD mBIT(2) 83181834Sroberto#define VXGE_HAL_PRC_CFG6_DOORBELL_MODE_EN mBIT(5) 84181834Sroberto#define VXGE_HAL_PRC_CFG6_L3_CPC_TRSFR_CODE_EN mBIT(8) 85181834Sroberto#define VXGE_HAL_PRC_CFG6_L4_CPC_TRSFR_CODE_EN mBIT(9) 86285612Sdelphij#define VXGE_HAL_PRC_CFG6_RXD_CRXDT(val) vBIT(val, 23, 9) 87181834Sroberto#define VXGE_HAL_PRC_CFG6_RXD_SPAT(val) vBIT(val, 36, 9) 88181834Sroberto/* 0x00a78 */ u64 prc_cfg7; 89285612Sdelphij#define VXGE_HAL_PRC_CFG7_SCATTER_MODE(val) vBIT(val, 6, 2) 90285612Sdelphij#define VXGE_HAL_PRC_CFG7_SMART_SCAT_EN mBIT(11) 91285612Sdelphij#define VXGE_HAL_PRC_CFG7_RXD_NS_CHG_EN mBIT(12) 92181834Sroberto#define VXGE_HAL_PRC_CFG7_NO_HDR_SEPARATION mBIT(14) 93181834Sroberto#define VXGE_HAL_PRC_CFG7_RXD_BUFF_SIZE_MASK(val) vBIT(val, 20, 4) 94181834Sroberto#define VXGE_HAL_PRC_CFG7_BUFF_SIZE0_MASK(val) vBIT(val, 27, 5) 95181834Sroberto/* 0x00a80 */ u64 tim_dest_addr; 96181834Sroberto#define VXGE_HAL_TIM_DEST_ADDR_TIM_DEST_ADDR(val) vBIT(val, 0, 64) 97181834Sroberto/* 0x00a88 */ u64 prc_rxd_doorbell; 98181834Sroberto#define VXGE_HAL_PRC_RXD_DOORBELL_NEW_QW_CNT(val) vBIT(val, 48, 16) 99285612Sdelphij/* 0x00a90 */ u64 rqa_prty_for_vp; 100181834Sroberto#define VXGE_HAL_RQA_PRTY_FOR_VP_RQA_PRTY_FOR_VP(val) vBIT(val, 59, 5) 101181834Sroberto/* 0x00a98 */ u64 rxdmem_size; 102181834Sroberto#define VXGE_HAL_RXDMEM_SIZE_PRC_RXDMEM_SIZE(val) vBIT(val, 51, 13) 103285612Sdelphij/* 0x00aa0 */ u64 frm_in_progress_cnt; 104181834Sroberto#define VXGE_HAL_FRM_IN_PROGRESS_CNT_PRC_FRM_IN_PROGRESS_CNT(val)\ 105285612Sdelphij vBIT(val, 59, 5) 106181834Sroberto/* 0x00aa8 */ u64 rx_multi_cast_stats; 107285612Sdelphij#define VXGE_HAL_RX_MULTI_CAST_STATS_FRAME_DISCARD(val) vBIT(val, 48, 16) 108181834Sroberto/* 0x00ab0 */ u64 rx_frm_transferred; 109285612Sdelphij#define VXGE_HAL_RX_FRM_TRANSFERRED_RX_FRM_TRANSFERRED(val) vBIT(val, 32, 32) 110181834Sroberto/* 0x00ab8 */ u64 rxd_returned; 111181834Sroberto#define VXGE_HAL_RXD_RETURNED_RXD_RETURNED(val) vBIT(val, 48, 16) 112285612Sdelphij u8 unused00c00[0x00c00 - 0x00ac0]; 113181834Sroberto 114181834Sroberto/* 0x00c00 */ u64 kdfc_fifo_trpl_partition; 115181834Sroberto#define VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(val) vBIT(val, 17, 15) 116181834Sroberto#define VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_1(val) vBIT(val, 33, 15) 117181834Sroberto#define VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_2(val) vBIT(val, 49, 15) 118285612Sdelphij/* 0x00c08 */ u64 kdfc_fifo_trpl_ctrl; 119285612Sdelphij#define VXGE_HAL_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE mBIT(7) 120285612Sdelphij/* 0x00c10 */ u64 kdfc_trpl_fifo_0_ctrl; 121181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE(val) vBIT(val, 14, 2) 122285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_FLIP_EN mBIT(22) 123285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN mBIT(23) 124285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_INT_CTRL(val) vBIT(val, 26, 2) 125285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_CTRL_STRUC mBIT(28) 126285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_ADD_PAD mBIT(29) 127285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_NO_SNOOP mBIT(30) 128285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_RLX_ORD mBIT(31) 129285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_SELECT(val) vBIT(val, 32, 8) 130285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_INT_NO(val) vBIT(val, 41, 7) 131285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_BIT_MAP(val) vBIT(val, 48, 16) 132181834Sroberto/* 0x00c18 */ u64 kdfc_trpl_fifo_1_ctrl; 133181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE(val) vBIT(val, 14, 2) 134181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_FLIP_EN mBIT(22) 135181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_SWAP_EN mBIT(23) 136285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_INT_CTRL(val) vBIT(val, 26, 2) 137181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_CTRL_STRUC mBIT(28) 138181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_ADD_PAD mBIT(29) 139181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_NO_SNOOP mBIT(30) 140181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_RLX_ORD mBIT(31) 141285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_SELECT(val) vBIT(val, 32, 8) 142181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_INT_NO(val) vBIT(val, 41, 7) 143181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_BIT_MAP(val) vBIT(val, 48, 16) 144285612Sdelphij/* 0x00c20 */ u64 kdfc_trpl_fifo_2_ctrl; 145181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_FLIP_EN mBIT(22) 146285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_SWAP_EN mBIT(23) 147181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_INT_CTRL(val) vBIT(val, 26, 2) 148285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_CTRL_STRUC mBIT(28) 149181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_ADD_PAD mBIT(29) 150285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_NO_SNOOP mBIT(30) 151285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_RLX_ORD mBIT(31) 152285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_SELECT(val) vBIT(val, 32, 8) 153285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_INT_NO(val) vBIT(val, 41, 7) 154285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_BIT_MAP(val) vBIT(val, 48, 16) 155181834Sroberto/* 0x00c28 */ u64 kdfc_trpl_fifo_0_wb_address; 156181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_0_WB_ADDRESS_ADD(val) vBIT(val, 0, 64) 157181834Sroberto/* 0x00c30 */ u64 kdfc_trpl_fifo_1_wb_address; 158181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_1_WB_ADDRESS_ADD(val) vBIT(val, 0, 64) 159181834Sroberto/* 0x00c38 */ u64 kdfc_trpl_fifo_2_wb_address; 160181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_2_WB_ADDRESS_ADD(val) vBIT(val, 0, 64) 161181834Sroberto/* 0x00c40 */ u64 kdfc_trpl_fifo_offset; 162285612Sdelphij#define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR0(val) vBIT(val, 1, 15) 163181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR1(val) vBIT(val, 17, 15) 164181834Sroberto#define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR2(val) vBIT(val, 33, 15) 165181834Sroberto/* 0x00c48 */ u64 kdfc_drbl_triplet_total; 166181834Sroberto#define VXGE_HAL_KDFC_DRBL_TRIPLET_TOTAL_KDFC_MAX_SIZE(val) vBIT(val, 17, 15) 167285612Sdelphij u8 unused00c60[0x00c60 - 0x00c50]; 168285612Sdelphij 169285612Sdelphij/* 0x00c60 */ u64 usdc_drbl_ctrl; 170285612Sdelphij#define VXGE_HAL_USDC_DRBL_CTRL_FLIP_EN mBIT(22) 171285612Sdelphij#define VXGE_HAL_USDC_DRBL_CTRL_SWAP_EN mBIT(23) 172181834Sroberto/* 0x00c68 */ u64 usdc_vp_ready; 173181834Sroberto#define VXGE_HAL_USDC_VP_READY_USDC_HTN_READY mBIT(7) 174181834Sroberto#define VXGE_HAL_USDC_VP_READY_USDC_SRQ_READY mBIT(15) 175181834Sroberto#define VXGE_HAL_USDC_VP_READY_USDC_CQRQ_READY mBIT(23) 176181834Sroberto/* 0x00c70 */ u64 kdfc_status; 177181834Sroberto#define VXGE_HAL_KDFC_STATUS_KDFC_WRR_0_READY mBIT(0) 178181834Sroberto#define VXGE_HAL_KDFC_STATUS_KDFC_WRR_1_READY mBIT(1) 179181834Sroberto#define VXGE_HAL_KDFC_STATUS_KDFC_WRR_2_READY mBIT(2) 180181834Sroberto u8 unused00c80[0x00c80 - 0x00c78]; 181181834Sroberto 182285612Sdelphij/* 0x00c80 */ u64 xmac_rpa_vcfg; 183181834Sroberto#define VXGE_HAL_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH mBIT(3) 184181834Sroberto#define VXGE_HAL_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH mBIT(7) 185285612Sdelphij#define VXGE_HAL_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH mBIT(11) 186181834Sroberto#define VXGE_HAL_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH mBIT(15) 187181834Sroberto#define VXGE_HAL_XMAC_RPA_VCFG_L4_INCL_CF mBIT(19) 188181834Sroberto#define VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG mBIT(23) 189181834Sroberto/* 0x00c88 */ u64 rxmac_vcfg0; 190181834Sroberto#define VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(val) vBIT(val, 2, 14) 191181834Sroberto#define VXGE_HAL_RXMAC_VCFG0_RTS_USE_MIN_LEN mBIT(19) 192181834Sroberto#define VXGE_HAL_RXMAC_VCFG0_RTS_MIN_FRM_LEN(val) vBIT(val, 26, 14) 193181834Sroberto#define VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN mBIT(43) 194181834Sroberto#define VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN mBIT(47) 195181834Sroberto#define VXGE_HAL_RXMAC_VCFG0_BCAST_EN mBIT(51) 196181834Sroberto#define VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN mBIT(55) 197181834Sroberto/* 0x00c90 */ u64 rxmac_vcfg1; 198181834Sroberto#define VXGE_HAL_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(val) vBIT(val, 42, 2) 199285612Sdelphij#define VXGE_HAL_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE mBIT(47) 200181834Sroberto#define VXGE_HAL_RXMAC_VCFG1_CONTRIB_L2_FLOW mBIT(51) 201181834Sroberto/* 0x00c98 */ u64 rts_access_steer_ctrl; 202181834Sroberto#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(val) vBIT(val, 1, 7) 203181834Sroberto#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(val) vBIT(val, 8, 4) 204181834Sroberto#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE mBIT(15) 205181834Sroberto#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_BEHAV_TBL_SEL mBIT(23) 206181834Sroberto#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_TABLE_SEL mBIT(27) 207285612Sdelphij#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(val) vBIT(val, 40, 8) 208181834Sroberto#define VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS mBIT(0) 209285612Sdelphij/* 0x00ca0 */ u64 rts_access_steer_data0; 210285612Sdelphij#define VXGE_HAL_RTS_ACCESS_STEER_DATA0_DATA(val) vBIT(val, 0, 64) 211285612Sdelphij/* 0x00ca8 */ u64 rts_access_steer_data1; 212285612Sdelphij#define VXGE_HAL_RTS_ACCESS_STEER_DATA1_DATA(val) vBIT(val, 0, 64) 213181834Sroberto u8 unused00d00[0x00d00 - 0x00cb0]; 214181834Sroberto 215181834Sroberto/* 0x00d00 */ u64 xmac_vsport_choice; 216181834Sroberto#define VXGE_HAL_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(val) vBIT(val, 3, 5) 217181834Sroberto/* 0x00d08 */ u64 xmac_stats_cfg; 218181834Sroberto/* 0x00d10 */ u64 xmac_stats_access_cmd; 219181834Sroberto#define VXGE_HAL_XMAC_STATS_ACCESS_CMD_OP(val) vBIT(val, 6, 2) 220181834Sroberto#define VXGE_HAL_XMAC_STATS_ACCESS_CMD_STROBE mBIT(15) 221181834Sroberto#define VXGE_HAL_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(val) vBIT(val, 32, 8) 222285612Sdelphij/* 0x00d18 */ u64 xmac_stats_access_data; 223285612Sdelphij#define VXGE_HAL_XMAC_STATS_ACCESS_DATA_XSMGR_DATA(val) vBIT(val, 0, 64) 224285612Sdelphij/* 0x00d20 */ u64 asic_ntwk_vp_ctrl; 225181834Sroberto#define VXGE_HAL_ASIC_NTWK_VP_CTRL_REQ_TEST_NTWK mBIT(3) 226181834Sroberto#define VXGE_HAL_ASIC_NTWK_VP_CTRL_XMACJ_SHOW_PORT_INFO mBIT(55) 227181834Sroberto#define VXGE_HAL_ASIC_NTWK_VP_CTRL_XMACJ_PORT_NUM mBIT(63) 228181834Sroberto u8 unused00d30[0x00d30 - 0x00d28]; 229181834Sroberto 230181834Sroberto/* 0x00d30 */ u64 xgmac_vp_int_status; 231285612Sdelphij#define VXGE_HAL_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_INT mBIT(3) 232181834Sroberto/* 0x00d38 */ u64 xgmac_vp_int_mask; 233181834Sroberto/* 0x00d40 */ u64 asic_ntwk_vp_err_reg; 234181834Sroberto#define VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT mBIT(3) 235181834Sroberto#define VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK mBIT(7) 236181834Sroberto#define VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT_OCCURRED mBIT(11) 237181834Sroberto#define VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK_OCCURRED mBIT(15) 238181834Sroberto#define VXGE_HAL_ASIC_NTWK_VP_ERR_REG_REAF_FAULT mBIT(19) 239181834Sroberto#define VXGE_HAL_ASIC_NTWK_VP_ERR_REG_REAF_OK mBIT(23) 240181834Sroberto/* 0x00d48 */ u64 asic_ntwk_vp_err_mask; 241181834Sroberto/* 0x00d50 */ u64 asic_ntwk_vp_err_alarm; 242181834Sroberto u8 unused00d80[0x00d80 - 0x00d58]; 243285612Sdelphij 244181834Sroberto/* 0x00d80 */ u64 rtdma_bw_ctrl; 245181834Sroberto#define VXGE_HAL_RTDMA_BW_CTRL_BW_CTRL_EN mBIT(39) 246181834Sroberto#define VXGE_HAL_RTDMA_BW_CTRL_DESIRED_BW(val) vBIT(val, 46, 18) 247181834Sroberto/* 0x00d88 */ u64 rtdma_rd_optimization_ctrl; 248181834Sroberto#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_GEN_INT_AFTER_ABORT mBIT(3) 249181834Sroberto#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_PAD_MODE(val) vBIT(val, 6, 2) 250181834Sroberto#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_PAD_PATTERN(val) vBIT(val, 8, 8) 251181834Sroberto#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE mBIT(19) 252181834Sroberto#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val)\ 253181834Sroberto vBIT(val, 21, 3) 254181834Sroberto#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK_EN mBIT(28) 255285612Sdelphij#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK(val)\ 256181834Sroberto vBIT(val, 29, 3) 257181834Sroberto#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN mBIT(35) 258285612Sdelphij#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(val) vBIT(val, 37, 3) 259181834Sroberto#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_WAIT_FOR_SPACE mBIT(43) 260181834Sroberto#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_FILL_THRESH(val)\ 261181834Sroberto vBIT(val, 51, 5) 262181834Sroberto#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY_EN mBIT(59) 263181834Sroberto#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY(val) vBIT(val, 61, 3) 264181834Sroberto/* 0x00d90 */ u64 pda_pcc_job_monitor; 265181834Sroberto#define VXGE_HAL_PDA_PCC_JOB_MONITOR_PDA_PCC_JOB_STATUS mBIT(7) 266181834Sroberto/* 0x00d98 */ u64 tx_protocol_assist_cfg; 267181834Sroberto#define VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN mBIT(6) 268181834Sroberto#define VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING mBIT(7) 269181834Sroberto u8 unused01000[0x01000 - 0x00da0]; 270285612Sdelphij 271181834Sroberto/* 0x01000 */ u64 tim_cfg1_int_num[4]; 272285612Sdelphij#define VXGE_HAL_TIM_CFG1_INT_NUM_BTIMER_VAL(val) vBIT(val, 6, 26) 273181834Sroberto#define VXGE_HAL_TIM_CFG1_INT_NUM_BITMP_EN mBIT(35) 274181834Sroberto#define VXGE_HAL_TIM_CFG1_INT_NUM_TXFRM_CNT_EN mBIT(36) 275181834Sroberto#define VXGE_HAL_TIM_CFG1_INT_NUM_TXD_CNT_EN mBIT(37) 276181834Sroberto#define VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_AC mBIT(38) 277181834Sroberto#define VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI mBIT(39) 278181834Sroberto#define VXGE_HAL_TIM_CFG1_INT_NUM_URNG_A(val) vBIT(val, 41, 7) 279181834Sroberto#define VXGE_HAL_TIM_CFG1_INT_NUM_URNG_B(val) vBIT(val, 49, 7) 280285612Sdelphij#define VXGE_HAL_TIM_CFG1_INT_NUM_URNG_C(val) vBIT(val, 57, 7) 281285612Sdelphij/* 0x01020 */ u64 tim_cfg2_int_num[4]; 282181834Sroberto#define VXGE_HAL_TIM_CFG2_INT_NUM_UEC_A(val) vBIT(val, 0, 16) 283181834Sroberto#define VXGE_HAL_TIM_CFG2_INT_NUM_UEC_B(val) vBIT(val, 16, 16) 284285612Sdelphij#define VXGE_HAL_TIM_CFG2_INT_NUM_UEC_C(val) vBIT(val, 32, 16) 285285612Sdelphij#define VXGE_HAL_TIM_CFG2_INT_NUM_UEC_D(val) vBIT(val, 48, 16) 286285612Sdelphij/* 0x01040 */ u64 tim_cfg3_int_num[4]; 287285612Sdelphij#define VXGE_HAL_TIM_CFG3_INT_NUM_TIMER_RI mBIT(0) 288285612Sdelphij#define VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(val) vBIT(val, 1, 4) 289181834Sroberto#define VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(val) vBIT(val, 6, 26) 290285612Sdelphij#define VXGE_HAL_TIM_CFG3_INT_NUM_UTIL_SEL(val) vBIT(val, 32, 6) 291181834Sroberto#define VXGE_HAL_TIM_CFG3_INT_NUM_LTIMER_VAL(val) vBIT(val, 38, 26) 292285612Sdelphij/* 0x01060 */ u64 tim_wrkld_clc; 293181834Sroberto#define VXGE_HAL_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(val) vBIT(val, 0, 32) 294181834Sroberto#define VXGE_HAL_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(val) vBIT(val, 35, 5) 295181834Sroberto#define VXGE_HAL_TIM_WRKLD_CLC_CNT_FRM_BYTE mBIT(40) 296181834Sroberto#define VXGE_HAL_TIM_WRKLD_CLC_CNT_RX_TX(val) vBIT(val, 41, 2) 297181834Sroberto#define VXGE_HAL_TIM_WRKLD_CLC_CNT_LNK_EN mBIT(43) 298181834Sroberto#define VXGE_HAL_TIM_WRKLD_CLC_HOST_UTIL(val) vBIT(val, 57, 7) 299181834Sroberto/* 0x01068 */ u64 tim_bitmap; 300181834Sroberto#define VXGE_HAL_TIM_BITMAP_MASK(val) vBIT(val, 0, 32) 301181834Sroberto#define VXGE_HAL_TIM_BITMAP_LLROOT_RXD_EN mBIT(32) 302181834Sroberto#define VXGE_HAL_TIM_BITMAP_LLROOT_TXD_EN mBIT(33) 303181834Sroberto/* 0x01070 */ u64 tim_ring_assn; 304181834Sroberto#define VXGE_HAL_TIM_RING_ASSN_INT_NUM(val) vBIT(val, 6, 2) 305181834Sroberto/* 0x01078 */ u64 tim_remap; 306181834Sroberto#define VXGE_HAL_TIM_REMAP_TX_EN mBIT(5) 307181834Sroberto#define VXGE_HAL_TIM_REMAP_RX_EN mBIT(6) 308181834Sroberto#define VXGE_HAL_TIM_REMAP_OFFLOAD_EN mBIT(7) 309285612Sdelphij#define VXGE_HAL_TIM_REMAP_TO_VPATH_NUM(val) vBIT(val, 11, 5) 310285612Sdelphij/* 0x01080 */ u64 tim_vpath_map; 311285612Sdelphij#define VXGE_HAL_TIM_VPATH_MAP_BMAP_ROOT(val) vBIT(val, 0, 32) 312285612Sdelphij/* 0x01088 */ u64 tim_pci_cfg; 313285612Sdelphij#define VXGE_HAL_TIM_PCI_CFG_ADD_PAD mBIT(7) 314285612Sdelphij#define VXGE_HAL_TIM_PCI_CFG_NO_SNOOP mBIT(15) 315181834Sroberto#define VXGE_HAL_TIM_PCI_CFG_RELAXED mBIT(23) 316285612Sdelphij#define VXGE_HAL_TIM_PCI_CFG_CTL_STR mBIT(31) 317285612Sdelphij u8 unused01100[0x01100 - 0x01090]; 318285612Sdelphij 319181834Sroberto/* 0x01100 */ u64 sgrp_assign; 320181834Sroberto#define VXGE_HAL_SGRP_ASSIGN_SGRP_ASSIGN(val) vBIT(val, 0, 64) 321181834Sroberto/* 0x01108 */ u64 sgrp_aoa_and_result; 322181834Sroberto#define VXGE_HAL_SGRP_AOA_AND_RESULT_PET_SGRP_AOA_AND_RESULT(val)\ 323181834Sroberto vBIT(val, 0, 64) 324181834Sroberto/* 0x01110 */ u64 rpe_pci_cfg; 325181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_PAD_LRO_DATA_ENABLE mBIT(7) 326181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_PAD_LRO_HDR_ENABLE mBIT(8) 327181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_PAD_LRO_CQE_ENABLE mBIT(9) 328181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_PAD_NONLL_CQE_ENABLE mBIT(10) 329181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_PAD_BASE_LL_CQE_ENABLE mBIT(11) 330285612Sdelphij#define VXGE_HAL_RPE_PCI_CFG_PAD_LL_CQE_IDATA_ENABLE mBIT(12) 331181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_PAD_CQRQ_IR_ENABLE mBIT(13) 332181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_PAD_CQSQ_IR_ENABLE mBIT(14) 333181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_PAD_CQRR_IR_ENABLE mBIT(15) 334181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_NOSNOOP_DATA mBIT(18) 335181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_NOSNOOP_NONLL_CQE mBIT(19) 336181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_NOSNOOP_LL_CQE mBIT(20) 337181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_NOSNOOP_CQRQ_IR mBIT(21) 338181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_NOSNOOP_CQSQ_IR mBIT(22) 339181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_NOSNOOP_CQRR_IR mBIT(23) 340181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_RELAXED_DATA mBIT(26) 341181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_RELAXED_NONLL_CQE mBIT(27) 342181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_RELAXED_LL_CQE mBIT(28) 343181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_RELAXED_CQRQ_IR mBIT(29) 344285612Sdelphij#define VXGE_HAL_RPE_PCI_CFG_RELAXED_CQSQ_IR mBIT(30) 345181834Sroberto#define VXGE_HAL_RPE_PCI_CFG_RELAXED_CQRR_IR mBIT(31) 346181834Sroberto/* 0x01118 */ u64 rpe_lro_cfg; 347181834Sroberto#define VXGE_HAL_RPE_LRO_CFG_SUPPRESS_LRO_ETH_TRLR mBIT(7) 348181834Sroberto#define VXGE_HAL_RPE_LRO_CFG_ALLOW_LRO_SNAP_SNAPJUMBO_MRG mBIT(11) 349285612Sdelphij#define VXGE_HAL_RPE_LRO_CFG_ALLOW_LRO_LLC_LLCJUMBO_MRG mBIT(15) 350285612Sdelphij#define VXGE_HAL_RPE_LRO_CFG_INCL_ACK_CNT_IN_CQE mBIT(23) 351285612Sdelphij/* 0x01120 */ u64 pe_mr2vp_ack_blk_limit; 352181834Sroberto#define VXGE_HAL_PE_MR2VP_ACK_BLK_LIMIT_BLK_LIMIT(val) vBIT(val, 32, 32) 353285612Sdelphij/* 0x01128 */ u64 pe_mr2vp_rirr_lirr_blk_limit; 354285612Sdelphij#define VXGE_HAL_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_RIRR_BLK_LIMIT(val)\ 355181834Sroberto vBIT(val, 0, 32) 356285612Sdelphij#define VXGE_HAL_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_LIRR_BLK_LIMIT(val)\ 357285612Sdelphij vBIT(val, 32, 32) 358285612Sdelphij/* 0x01130 */ u64 txpe_pci_nce_cfg; 359285612Sdelphij#define VXGE_HAL_TXPE_PCI_NCE_CFG_NCE_THRESH(val) vBIT(val, 0, 32) 360285612Sdelphij#define VXGE_HAL_TXPE_PCI_NCE_CFG_PAD_TOWI_ENABLE mBIT(55) 361285612Sdelphij#define VXGE_HAL_TXPE_PCI_NCE_CFG_NOSNOOP_TOWI mBIT(63) 362181834Sroberto u8 unused01180[0x01180 - 0x01138]; 363181834Sroberto 364181834Sroberto/* 0x01180 */ u64 msg_qpad_en_cfg; 365181834Sroberto#define VXGE_HAL_MSG_QPAD_EN_CFG_UMQ_BWR_READ mBIT(3) 366285612Sdelphij#define VXGE_HAL_MSG_QPAD_EN_CFG_DMQ_BWR_READ mBIT(7) 367285612Sdelphij#define VXGE_HAL_MSG_QPAD_EN_CFG_MXP_GENDMA_READ mBIT(11) 368285612Sdelphij#define VXGE_HAL_MSG_QPAD_EN_CFG_UXP_GENDMA_READ mBIT(15) 369285612Sdelphij#define VXGE_HAL_MSG_QPAD_EN_CFG_UMQ_MSG_WRITE mBIT(19) 370181834Sroberto#define VXGE_HAL_MSG_QPAD_EN_CFG_UMQDMQ_IR_WRITE mBIT(23) 371285612Sdelphij#define VXGE_HAL_MSG_QPAD_EN_CFG_MXP_GENDMA_WRITE mBIT(27) 372285612Sdelphij#define VXGE_HAL_MSG_QPAD_EN_CFG_UXP_GENDMA_WRITE mBIT(31) 373285612Sdelphij/* 0x01188 */ u64 msg_pci_cfg; 374285612Sdelphij#define VXGE_HAL_MSG_PCI_CFG_GENDMA_NO_SNOOP mBIT(3) 375181834Sroberto#define VXGE_HAL_MSG_PCI_CFG_UMQDMQ_IR_NO_SNOOP mBIT(7) 376181834Sroberto#define VXGE_HAL_MSG_PCI_CFG_UMQ_NO_SNOOP mBIT(11) 377181834Sroberto#define VXGE_HAL_MSG_PCI_CFG_DMQ_NO_SNOOP mBIT(15) 378181834Sroberto/* 0x01190 */ u64 umqdmq_ir_init; 379181834Sroberto#define VXGE_HAL_UMQDMQ_IR_INIT_HOST_WRITE_ADD(val) vBIT(val, 0, 64) 380285612Sdelphij/* 0x01198 */ u64 dmq_ir_int; 381181834Sroberto#define VXGE_HAL_DMQ_IR_INT_IMMED_ENABLE mBIT(6) 382181834Sroberto#define VXGE_HAL_DMQ_IR_INT_EVENT_ENABLE mBIT(7) 383181834Sroberto#define VXGE_HAL_DMQ_IR_INT_NUMBER(val) vBIT(val, 9, 7) 384181834Sroberto#define VXGE_HAL_DMQ_IR_INT_BITMAP(val) vBIT(val, 16, 16) 385181834Sroberto/* 0x011a0 */ u64 dmq_bwr_init_add; 386181834Sroberto#define VXGE_HAL_DMQ_BWR_INIT_ADD_HOST(val) vBIT(val, 0, 64) 387181834Sroberto/* 0x011a8 */ u64 dmq_bwr_init_byte; 388181834Sroberto#define VXGE_HAL_DMQ_BWR_INIT_BYTE_COUNT(val) vBIT(val, 0, 32) 389181834Sroberto/* 0x011b0 */ u64 dmq_ir; 390181834Sroberto#define VXGE_HAL_DMQ_IR_POLICY(val) vBIT(val, 0, 8) 391181834Sroberto/* 0x011b8 */ u64 umq_int; 392285612Sdelphij#define VXGE_HAL_UMQ_INT_IMMED_ENABLE mBIT(6) 393181834Sroberto#define VXGE_HAL_UMQ_INT_EVENT_ENABLE mBIT(7) 394181834Sroberto#define VXGE_HAL_UMQ_INT_NUMBER(val) vBIT(val, 9, 7) 395181834Sroberto#define VXGE_HAL_UMQ_INT_BITMAP(val) vBIT(val, 16, 16) 396181834Sroberto/* 0x011c0 */ u64 umq_mr2vp_bwr_pfch_init; 397181834Sroberto#define VXGE_HAL_UMQ_MR2VP_BWR_PFCH_INIT_NUMBER(val) vBIT(val, 0, 8) 398181834Sroberto/* 0x011c8 */ u64 umq_bwr_pfch_ctrl; 399181834Sroberto#define VXGE_HAL_UMQ_BWR_PFCH_CTRL_POLL_EN mBIT(3) 400181834Sroberto/* 0x011d0 */ u64 umq_mr2vp_bwr_eol; 401181834Sroberto#define VXGE_HAL_UMQ_MR2VP_BWR_EOL_POLL_LATENCY(val) vBIT(val, 32, 32) 402181834Sroberto/* 0x011d8 */ u64 umq_bwr_init_add; 403285612Sdelphij#define VXGE_HAL_UMQ_BWR_INIT_ADD_HOST(val) vBIT(val, 0, 64) 404285612Sdelphij/* 0x011e0 */ u64 umq_bwr_init_byte; 405285612Sdelphij#define VXGE_HAL_UMQ_BWR_INIT_BYTE_COUNT(val) vBIT(val, 0, 32) 406285612Sdelphij/* 0x011e8 */ u64 gendma_int; 407285612Sdelphij#define VXGE_HAL_GENDMA_INT_IMMED_ENABLE mBIT(6) 408285612Sdelphij#define VXGE_HAL_GENDMA_INT_EVENT_ENABLE mBIT(7) 409285612Sdelphij#define VXGE_HAL_GENDMA_INT_NUMBER(val) vBIT(val, 9, 7) 410285612Sdelphij#define VXGE_HAL_GENDMA_INT_BITMAP(val) vBIT(val, 16, 16) 411285612Sdelphij/* 0x011f0 */ u64 umqdmq_ir_init_notify; 412285612Sdelphij#define VXGE_HAL_UMQDMQ_IR_INIT_NOTIFY_PULSE mBIT(3) 413285612Sdelphij/* 0x011f8 */ u64 dmq_init_notify; 414285612Sdelphij#define VXGE_HAL_DMQ_INIT_NOTIFY_PULSE mBIT(3) 415285612Sdelphij/* 0x01200 */ u64 umq_init_notify; 416285612Sdelphij#define VXGE_HAL_UMQ_INIT_NOTIFY_PULSE mBIT(3) 417285612Sdelphij u8 unused01380[0x01380 - 0x01208]; 418285612Sdelphij 419285612Sdelphij/* 0x01380 */ u64 tpa_cfg; 420285612Sdelphij#define VXGE_HAL_TPA_CFG_IGNORE_FRAME_ERR mBIT(3) 421285612Sdelphij#define VXGE_HAL_TPA_CFG_IPV6_STOP_SEARCHING mBIT(7) 422285612Sdelphij#define VXGE_HAL_TPA_CFG_L4_PSHDR_PRESENT mBIT(11) 423285612Sdelphij#define VXGE_HAL_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS mBIT(15) 424285612Sdelphij u8 unused01400[0x01400 - 0x01388]; 425285612Sdelphij 426285612Sdelphij/* 0x01400 */ u64 tx_vp_reset_discarded_frms; 427285612Sdelphij#define VXGE_HAL_TX_VP_RESET_DISCARDED_FRMS_TX_VP_RESET_DISCARDED_FRMS(val)\ 428181834Sroberto vBIT(val, 48, 16) 429181834Sroberto u8 unused01480[0x01480 - 0x01408]; 430181834Sroberto 431181834Sroberto/* 0x01480 */ u64 fau_rpa_vcfg; 432181834Sroberto#define VXGE_HAL_FAU_RPA_VCFG_L4_COMP_CSUM mBIT(7) 433181834Sroberto#define VXGE_HAL_FAU_RPA_VCFG_L3_INCL_CF mBIT(11) 434181834Sroberto#define VXGE_HAL_FAU_RPA_VCFG_L3_COMP_CSUM mBIT(15) 435181834Sroberto u8 unused014a8[0x014a8 - 0x01488]; 436181834Sroberto 437285612Sdelphij/* 0x014a8 */ u64 fau_adaptive_lro_filter_ctrl; 438181834Sroberto#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IP_FILTER_EN mBIT(0) 439285612Sdelphij#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IP_MODE mBIT(1) 440181834Sroberto#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_VLAN_FILTER_EN mBIT(2) 441181834Sroberto#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IPV4_ADDRESS_A_EN mBIT(3) 442285612Sdelphij#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IPV4_ADDRESS_B_EN mBIT(4) 443181834Sroberto#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IPV4_ADDRESS_C_EN mBIT(5) 444181834Sroberto#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IPV4_ADDRESS_D_EN mBIT(6) 445181834Sroberto/* 0x014b0 */ u64 fau_adaptive_lro_filter_ip_data0; 446181834Sroberto#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_IP_DATA0_DATA(val) vBIT(val, 0, 64) 447181834Sroberto/* 0x014b8 */ u64 fau_adaptive_lro_filter_ip_data1; 448181834Sroberto#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_IP_DATA1_DATA(val) vBIT(val, 0, 64) 449285612Sdelphij/* 0x014c0 */ u64 fau_adaptive_lro_filter_vlan_data; 450285612Sdelphij#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_VLAN_DATA_VLAN_VID(val)\ 451285612Sdelphij vBIT(val, 0, 12) 452181834Sroberto u8 unused014d0[0x014d0 - 0x014c8]; 453285612Sdelphij 454285612Sdelphij/* 0x014d0 */ u64 dbg_stats_rx_mpa; 455285612Sdelphij#define VXGE_HAL_DBG_STATS_RX_MPA_CRC_FAIL_FRMS(val) vBIT(val, 0, 16) 456285612Sdelphij#define VXGE_HAL_DBG_STATS_RX_MPA_MRK_FAIL_FRMS(val) vBIT(val, 16, 16) 457181834Sroberto#define VXGE_HAL_DBG_STATS_RX_MPA_LEN_FAIL_FRMS(val) vBIT(val, 32, 16) 458181834Sroberto/* 0x014d8 */ u64 dbg_stats_rx_fau; 459181834Sroberto#define VXGE_HAL_DBG_STATS_RX_FAU_RX_WOL_FRMS(val) vBIT(val, 0, 16) 460181834Sroberto#define VXGE_HAL_DBG_STATS_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val)\ 461285612Sdelphij vBIT(val, 16, 16) 462285612Sdelphij#define VXGE_HAL_DBG_STATS_RX_FAU_RX_PERMITTED_FRMS(val) vBIT(val, 32, 32) 463181834Sroberto u8 unused014f0[0x014f0 - 0x014e0]; 464285612Sdelphij 465181834Sroberto/* 0x014f0 */ u64 fbmc_vp_rdy; 466285612Sdelphij#define VXGE_HAL_FBMC_VP_RDY_QUEUE_SPAV_FM mBIT(0) 467285612Sdelphij u8 unused01e00[0x01e00 - 0x014f8]; 468285612Sdelphij 469181834Sroberto/* 0x01e00 */ u64 vpath_pcipif_int_status; 470181834Sroberto#define VXGE_HAL_VPATH_PCIPIF_INT_STATUS_SRPCIM_MSG_TO_VPATH_INT mBIT(3) 471285612Sdelphij#define VXGE_HAL_VPATH_PCIPIF_INT_STATUS_VPATH_SPARE_R1_INT mBIT(7) 472285612Sdelphij/* 0x01e08 */ u64 vpath_pcipif_int_mask; 473285612Sdelphij u8 unused01e20[0x01e20 - 0x01e10]; 474285612Sdelphij 475285612Sdelphij/* 0x01e20 */ u64 srpcim_msg_to_vpath_reg; 476285612Sdelphij#define VXGE_HAL_SRPCIM_MSG_TO_VPATH_REG_INT mBIT(3) 477285612Sdelphij/* 0x01e28 */ u64 srpcim_msg_to_vpath_mask; 478285612Sdelphij/* 0x01e30 */ u64 srpcim_msg_to_vpath_alarm; 479285612Sdelphij u8 unused01ea0[0x01ea0 - 0x01e38]; 480285612Sdelphij 481285612Sdelphij/* 0x01ea0 */ u64 vpath_to_srpcim_wmsg; 482#define VXGE_HAL_VPATH_TO_SRPCIM_WMSG_WMSG(val) vBIT(val, 0, 64) 483/* 0x01ea8 */ u64 vpath_to_srpcim_wmsg_trig; 484#define VXGE_HAL_VPATH_TO_SRPCIM_WMSG_TRIG mBIT(0) 485 u8 unused02000[0x02000 - 0x01eb0]; 486 487/* 0x02000 */ u64 vpath_general_int_status; 488#define VXGE_HAL_VPATH_GENERAL_INT_STATUS_PIC_INT mBIT(3) 489#define VXGE_HAL_VPATH_GENERAL_INT_STATUS_PCI_INT mBIT(7) 490#define VXGE_HAL_VPATH_GENERAL_INT_STATUS_WRDMA_INT mBIT(15) 491#define VXGE_HAL_VPATH_GENERAL_INT_STATUS_XMAC_INT mBIT(19) 492/* 0x02008 */ u64 vpath_general_int_mask; 493#define VXGE_HAL_VPATH_GENERAL_INT_MASK_PIC_INT mBIT(3) 494#define VXGE_HAL_VPATH_GENERAL_INT_MASK_PCI_INT mBIT(7) 495#define VXGE_HAL_VPATH_GENERAL_INT_MASK_WRDMA_INT mBIT(15) 496#define VXGE_HAL_VPATH_GENERAL_INT_MASK_XMAC_INT mBIT(19) 497/* 0x02010 */ u64 vpath_ppif_int_status; 498#define VXGE_HAL_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_INT mBIT(3) 499#define VXGE_HAL_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_INT mBIT(7) 500#define VXGE_HAL_VPATH_PPIF_INT_STATUS_PCI_CONFIG_ERRORS_INT mBIT(11) 501#define VXGE_HAL_VPATH_PPIF_INT_STATUS_MRPCIM_TO_VPATH_ALARM_INT mBIT(15) 502#define VXGE_HAL_VPATH_PPIF_INT_STATUS_SRPCIM_TO_VPATH_ALARM_INT mBIT(19) 503/* 0x02018 */ u64 vpath_ppif_int_mask; 504/* 0x02020 */ u64 kdfcctl_errors_reg; 505#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR mBIT(3) 506#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR mBIT(7) 507#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR mBIT(11) 508#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON mBIT(15) 509#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON mBIT(19) 510#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON mBIT(23) 511#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR mBIT(31) 512#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR mBIT(35) 513#define VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR mBIT(39) 514/* 0x02028 */ u64 kdfcctl_errors_mask; 515/* 0x02030 */ u64 kdfcctl_errors_alarm; 516 u8 unused02040[0x02040 - 0x02038]; 517 518/* 0x02040 */ u64 general_errors_reg; 519#define VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW mBIT(3) 520#define VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW mBIT(7) 521#define VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW mBIT(11) 522#define VXGE_HAL_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR mBIT(15) 523#define VXGE_HAL_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT mBIT(19) 524#define VXGE_HAL_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS mBIT(27) 525#define VXGE_HAL_GENERAL_ERRORS_REG_INI_SERR_DET mBIT(31) 526/* 0x02048 */ u64 general_errors_mask; 527/* 0x02050 */ u64 general_errors_alarm; 528/* 0x02058 */ u64 pci_config_errors_reg; 529#define VXGE_HAL_PCI_CONFIG_ERRORS_REG_STATUS_ERR mBIT(3) 530#define VXGE_HAL_PCI_CONFIG_ERRORS_REG_UNCOR_ERR mBIT(7) 531#define VXGE_HAL_PCI_CONFIG_ERRORS_REG_COR_ERR mBIT(11) 532/* 0x02060 */ u64 pci_config_errors_mask; 533/* 0x02068 */ u64 pci_config_errors_alarm; 534/* 0x02070 */ u64 mrpcim_to_vpath_alarm_reg; 535#define VXGE_HAL_MRPCIM_TO_VPATH_ALARM_REG_ALARM mBIT(3) 536/* 0x02078 */ u64 mrpcim_to_vpath_alarm_mask; 537/* 0x02080 */ u64 mrpcim_to_vpath_alarm_alarm; 538/* 0x02088 */ u64 srpcim_to_vpath_alarm_reg; 539#define VXGE_HAL_SRPCIM_TO_VPATH_ALARM_REG_PPIF_ALARM(val) vBIT(val, 0, 17) 540/* 0x02090 */ u64 srpcim_to_vpath_alarm_mask; 541/* 0x02098 */ u64 srpcim_to_vpath_alarm_alarm; 542 u8 unused02108[0x02108 - 0x020a0]; 543 544/* 0x02108 */ u64 kdfcctl_status; 545#define VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO0_PRES(val) vBIT(val, 0, 8) 546#define VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO1_PRES(val) vBIT(val, 8, 8) 547#define VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO2_PRES(val) vBIT(val, 16, 8) 548#define VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO0_OVRWR(val) vBIT(val, 24, 8) 549#define VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO1_OVRWR(val) vBIT(val, 32, 8) 550#define VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO2_OVRWR(val) vBIT(val, 40, 8) 551/* 0x02110 */ u64 rsthdlr_status; 552#define VXGE_HAL_RSTHDLR_STATUS_RSTHDLR_CURRENT_RESET mBIT(3) 553#define VXGE_HAL_RSTHDLR_STATUS_RSTHDLR_CURRENT_VPIN(val) vBIT(val, 6, 2) 554/* 0x02118 */ u64 fifo0_status; 555#define VXGE_HAL_FIFO0_STATUS_DBLGEN_FIFO0_RDIDX(val) vBIT(val, 0, 12) 556/* 0x02120 */ u64 fifo1_status; 557#define VXGE_HAL_FIFO1_STATUS_DBLGEN_FIFO1_RDIDX(val) vBIT(val, 0, 12) 558/* 0x02128 */ u64 fifo2_status; 559#define VXGE_HAL_FIFO2_STATUS_DBLGEN_FIFO2_RDIDX(val) vBIT(val, 0, 12) 560 u8 unused02158[0x02158 - 0x02130]; 561 562/* 0x02158 */ u64 tgt_illegal_access; 563#define VXGE_HAL_TGT_ILLEGAL_ACCESS_SWIF_REGION(val) vBIT(val, 1, 7) 564 u8 unused02200[0x02200 - 0x02160]; 565 566/* 0x02200 */ u64 vpath_general_cfg1; 567#define VXGE_HAL_VPATH_GENERAL_CFG1_TC_VALUE(val) vBIT(val, 1, 3) 568#define VXGE_HAL_VPATH_GENERAL_CFG1_DATA_BYTE_SWAPEN mBIT(7) 569#define VXGE_HAL_VPATH_GENERAL_CFG1_DATA_FLIPEN mBIT(11) 570#define VXGE_HAL_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN mBIT(15) 571#define VXGE_HAL_VPATH_GENERAL_CFG1_CTL_FLIPEN mBIT(23) 572#define VXGE_HAL_VPATH_GENERAL_CFG1_MSIX_ADDR_SWAPEN mBIT(51) 573#define VXGE_HAL_VPATH_GENERAL_CFG1_MSIX_ADDR_FLIPEN mBIT(55) 574#define VXGE_HAL_VPATH_GENERAL_CFG1_MSIX_DATA_SWAPEN mBIT(59) 575#define VXGE_HAL_VPATH_GENERAL_CFG1_MSIX_DATA_FLIPEN mBIT(63) 576/* 0x02208 */ u64 vpath_general_cfg2; 577#define VXGE_HAL_VPATH_GENERAL_CFG2_SIZE_QUANTUM(val) vBIT(val, 1, 3) 578/* 0x02210 */ u64 vpath_general_cfg3; 579#define VXGE_HAL_VPATH_GENERAL_CFG3_IGNORE_VPATH_RST_FOR_INTA mBIT(3) 580 u8 unused02220[0x02220 - 0x02218]; 581 582/* 0x02220 */ u64 kdfcctl_cfg0; 583#define VXGE_HAL_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 mBIT(1) 584#define VXGE_HAL_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1 mBIT(2) 585#define VXGE_HAL_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2 mBIT(3) 586#define VXGE_HAL_KDFCCTL_CFG0_BIT_FLIPEN_FIFO0 mBIT(5) 587#define VXGE_HAL_KDFCCTL_CFG0_BIT_FLIPEN_FIFO1 mBIT(6) 588#define VXGE_HAL_KDFCCTL_CFG0_BIT_FLIPEN_FIFO2 mBIT(7) 589#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO0 mBIT(9) 590#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO1 mBIT(10) 591#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO2 mBIT(11) 592#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO0 mBIT(13) 593#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO1 mBIT(14) 594#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO2 mBIT(15) 595#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO0 mBIT(17) 596#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO1 mBIT(18) 597#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO2 mBIT(19) 598#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO0 mBIT(21) 599#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO1 mBIT(22) 600#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO2 mBIT(23) 601#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO0 mBIT(25) 602#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO1 mBIT(26) 603#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO2 mBIT(27) 604#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO0 mBIT(29) 605#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO1 mBIT(30) 606#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO2 mBIT(31) 607#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO0 mBIT(33) 608#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO1 mBIT(34) 609#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO2 mBIT(35) 610#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO0 mBIT(37) 611#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO1 mBIT(38) 612#define VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO2 mBIT(39) 613/* 0x02228 */ u64 dblgen_cfg0; 614#define VXGE_HAL_DBLGEN_CFG0_NO_OF_QWORDS(val) vBIT(val, 0, 12) 615#define VXGE_HAL_DBLGEN_CFG0_EN_DMA mBIT(15) 616#define VXGE_HAL_DBLGEN_CFG0_NO_SNOOP mBIT(19) 617#define VXGE_HAL_DBLGEN_CFG0_RELAX_ORD mBIT(23) 618#define VXGE_HAL_DBLGEN_CFG0_RD_SPLIT_ON_ADDR mBIT(27) 619/* 0x02230 */ u64 dblgen_cfg1; 620#define VXGE_HAL_DBLGEN_CFG1_FIFO0_BUFFER_START_ADDR(val) vBIT(val, 0, 64) 621/* 0x02238 */ u64 dblgen_cfg2; 622#define VXGE_HAL_DBLGEN_CFG2_FIFO1_BUFFER_START_ADDR(val) vBIT(val, 0, 64) 623/* 0x02240 */ u64 dblgen_cfg3; 624#define VXGE_HAL_DBLGEN_CFG3_FIFO2_BUFFER_START_ADDR(val) vBIT(val, 0, 64) 625/* 0x02248 */ u64 dblgen_cfg4; 626#define VXGE_HAL_DBLGEN_CFG4_TRIPLET_PRIORITY_VP_NUMBER(val) vBIT(val, 3, 5) 627/* 0x02250 */ u64 dblgen_cfg5; 628#define VXGE_HAL_DBLGEN_CFG5_FIFO0_WRIDX(val) vBIT(val, 0, 12) 629/* 0x02258 */ u64 dblgen_cfg6; 630#define VXGE_HAL_DBLGEN_CFG6_FIFO1_WRIDX(val) vBIT(val, 0, 12) 631/* 0x02260 */ u64 dblgen_cfg7; 632#define VXGE_HAL_DBLGEN_CFG7_FIFO2_WRIDX(val) vBIT(val, 0, 12) 633/* 0x02268 */ u64 stats_cfg; 634#define VXGE_HAL_STATS_CFG_START_HOST_ADDR(val) vBIT(val, 0, 57) 635/* 0x02270 */ u64 interrupt_cfg0; 636#define VXGE_HAL_INTERRUPT_CFG0_MSIX_FOR_RXTI(val) vBIT(val, 1, 7) 637#define VXGE_HAL_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(val) vBIT(val, 9, 7) 638#define VXGE_HAL_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(val) vBIT(val, 17, 7) 639#define VXGE_HAL_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(val) vBIT(val, 25, 7) 640#define VXGE_HAL_INTERRUPT_CFG0_GROUP3_MSIX_FOR_TXTI(val) vBIT(val, 33, 7) 641 u8 unused02280[0x02280 - 0x02278]; 642 643/* 0x02280 */ u64 interrupt_cfg2; 644#define VXGE_HAL_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(val) vBIT(val, 1, 7) 645/* 0x02288 */ u64 one_shot_vect0_en; 646#define VXGE_HAL_ONE_SHOT_VECT0_EN_ONE_SHOT_VECT0_EN mBIT(3) 647/* 0x02290 */ u64 one_shot_vect1_en; 648#define VXGE_HAL_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN mBIT(3) 649/* 0x02298 */ u64 one_shot_vect2_en; 650#define VXGE_HAL_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN mBIT(3) 651/* 0x022a0 */ u64 one_shot_vect3_en; 652#define VXGE_HAL_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN mBIT(3) 653 u8 unused022b0[0x022b0 - 0x022a8]; 654 655/* 0x022b0 */ u64 pci_config_access_cfg1; 656#define VXGE_HAL_PCI_CONFIG_ACCESS_CFG1_ADDRESS(val) vBIT(val, 0, 12) 657#define VXGE_HAL_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0 mBIT(15) 658/* 0x022b8 */ u64 pci_config_access_cfg2; 659#define VXGE_HAL_PCI_CONFIG_ACCESS_CFG2_REQ mBIT(0) 660/* 0x022c0 */ u64 pci_config_access_status; 661#define VXGE_HAL_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR mBIT(0) 662#define VXGE_HAL_PCI_CONFIG_ACCESS_STATUS_DATA(val) vBIT(val, 32, 32) 663 u8 unused02300[0x02300 - 0x022c8]; 664 665/* 0x02300 */ u64 vpath_debug_stats0; 666#define VXGE_HAL_VPATH_DEBUG_STATS0_INI_NUM_MWR_SENT(val) vBIT(val, 0, 32) 667/* 0x02308 */ u64 vpath_debug_stats1; 668#define VXGE_HAL_VPATH_DEBUG_STATS1_INI_NUM_MRD_SENT(val) vBIT(val, 0, 32) 669/* 0x02310 */ u64 vpath_debug_stats2; 670#define VXGE_HAL_VPATH_DEBUG_STATS2_INI_NUM_CPL_RCVD(val) vBIT(val, 0, 32) 671/* 0x02318 */ u64 vpath_debug_stats3; 672#define VXGE_HAL_VPATH_DEBUG_STATS3_INI_NUM_MWR_BYTE_SENT(val) vBIT(val, 0, 64) 673/* 0x02320 */ u64 vpath_debug_stats4; 674#define VXGE_HAL_VPATH_DEBUG_STATS4_INI_NUM_CPL_BYTE_RCVD(val) vBIT(val, 0, 64) 675/* 0x02328 */ u64 vpath_debug_stats5; 676#define VXGE_HAL_VPATH_DEBUG_STATS5_WRCRDTARB_XOFF(val) vBIT(val, 32, 32) 677/* 0x02330 */ u64 vpath_debug_stats6; 678#define VXGE_HAL_VPATH_DEBUG_STATS6_RDCRDTARB_XOFF(val) vBIT(val, 32, 32) 679/* 0x02338 */ u64 vpath_genstats_count01; 680#define VXGE_HAL_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT1(val)\ 681 vBIT(val, 0, 32) 682#define VXGE_HAL_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT0(val)\ 683 vBIT(val, 32, 32) 684/* 0x02340 */ u64 vpath_genstats_count23; 685#define VXGE_HAL_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT3(val)\ 686 vBIT(val, 0, 32) 687#define VXGE_HAL_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT2(val)\ 688 vBIT(val, 32, 32) 689/* 0x02348 */ u64 vpath_genstats_count4; 690#define VXGE_HAL_VPATH_GENSTATS_COUNT4_PPIF_VPATH_GENSTATS_COUNT4(val)\ 691 vBIT(val, 32, 32) 692/* 0x02350 */ u64 vpath_genstats_count5; 693#define VXGE_HAL_VPATH_GENSTATS_COUNT5_PPIF_VPATH_GENSTATS_COUNT5(val)\ 694 vBIT(val, 32, 32) 695 u8 unused02540[0x02540 - 0x02358]; 696 697/* 0x02540 */ u64 qcc_pci_cfg; 698#define VXGE_HAL_QCC_PCI_CFG_ADD_PAD_CQE_SPACE mBIT(5) 699#define VXGE_HAL_QCC_PCI_CFG_ADD_PAD_WQE mBIT(6) 700#define VXGE_HAL_QCC_PCI_CFG_ADD_PAD_SRQIR mBIT(7) 701#define VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_CQE_SPACE mBIT(13) 702#define VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_WQE mBIT(14) 703#define VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_SRQIR mBIT(15) 704#define VXGE_HAL_QCC_PCI_CFG_RELAXED_SRQIR mBIT(23) 705#define VXGE_HAL_QCC_PCI_CFG_CTL_STR_CQE_SPACE mBIT(29) 706#define VXGE_HAL_QCC_PCI_CFG_CTL_STR_WQE mBIT(30) 707#define VXGE_HAL_QCC_PCI_CFG_CTL_STR_SRQIR mBIT(31) 708 u8 unused02600[0x02600 - 0x02548]; 709 710/* 0x02600 */ u64 h2l_vpath_config; 711#define VXGE_HAL_H2L_VPATH_CONFIG_OD_PAD_ENABLE mBIT(7) 712#define VXGE_HAL_H2L_VPATH_CONFIG_OD_NO_SNOOP mBIT(15) 713/* 0x02608 */ u64 h2l_zero_byte_read_address; 714#define VXGE_HAL_H2L_ZERO_BYTE_READ_ADDRESS_H2L_ZERO_BYTE_READ_ADDRESS(val)\ 715 vBIT(val, 0, 64) 716 u8 unused02640[0x02640 - 0x02610]; 717 718/* 0x02640 */ u64 ph2l_vp_cfg0; 719#define VXGE_HAL_PH2L_VP_CFG0_NOSNOOP_DATA mBIT(7) 720 721} vxge_hal_vpath_reg_t; 722 723__EXTERN_END_DECLS 724 725#endif /* VXGE_HAL_VPATH_REGS_H */ 726