/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonMachineScheduler.cpp | 38 /// Check if scheduling of this SU is possible 43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { argument 44 if (!SU || !SU->getInstr()) 49 switch (SU->getInstr()->getOpcode()) { 51 if (!ResourcesModel->canReserveResources(SU->getInstr())) 75 if (I->getSUnit() == SU) 83 bool VLIWResourceModel::reserveResources(SUnit *SU) { argument 86 if (!SU) { 92 // If this SU doe 219 releaseTopNode(SUnit *SU) argument 236 releaseBottomNode(SUnit *SU) argument 268 checkHazard(SUnit *SU) argument 279 releaseNode(SUnit *SU, unsigned ReadyCycle) argument 320 bumpNode(SUnit *SU) argument 358 SUnit *SU = *(Pending.begin()+i); local 378 removeReady(SUnit *SU) argument 407 traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, PressureElement P) argument 422 getSingleUnscheduledPred(SUnit *SU) argument 440 getSingleUnscheduledSucc(SUnit *SU) argument 467 SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose) argument 642 SUnit *SU; local 684 schedNode(SUnit *SU, bool IsTopNode) argument [all...] |
H A D | HexagonMachineScheduler.h | 88 bool isResourceAvailable(SUnit *SU); 89 bool reserveResources(SUnit *SU); 115 SUnit *SU; member in struct:llvm::ConvergingVLIWScheduler::SchedCandidate 123 SchedCandidate(): SU(NULL), SCost(0) {} 176 bool checkHazard(SUnit *SU); 178 void releaseNode(SUnit *SU, unsigned ReadyCycle); 182 void bumpNode(SUnit *SU); 186 void removeReady(SUnit *SU); 214 virtual void schedNode(SUnit *SU, bool IsTopNode); 216 virtual void releaseTopNode(SUnit *SU); [all...] |
/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | ResourcePriorityQueue.h | 88 void addNode(const SUnit *SU) { argument 92 void updateNode(const SUnit *SU) {} argument 108 /// Single cost function reflecting benefit of scheduling SU 110 signed SUSchedulingCost (SUnit *SU); 114 void initNumRegDefsLeft(SUnit *SU); 115 void updateNumRegDefsLeft(SUnit *SU); 116 signed regPressureDelta(SUnit *SU, bool RawPressure = false); 117 signed rawRegPressureDelta (SUnit *SU, unsigned RCId); 125 virtual void remove(SUnit *SU); 131 bool isResourceAvailable(SUnit *SU); [all...] |
H A D | ScheduleDAGInstrs.h | 35 SUnit *SU; member in struct:llvm::VReg2SUnit 37 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {} 47 SUnit *SU; member in struct:llvm::PhysRegSUOper 51 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {} 160 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { 161 if (!SU->SchedClass) 162 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr()); 163 return SU->SchedClass; 217 virtual void dumpNode(const SUnit *SU) cons [all...] |
H A D | LatencyPriorityQueue.h | 57 void addNode(const SUnit *SU) { argument 61 void updateNode(const SUnit *SU) { argument 84 virtual void remove(SUnit *SU); 95 void AdjustPriorityOfUnscheduledPreds(SUnit *SU); 96 SUnit *getSingleUnscheduledPred(SUnit *SU);
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H A D | ScheduleDFS.h | 148 unsigned getNumInstrs(const SUnit *SU) const { 149 return DFSNodeData[SU->NodeNum].InstrCount; 161 ILPValue getILP(const SUnit *SU) const { 162 return ILPValue(DFSNodeData[SU->NodeNum].InstrCount, 1 + SU->getDepth()); 172 unsigned getSubtreeID(const SUnit *SU) const { 175 assert(SU->NodeNum < DFSNodeData.size() && "New Node"); 176 return DFSNodeData[SU->NodeNum].SubtreeID;
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H A D | MachineScheduler.h | 128 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0; 132 virtual void releaseTopNode(SUnit *SU) = 0; 135 virtual void releaseBottomNode(SUnit *SU) = 0; 156 // SU is in this queue if it's NodeQueueID is a superset of this ID. 157 bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); } 173 iterator find(SUnit *SU) { argument 174 return std::find(Queue.begin(), Queue.end(), SU); 177 void push(SUnit *SU) { argument 178 Queue.push_back(SU); [all...] |
H A D | ScoreboardHazardRecognizer.h | 115 // Stalls provides an cycle offset at which SU will be scheduled. It will be 117 virtual HazardType getHazardType(SUnit *SU, int Stalls); 119 virtual void EmitInstruction(SUnit *SU);
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/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ResourcePriorityQueue.cpp | 71 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { argument 73 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 108 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, argument 111 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 146 static unsigned numberCtrlDepsInSU(SUnit *SU) { argument 148 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 156 static unsigned numberCtrlPredInSU(SUnit *SU) { argument 174 SUnit *SU = &(*SUnits)[i]; local 216 getSingleUnscheduledPred(SUnit *SU) argument 232 push(SUnit *SU) argument 247 isResourceAvailable(SUnit *SU) argument 290 reserveResources(SUnit *SU) argument 327 rawRegPressureDelta(SUnit *SU, unsigned RCId) argument 361 regPressureDelta(SUnit *SU, bool RawPressure) argument 403 SUSchedulingCost(SUnit *SU) argument 473 scheduledNode(SUnit *SU) argument 549 initNumRegDefsLeft(SUnit *SU) argument 581 adjustPriorityOfUnscheduledPreds(SUnit *SU) argument 634 remove(SUnit *SU) argument [all...] |
H A D | ScheduleDAGVLIW.cpp | 86 void releaseSucc(SUnit *SU, const SDep &D); 87 void releaseSuccessors(SUnit *SU); 88 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle); 115 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { argument 130 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency()); 139 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) { argument 141 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 146 releaseSucc(SU, *I); 153 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigne argument [all...] |
H A D | ScheduleDAGRRList.cpp | 184 /// IsReachable - Checks if SU is reachable from TargetSU. 185 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { argument 186 return Topo.IsReachable(SU, TargetSU); 189 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will 191 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { argument 192 return Topo.WillCreateCycle(SU, TargetSU); 195 /// AddPred - adds a predecessor edge to SUnit SU. 198 void AddPred(SUnit *SU, const SDep &D) { argument 199 Topo.AddPred(SU, D.getSUnit()); 200 SU 206 RemovePred(SUnit *SU, const SDep &D) argument 212 isReady(SUnit *SU) argument 364 ReleasePred(SUnit *SU, const SDep *PredEdge) argument 524 ReleasePredecessors(SUnit *SU) argument 621 AdvancePastStalls(SUnit *SU) argument 663 EmitNode(SUnit *SU) argument 705 ScheduleNodeBottomUp(SUnit *SU) argument 804 UnscheduleNodeBottomUp(SUnit *SU) argument 893 SUnit *SU = *I; local 903 BacktrackBottomUp(SUnit *SU, SUnit *BtSU) argument 925 isOperandOf(const SUnit *SU, SDNode *N) argument 936 CopyAndMoveSuccessors(SUnit *SU) argument 1135 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVector<SUnit*, 2> &Copies) argument 1205 CheckForLiveRegDef(SUnit *SU, unsigned Reg, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVector<unsigned, 4> &LRegs, const TargetRegisterInfo *TRI) argument 1227 CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVector<unsigned, 4> &LRegs) argument 1255 DelayForLiveRegsBottomUp(SUnit *SU, SmallVector<unsigned, 4> &LRegs) argument 1331 SUnit *SU = Interferences[i-1]; local 1502 SUnit *SU = PickNodeToScheduleBottomUp(); local 1706 remove(SUnit *SU) argument 1799 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); local [all...] |
H A D | ScheduleDAGSDNodes.cpp | 78 SUnit *SU = &SUnits.back(); local 83 SU->SchedulingPref = Sched::None; 85 SU->SchedulingPref = TLI.getSchedulingPreference(N); 86 return SU; 90 SUnit *SU = newSUnit(Old->getNode()); local 91 SU->OrigNode = Old->OrigNode; 92 SU->Latency = Old->Latency; 93 SU->isVRegCycle = Old->isVRegCycle; 94 SU->isCall = Old->isCall; 95 SU [all...] |
H A D | ScheduleDAGSDNodes.h | 92 void InitVRegCycleFlag(SUnit *SU); 96 void InitNumRegDefsLeft(SUnit *SU); 100 virtual void computeLatency(SUnit *SU); 120 virtual void dumpNode(const SUnit *SU) const; 124 virtual std::string getGraphNodeLabel(const SUnit *SU) const; 140 RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD); 180 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
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H A D | ScheduleDAGFast.cpp | 85 /// AddPred - adds a predecessor edge to SUnit SU. 87 void AddPred(SUnit *SU, const SDep &D) { argument 88 SU->addPred(D); 91 /// RemovePred - removes a predecessor edge from SUnit SU. 93 void RemovePred(SUnit *SU, const SDep &D) { argument 94 SU->removePred(D); 98 void ReleasePred(SUnit *SU, SDep *PredEdge); 99 void ReleasePredecessors(SUnit *SU, unsigned CurCycle); 139 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { argument 160 void ScheduleDAGFast::ReleasePredecessors(SUnit *SU, unsigne argument 182 ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) argument 212 CopyAndMoveSuccessors(SUnit *SU) argument 387 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVector<SUnit*, 2> &Copies) argument 448 CheckForLiveRegDef(SUnit *SU, unsigned Reg, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVector<unsigned, 4> &LRegs, const TargetRegisterInfo *TRI) argument 469 DelayForLiveRegsBottomUp(SUnit *SU, SmallVector<unsigned, 4> &LRegs) argument [all...] |
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/ |
H A D | LatencyPriorityQueue.cpp | 54 /// of SU, return it, otherwise return null. 55 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) { argument 57 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 72 void LatencyPriorityQueue::push(SUnit *SU) { argument 76 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 78 if (getSingleUnscheduledPred(I->getSUnit()) == SU) 81 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking; 83 Queue.push_back(SU); 91 scheduledNode(SUnit *SU) argument 104 AdjustPriorityOfUnscheduledPreds(SUnit *SU) argument 133 remove(SUnit *SU) argument [all...] |
H A D | ScheduleDAGInstrs.cpp | 196 /// the exit SU to the register defs and use list. This is because we want to 239 /// MO is an operand of SU's instruction that defines a physical register. Add 240 /// data dependencies from SU to any uses of the physical register. 241 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { argument 242 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); 253 SUnit *UseSU = I->SU; 254 if (UseSU == SU) 263 Dep = SDep(SU, SDep::Artificial); 267 SU->hasPhysRegDefs = true; 268 Dep = SDep(SU, SDe 287 addPhysRegDeps(SUnit *SU, unsigned OperIdx) argument 368 addVRegDefDeps(SUnit *SU, unsigned OperIdx) argument 408 addVRegUseDeps(SUnit *SU, unsigned OperIdx) argument 607 adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI, SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList, unsigned LatencyToLoad) argument 681 SUnit *SU = newSUnit(MI); local 756 SUnit *SU = MISUnitMap[MI]; local 1055 visitPreorder(const SUnit *SU) argument 1063 visitPostorderNode(const SUnit *SU) argument 1215 follow(const SUnit *SU) argument 1235 hasDataSucc(const SUnit *SU) argument 1253 const SUnit *SU = &*SI; local [all...] |
H A D | MachineScheduler.cpp | 351 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { argument 373 /// releaseSuccessors - Call releaseSucc on each of SU's successors. 374 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { argument 375 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 377 releaseSucc(SU, &*I); 385 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) { argument 407 /// releasePredecessors - Call releasePred on each of SU's predecessors. 408 void ScheduleDAGMI::releasePredecessors(SUnit *SU) { argument 409 for (SUnit::pred_iterator I = SU 618 SUnit *SU = &(*I); local 669 scheduleMI(SUnit *SU, bool IsTopNode) argument 709 updateQueues(SUnit *SU, bool IsTopNode) argument 774 SUnit *SU; member in struct:__anon2177::LoadClusterMutation::LoadInfo 808 SUnit *SU = Loads[Idx]; local 856 SUnit *SU = &DAG->SUnits[Idx]; local 906 SUnit *SU = &DAG->SUnits[--Idx]; local 1095 SUnit *SU = &DAG->SUnits[Idx]; local 1158 SUnit *SU; member in struct:__anon2180::ConvergingScheduler::SchedCandidate 1457 releaseTopNode(SUnit *SU) argument 1474 releaseBottomNode(SUnit *SU) argument 1519 checkHazard(SUnit *SU) argument 1562 releaseNode(SUnit *SU, unsigned ReadyCycle) argument 1636 bumpNode(SUnit *SU) argument 1692 SUnit *SU = *(Pending.begin()+i); local 1713 removeReady(SUnit *SU) argument 1900 getWeakLeft(const SUnit *SU, bool isTop) argument 1911 biasPhysRegCopy(const SUnit *SU, bool isTop) argument 2280 SUnit *SU; local 2318 reschedulePhysRegCopies(SUnit *SU, bool isTop) argument 2349 schedNode(SUnit *SU, bool IsTopNode) argument 2463 SUnit *SU = ReadyQ.back(); local 2482 schedNode(SUnit *SU, bool IsTopNode) argument 2488 releaseBottomNode(SUnit *SU) argument 2550 SUnit *SU; local 2572 schedNode(SUnit *SU, bool IsTopNode) argument 2574 releaseTopNode(SUnit *SU) argument 2577 releaseBottomNode(SUnit *SU) argument 2639 getNodeLabel(const SUnit *SU, const ScheduleDAG *G) argument 2645 getNodeDescription(const SUnit *SU, const ScheduleDAG *G) argument [all...] |
H A D | ScheduleDAG.cpp | 183 SUnit *SU = WorkList.pop_back_val(); 184 SU->isDepthCurrent = false; 185 for (SUnit::const_succ_iterator I = SU->Succs.begin(), 186 E = SU->Succs.end(); I != E; ++I) { 199 SUnit *SU = WorkList.pop_back_val(); 200 SU->isHeightCurrent = false; 201 for (SUnit::const_pred_iterator I = SU->Preds.begin(), 202 E = SU->Preds.end(); I != E; ++I) { 317 dbgs() << "SU(" << NodeNum << "): "; 346 dbgs() << "SU(" << [all...] |
H A D | ScoreboardHazardRecognizer.cpp | 118 ScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument 128 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 165 DEBUG(dbgs() << "SU(" << SU->NodeNum << "): "); 166 DEBUG(DAG->dumpNode(SU)); 178 void ScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) { argument 184 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
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/freebsd-10.0-release/contrib/llvm/lib/Target/R600/ |
H A D | R600MachineScheduler.cpp | 64 SUnit *SU = 0; local 78 SU = pickAlu(); 79 if (SU) { 86 if (!SU) { 88 SU = pickOther(IDFetch); 89 if (SU) 94 if (!SU) { 95 SU = pickOther(IDOther); 96 if (SU) 101 if (SU) { 121 schedNode(SUnit *SU, bool IsTopNode) argument 164 releaseTopNode(SUnit *SU) argument 173 releaseBottomNode(SUnit *SU) argument 246 getInstKind(SUnit* SU) argument 295 SUnit *SU = *It; local 401 SUnit *SU = AttemptFillSlot(Chan); local 415 SUnit *SU = 0; local [all...] |
H A D | R600MachineScheduler.h | 96 virtual void schedNode(SUnit *SU, bool IsTopNode); 97 virtual void releaseTopNode(SUnit *SU); 98 virtual void releaseBottomNode(SUnit *SU); 103 int getInstKind(SUnit *SU); 105 AluKind getAluKind(SUnit *SU) const;
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/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 35 ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument 38 MachineInstr *MI = SU->getInstr(); 70 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls); 79 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) { argument 80 MachineInstr *MI = SU->getInstr(); 86 ScoreboardHazardRecognizer::EmitInstruction(SU);
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H A D | ARMHazardRecognizer.h | 47 virtual HazardType getHazardType(SUnit *SU, int Stalls); 49 virtual void EmitInstruction(SUnit *SU);
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/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.h | 33 virtual HazardType getHazardType(SUnit *SU, int Stalls); 34 virtual void EmitInstruction(SUnit *SU); 68 virtual HazardType getHazardType(SUnit *SU, int Stalls); 69 virtual void EmitInstruction(SUnit *SU);
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H A D | PPCHazardRecognizers.cpp | 26 void PPCScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) { argument 27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 32 ScoreboardHazardRecognizer::EmitInstruction(SU); 36 PPCScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument 37 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls); 137 getHazardType(SUnit *SU, int Stalls) { argument 140 MachineInstr *MI = SU->getInstr(); 197 void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) { argument 198 MachineInstr *MI = SU->getInstr();
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