/freebsd-10.0-release/contrib/llvm/lib/MC/ |
H A D | MCCodeGenInfo.cpp | 18 void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM, argument 20 RelocationModel = RM;
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/freebsd-10.0-release/sys/tools/sound/ |
H A D | emu10k1-mkalsa.sh | 7 RM=${RM:=rm} 11 trap "${RM} -f $OUT.tmp" EXIT
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/freebsd-10.0-release/crypto/heimdal/lib/sqlite/ |
H A D | NTMakefile | 46 -$(RM) $(LIBSQLITE) 47 -$(RM) $(INCFILES)
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/freebsd-10.0-release/contrib/libreadline/support/ |
H A D | shlib-install | 45 RM="rm -f" 51 ${echo} $RM ${INSTALLDIR}/${LIBNAME}.${OLDSUFF} 62 ${echo} ${RM} ${INSTALLDIR}/${LIBNAME} 80 ${echo} $RM ${BINDIR}/${LIBNAME}.${OLDSUFF} 89 ${echo} ${RM} ${BINDIR}/${LIBNAME} 90 ${echo} ${RM} ${INSTALLDIR}/${IMPLIBNAME} 121 ${echo} ${RM} ${INSTALLDIR}/$LINK2 127 ${echo} ${RM} ${INSTALLDIR}/$LINK1 135 ${echo} ${RM} ${INSTALLDIR}/$LINK2 141 ${echo} ${RM} [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZSubtarget.cpp | 31 // Return true if GV binds locally under reloc model RM. 32 static bool bindsLocally(const GlobalValue *GV, Reloc::Model RM) { argument 34 if (RM == Reloc::Static) 41 Reloc::Model RM, 50 return bindsLocally(GV, RM); 40 isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM, CodeModel::Model CM) const argument
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H A D | SystemZTargetMachine.cpp | 24 Reloc::Model RM, 27 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 21 SystemZTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-10.0-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcTargetMachine.cpp | 31 Reloc::Model RM, CodeModel::Model CM, 34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 82 Reloc::Model RM, 85 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { 94 Reloc::Model RM, 97 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { 28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument 78 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 90 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-10.0-release/contrib/bmake/mk/ |
H A D | autodep.mk | 73 RM?= rm macro 91 @${SHELL} -ec "${CC_MD} -M ${CPPFLAGS_MD} y.tab.c | sed '/:/s/^/$@ /' > $@" || { ${RM} -f y.tab.c $@; false; } 92 @${RM} -f y.tab.c 97 @${SHELL} -ec "${CC_MD} -M ${CPPFLAGS_MD} lex.yy.c | sed '/:/s/^/$@ /' > $@" || { ${RM} -f lex.yy.c $@; false; } 98 @${RM} -f lex.yy.c 102 @${SHELL} -ec "${CC_MD} -M ${CPPFLAGS_MD} $< | sed '/:/s/^/$@ /' > $@" || { ${RM} -f $@; false; } 106 @${SHELL} -ec "${CC_MD} -M ${CPPFLAGS_MD} ${AINC} $< | sed '/:/s/^/$@ /' > $@" || { ${RM} -f $@; false; } 110 @${SHELL} -ec "${CXX_MD} -M ${CXXFLAGS_MD} $< | sed '/:/s/^/$@ /' > $@" || { ${RM} -f $@; false; } 114 ${CC_MD} ${CFLAGS_MD:S/D//} ${CPPFLAGS_MD} y.tab.c > $@ || { ${RM} -f y.tab.c $@; false; } 115 ${RM} [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsELFStreamer.cpp | 62 Reloc::Model RM = Subtarget.getRelocationModel(); local 63 if (RM == Reloc::PIC_ || RM == Reloc::Default) 65 else if (RM == Reloc::Static)
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/freebsd-10.0-release/contrib/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCTargetDesc.cpp | 64 static MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument 71 CM = RM == Reloc::PIC_ ? CodeModel::Medium : CodeModel::Small; 73 X->InitMCCodeGenInfo(RM, CM, OL); 77 static MCCodeGenInfo *createSparcV9MCCodeGenInfo(StringRef TT, Reloc::Model RM, argument 86 X->InitMCCodeGenInfo(RM, CM, OL);
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/freebsd-10.0-release/contrib/gcclibs/libiberty/ |
H A D | makefile.vms | 31 $(RM) config.h; 32 $(RM) *.obj; 33 $(RM) libiberty.olb;
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/freebsd-10.0-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXTargetMachine.cpp | 71 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, 73 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 83 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, 85 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} 91 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, 93 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} 69 NVPTXTargetMachine( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument 81 NVPTXTargetMachine32( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 89 NVPTXTargetMachine64( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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H A D | NVPTXTargetMachine.h | 51 const TargetOptions &Options, Reloc::Model RM, 103 Reloc::Model RM, CodeModel::Model CM, 112 Reloc::Model RM, CodeModel::Model CM,
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/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCTargetMachine.cpp | 38 Reloc::Model RM, CodeModel::Model CM, 41 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 58 Reloc::Model RM, CodeModel::Model CM, 60 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { 68 Reloc::Model RM, CodeModel::Model CM, 70 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { 35 PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument 55 PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 65 PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-10.0-release/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCTargetDesc.cpp | 58 static MCCodeGenInfo *createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument 65 if (RM == Reloc::Default || RM == Reloc::DynamicNoPIC) 66 RM = Reloc::Static; 100 CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; 101 X->InitMCCodeGenInfo(RM, CM, OL);
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/freebsd-10.0-release/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430TargetMachine.cpp | 32 Reloc::Model RM, CodeModel::Model CM, 34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-10.0-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreTargetMachine.cpp | 26 Reloc::Model RM, CodeModel::Model CM, 28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 23 XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-10.0-release/crypto/heimdal/base/ |
H A D | NTMakefile | 53 -$(RM) $(INCFILES)
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/freebsd-10.0-release/contrib/llvm/lib/Target/XCore/MCTargetDesc/ |
H A D | XCoreMCTargetDesc.cpp | 65 static MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument 69 if (RM == Reloc::Default) { 70 RM = Reloc::Static; 72 X->InitMCCodeGenInfo(RM, CM, OL);
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/freebsd-10.0-release/contrib/ntp/scripts/ |
H A D | ntp-status | 12 RM=/bin/rm 23 trap '$RM -f $FILE; exit' 1 2 3 4 13 15 45 $RM -f $FILE
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/freebsd-10.0-release/contrib/pam_modules/pam_passwdqc/ |
H A D | Makefile | 7 RM = rm -f macro 45 $(RM) $(FAKEROOT)$(SECUREDIR)/$(TITLE).so 48 $(RM) $(PROJ) *.o
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/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsTargetMachine.cpp | 56 Reloc::Model RM, CodeModel::Model CM, 59 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 60 Subtarget(TT, CPU, FS, isLittle, RM, this), 117 Reloc::Model RM, CodeModel::Model CM, 119 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} 126 Reloc::Model RM, CodeModel::Model CM, 128 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} 54 MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument 115 MipsebTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 124 MipselTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-10.0-release/contrib/libreadline/examples/ |
H A D | Makefile.in | 22 RM = rm -f 51 ${RM} $@ 82 $(RM) $(OBJECTS) 83 $(RM) $(EXECUTABLES) *.exe 86 $(RM) Makefile
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/freebsd-10.0-release/contrib/llvm/lib/CodeGen/ |
H A D | LiveRangeEdit.cpp | 112 bool LiveRangeEdit::canRematerializeAt(Remat &RM, argument 118 if (!Remattable.count(RM.ParentVNI)) 123 if (RM.OrigMI) 124 DefIdx = LIS.getInstructionIndex(RM.OrigMI); 126 DefIdx = RM.ParentVNI->def; 127 RM.OrigMI = LIS.getInstructionFromIndex(DefIdx); 128 assert(RM.OrigMI && "No defining instruction for remattable value"); 132 if (cheapAsAMove && !RM.OrigMI->isAsCheapAsAMove()) 136 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) 145 const Remat &RM, 142 rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &tri, bool Late) argument [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86TargetMachine.cpp | 36 Reloc::Model RM, CodeModel::Model CM, 38 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false), 59 Reloc::Model RM, CodeModel::Model CM, 61 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true), 79 Reloc::Model RM, CodeModel::Model CM, 82 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 33 X86_32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 56 X86_64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 76 X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
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