Searched refs:OL (Results 1 - 25 of 56) sorted by relevance

123

/freebsd-10.0-release/contrib/llvm/lib/MC/
H A DMCCodeGenInfo.cpp19 CodeGenOpt::Level OL) {
22 OptLevel = OL;
18 InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/freebsd-10.0-release/contrib/llvm/lib/Target/Sparc/
H A DSparcTargetMachine.cpp32 CodeGenOpt::Level OL,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
84 CodeGenOpt::Level OL)
85 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
96 CodeGenOpt::Level OL)
97 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
78 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
90 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DSparcTargetMachine.h39 CodeGenOpt::Level OL, bool is64bit);
70 CodeGenOpt::Level OL);
82 CodeGenOpt::Level OL);
/freebsd-10.0-release/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXTargetMachine.cpp72 CodeGenOpt::Level OL, bool is64bit)
73 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
84 CodeGenOpt::Level OL)
85 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
92 CodeGenOpt::Level OL)
93 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
69 NVPTXTargetMachine( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
81 NVPTXTargetMachine32( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
89 NVPTXTargetMachine64( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCTargetMachine.cpp39 CodeGenOpt::Level OL,
41 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
59 CodeGenOpt::Level OL)
60 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
69 CodeGenOpt::Level OL)
70 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
35 PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
55 PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
65 PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DPPCTargetMachine.h44 CodeGenOpt::Level OL, bool is64Bit);
84 CodeGenOpt::Level OL);
95 CodeGenOpt::Level OL);
/freebsd-10.0-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430TargetMachine.cpp33 CodeGenOpt::Level OL)
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DMSP430TargetMachine.h44 CodeGenOpt::Level OL);
/freebsd-10.0-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZTargetMachine.cpp26 CodeGenOpt::Level OL)
27 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
21 SystemZTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/freebsd-10.0-release/contrib/llvm/lib/Target/XCore/
H A DXCoreTargetMachine.cpp27 CodeGenOpt::Level OL)
28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
23 XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DXCoreTargetMachine.h38 CodeGenOpt::Level OL);
/freebsd-10.0-release/contrib/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCTargetDesc.cpp66 CodeGenOpt::Level OL) {
73 X->InitMCCodeGenInfo(RM, CM, OL);
79 CodeGenOpt::Level OL) {
86 X->InitMCCodeGenInfo(RM, CM, OL);
64 createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
77 createSparcV9MCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/
H A DMipsTargetMachine.cpp57 CodeGenOpt::Level OL,
59 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
118 CodeGenOpt::Level OL)
119 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
127 CodeGenOpt::Level OL)
128 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
54 MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
115 MipsebTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
124 MipselTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DMipsTargetMachine.h53 CodeGenOpt::Level OL,
103 CodeGenOpt::Level OL);
114 CodeGenOpt::Level OL);
/freebsd-10.0-release/contrib/llvm/lib/Target/X86/
H A DX86TargetMachine.cpp37 CodeGenOpt::Level OL)
38 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
60 CodeGenOpt::Level OL)
61 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
80 CodeGenOpt::Level OL,
82 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
33 X86_32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
56 X86_64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
76 X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
H A DX86TargetMachine.h41 CodeGenOpt::Level OL,
90 CodeGenOpt::Level OL);
119 CodeGenOpt::Level OL);
/freebsd-10.0-release/contrib/llvm/include/llvm/MC/
H A DMCCodeGenInfo.h38 CodeGenOpt::Level OL = CodeGenOpt::Default);
/freebsd-10.0-release/contrib/llvm/lib/Target/CppBackend/
H A DCPPTargetMachine.h28 CodeGenOpt::Level OL)
25 CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64TargetMachine.cpp33 CodeGenOpt::Level OL)
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
29 AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DAArch64TargetMachine.h39 CodeGenOpt::Level OL);
/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCTargetDesc.cpp70 CodeGenOpt::Level OL) {
74 X->InitMCCodeGenInfo(Reloc::Static, CM, OL);
68 createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/freebsd-10.0-release/contrib/llvm/lib/Target/MBlaze/
H A DMBlazeTargetMachine.cpp38 CodeGenOpt::Level OL)
39 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 MBlazeTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/freebsd-10.0-release/contrib/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCTargetDesc.cpp55 CodeGenOpt::Level OL) {
57 X->InitMCCodeGenInfo(RM, CM, OL);
53 createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/freebsd-10.0-release/contrib/llvm/lib/Target/NVPTX/MCTargetDesc/
H A DNVPTXMCTargetDesc.cpp54 StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) {
56 X->InitMCCodeGenInfo(RM, CM, OL);
53 createNVPTXMCCodeGenInfo( StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/
H A DARMTargetMachine.h45 CodeGenOpt::Level OL);
80 CodeGenOpt::Level OL);
118 CodeGenOpt::Level OL);

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