| /freebsd-10.0-release/sys/contrib/dev/acpica/compiler/ |
| H A D | asltransform.c | 398 ACPI_PARSE_OBJECT *NewOp; local
457 NewOp = TrCreateLeafNode (PARSEOP_ELSE);
458 NewOp->Asl.Parent = Conditional->Asl.Parent;
459 TrAmlInitLineNumbers (NewOp, NewOp->Asl.Parent);
463 TrAmlInsertPeer (Conditional, NewOp);
464 CurrentParentNode = NewOp;
486 NewOp = NewOp2;
489 NewOp->Asl.Next = NewOp2;
492 NewOp
[all...] |
| H A D | aslopcodes.c | 671 ACPI_PARSE_OBJECT *NewOp; local
699 NewOp = TrAllocateNode (PARSEOP_INTEGER);
701 NewOp->Asl.AmlOpcode = AML_BYTE_OP;
702 NewOp->Asl.Value.Integer = 16;
703 NewOp->Asl.Parent = Op;
705 Op->Asl.Child = NewOp;
706 Op = NewOp;
710 NewOp = TrAllocateNode (PARSEOP_RAW_DATA);
711 NewOp->Asl.AmlOpcode = AML_RAW_DATA_BUFFER;
712 NewOp
[all...] |
| /freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPeephole.cpp | 258 int NewOp = QII->getInvertedPredicatedOpcode(MI->getOpcode()); local
259 MI->setDesc(QII->get(NewOp));
269 unsigned NewOp = 0; local
277 NewOp = Op;
280 NewOp = Hexagon::TFR_condset_ir;
283 NewOp = Hexagon::TFR_condset_ri;
286 NewOp = Hexagon::MUX_ir;
289 NewOp = Hexagon::MUX_ri;
292 if (NewOp) {
296 MI->setDesc(QII->get(NewOp));
[all...] |
| /freebsd-10.0-release/sys/contrib/dev/acpica/components/parser/ |
| H A D | psobject.c | 280 * NewOp - Returned Op
292 ACPI_PARSE_OBJECT **NewOp)
329 *NewOp = NamedOp;
381 WalkState->Op = *NewOp = Op;
289 AcpiPsCreateOp( ACPI_WALK_STATE *WalkState, UINT8 *AmlOpStart, ACPI_PARSE_OBJECT **NewOp) argument
|
| /freebsd-10.0-release/sys/contrib/dev/acpica/include/ |
| H A D | acparser.h | 145 ACPI_PARSE_OBJECT **NewOp);
|
| /freebsd-10.0-release/contrib/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 1216 Value *NewOp = Builder->CreateAnd(Op0COp, Op1COp, I.getName()); local
1217 return CastInst::Create(Op0C->getOpcode(), NewOp, I.getType());
1242 Value *NewOp = local
1245 return BinaryOperator::Create(SI1->getOpcode(), NewOp,
1749 Value *NewOp = Builder->CreateAnd((V1 == A) ? B : A, CI1); local
1750 return BinaryOperator::CreateOr(NewOp, V1);
1951 Value *NewOp = Builder->CreateOr(SI0->getOperand(0), SI1->getOperand(0), local
1953 return BinaryOperator::Create(SI1->getOpcode(), NewOp,
2036 Value *NewOp = Builder->CreateOr(Op0COp, Op1COp, I.getName()); local
2037 return CastInst::Create(Op0C->getOpcode(), NewOp,
2297 Value *NewOp = local
2349 Value *NewOp = Builder->CreateXor(Op0C->getOperand(0), local
[all...] |
| /freebsd-10.0-release/contrib/llvm/include/llvm/Analysis/ |
| H A D | ScalarEvolution.h | 623 SmallVector<const SCEV *, 4> NewOp(Operands.begin(), Operands.end());
624 return getAddRecExpr(NewOp, L, Flags);
|
| /freebsd-10.0-release/contrib/llvm/lib/Transforms/Scalar/ |
| H A D | Reassociate.cpp | 803 BinaryOperator *NewOp; local
806 NewOp = BinaryOperator::Create(Instruction::BinaryOps(Opcode),
809 NewOp = NodesToRewrite.pop_back_val();
813 Op->setOperand(0, NewOp);
818 Op = NewOp;
|
| /freebsd-10.0-release/contrib/llvm/lib/TableGen/ |
| H A D | Record.cpp | 1050 const OpInit *NewOp = RHSo->clone(NewOperands); local
1051 Init *NewVal = NewOp->Fold(CurRec, CurMultiClass);
1052 if (NewVal != NewOp)
1123 const OpInit *NewOp = RHSo->clone(NewOperands); local
1124 Init *NewItem = NewOp->Fold(CurRec, CurMultiClass);
1125 if (NewItem != NewOp)
|
| /freebsd-10.0-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 6276 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG); local
6277 if (NewOp.getNode())
6278 return NewOp;
6753 SDValue NewOp = LowerVectorIntExtend(Op, DAG); local
6754 if (NewOp.getNode())
6755 return NewOp;
6761 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG); local
6762 if (NewOp.getNode())
6763 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6769 SDValue NewOp local
6778 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG); local
6833 SDValue NewOp = NormalizeVectorShuffle(Op, DAG); local
7076 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG); local
7082 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); local
7088 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG); local
12460 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, SelectionDAG &DAG, unsigned NewOp) argument
15273 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI); local
17364 unsigned NewOp = 0; local
[all...] |
| /freebsd-10.0-release/contrib/llvm/lib/Bitcode/Reader/ |
| H A D | BitcodeReader.cpp | 330 Value *NewOp; local
333 NewOp = *I;
336 NewOp = RealVal;
344 NewOp = operator[](It->second);
347 NewOps.push_back(cast<Constant>(NewOp));
|
| /freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 135 SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0)); local
137 NewOp.getValueType().getVectorElementType(),
138 NewOp, N->getOperand(1));
|
| H A D | DAGCombiner.cpp | 772 SDValue NewOp = PromoteOperand(Op, PVT, Replace); local
773 if (NewOp.getNode() == 0)
775 AddToWorkList(NewOp.getNode());
778 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
779 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
787 SDValue NewOp = PromoteOperand(Op, PVT, Replace); local
788 if (NewOp.getNode() == 0)
790 AddToWorkList(NewOp.getNode());
793 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp
[all...] |
| /freebsd-10.0-release/contrib/llvm/lib/Transforms/Vectorize/ |
| H A D | BBVectorize.cpp | 2569 Instruction *NewOp = local
2572 NewOp->insertBefore(IBeforeJ ? J : I);
2573 return NewOp;
|
| /freebsd-10.0-release/contrib/llvm/lib/Analysis/ |
| H A D | ScalarEvolution.cpp | 1323 const SCEV *NewOp = T->getOperand(); local
1324 if (getTypeSizeInBits(NewOp->getType()) < getTypeSizeInBits(Ty))
1325 return getAnyExtendExpr(NewOp, Ty);
1326 return getTruncateOrNoop(NewOp, Ty);
|
| /freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 5133 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG); local
5134 if (NewOp.getNode())
5135 return NewOp;
5671 SelectionDAG &DAG, unsigned NewOp) {
5685 if (NewOp == ARMISD::ATOMCMPXCHG64_DAG) {
5695 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64,
5670 ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results, SelectionDAG &DAG, unsigned NewOp) argument
|