/freebsd-10.0-release/contrib/llvm/include/llvm/Target/ |
H A D | TargetOpcodes.h | 47 /// defined by an IMPLICIT_DEF, because it is commonly used to implement 51 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 52 IMPLICIT_DEF = 8, enumerator in enum:llvm::TargetOpcode::__anon2045
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H A D | TargetInstrInfo.h | 70 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
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/freebsd-10.0-release/contrib/llvm/lib/CodeGen/ |
H A D | ProcessImplicitDefs.cpp | 25 /// Process IMPLICIT_DEF instructions and make sure there is one implicit_def 91 DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI); 92 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); 121 // If we found the using MI, we can erase the IMPLICIT_DEF. 129 // Leave the physreg IMPLICIT_DEF, but trim any extra operands. 135 /// processImplicitDefs - Process IMPLICIT_DEF instructions and turn them into
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H A D | MachineSSAUpdater.cpp | 108 /// InsertNewDef - Insert an empty PHI or IMPLICIT_DEF instruction which define 149 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, 291 /// GetUndefVal - Create an IMPLICIT_DEF instruction with a new register. 296 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF,
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H A D | PHIElimination.cpp | 151 // Remove dead IMPLICIT_DEF instructions. 244 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg); 382 // Insert an IMPLICIT_DEF instruction. 384 TII->get(TargetOpcode::IMPLICIT_DEF),
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H A D | TwoAddressInstructionPass.cpp | 1670 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF"); 1671 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
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/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ResourcePriorityQueue.cpp | 268 case TargetOpcode::IMPLICIT_DEF: 308 case TargetOpcode::IMPLICIT_DEF: 555 if (N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
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H A D | InstrEmitter.cpp | 211 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 212 "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 270 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 271 // Add an IMPLICIT_DEF instruction before every use. 273 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc 281 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 713 if (Opc == TargetOpcode::IMPLICIT_DEF) 714 // We want a unique VR for each IMPLICIT_DEF use.
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H A D | ScheduleDAGSDNodes.cpp | 82 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)) 539 if (POpc == TargetOpcode::IMPLICIT_DEF) {
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H A D | FastISel.cpp | 234 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
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H A D | ScheduleDAGRRList.cpp | 2121 Opc == TargetOpcode::IMPLICIT_DEF) 2144 if (POpc == TargetOpcode::IMPLICIT_DEF)
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H A D | SelectionDAGISel.cpp | 1619 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
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/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.cpp | 210 MInst->getOpcode() == TargetOpcode::IMPLICIT_DEF) {
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H A D | HexagonMachineScheduler.cpp | 57 case TargetOpcode::IMPLICIT_DEF: 109 case TargetOpcode::IMPLICIT_DEF:
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/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCCodeEmitter.cpp | 125 case TargetOpcode::IMPLICIT_DEF:
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/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | MachineInstr.h | 643 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; } 695 case TargetOpcode::IMPLICIT_DEF:
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/freebsd-10.0-release/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.cpp | 301 case TargetOpcode::IMPLICIT_DEF:
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/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 267 // See if the first operand of this insert_subreg is IMPLICIT_DEF 301 // See if all bar one of the operands are IMPLICIT_DEF and insert the 526 TII->get(TargetOpcode::IMPLICIT_DEF), Out);
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H A D | ARMISelDAGToDAG.cpp | 1774 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0); 1884 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) 1931 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) 2049 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) 2184 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
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H A D | ARMCodeEmitter.cpp | 871 case TargetOpcode::IMPLICIT_DEF:
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/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.cpp | 579 case TargetOpcode::IMPLICIT_DEF:
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/freebsd-10.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86CodeEmitter.cpp | 1194 case TargetOpcode::IMPLICIT_DEF:
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H A D | X86FloatingPoint.cpp | 1398 case TargetOpcode::IMPLICIT_DEF: {
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/freebsd-10.0-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 1151 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64); 2026 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
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/freebsd-10.0-release/contrib/llvm/lib/CodeGen/AsmPrinter/ |
H A D | AsmPrinter.cpp | 704 case TargetOpcode::IMPLICIT_DEF:
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