1203954Srdivacky//===-- llvm/Target/TargetOpcodes.h - Target Indep Opcodes ------*- C++ -*-===// 2203954Srdivacky// 3203954Srdivacky// The LLVM Compiler Infrastructure 4203954Srdivacky// 5203954Srdivacky// This file is distributed under the University of Illinois Open Source 6203954Srdivacky// License. See LICENSE.TXT for details. 7203954Srdivacky// 8203954Srdivacky//===----------------------------------------------------------------------===// 9203954Srdivacky// 10203954Srdivacky// This file defines the target independent instruction opcodes. 11203954Srdivacky// 12203954Srdivacky//===----------------------------------------------------------------------===// 13203954Srdivacky 14203954Srdivacky#ifndef LLVM_TARGET_TARGETOPCODES_H 15203954Srdivacky#define LLVM_TARGET_TARGETOPCODES_H 16203954Srdivacky 17203954Srdivackynamespace llvm { 18210299Sed 19204642Srdivacky/// Invariant opcodes: All instruction sets have these as their low opcodes. 20210299Sed/// 21210299Sed/// Every instruction defined here must also appear in Target.td and the order 22210299Sed/// must be the same as in CodeGenTarget.cpp. 23210299Sed/// 24203954Srdivackynamespace TargetOpcode { 25210299Sed enum { 26203954Srdivacky PHI = 0, 27203954Srdivacky INLINEASM = 1, 28212904Sdim PROLOG_LABEL = 2, 29203954Srdivacky EH_LABEL = 3, 30203954Srdivacky GC_LABEL = 4, 31210299Sed 32203954Srdivacky /// KILL - This instruction is a noop that is used only to adjust the 33203954Srdivacky /// liveness of registers. This can be useful when dealing with 34203954Srdivacky /// sub-registers. 35203954Srdivacky KILL = 5, 36210299Sed 37203954Srdivacky /// EXTRACT_SUBREG - This instruction takes two operands: a register 38203954Srdivacky /// that has subregisters, and a subregister index. It returns the 39203954Srdivacky /// extracted subregister value. This is commonly used to implement 40203954Srdivacky /// truncation operations on target architectures which support it. 41203954Srdivacky EXTRACT_SUBREG = 6, 42210299Sed 43210299Sed /// INSERT_SUBREG - This instruction takes three operands: a register that 44210299Sed /// has subregisters, a register providing an insert value, and a 45210299Sed /// subregister index. It returns the value of the first register with the 46210299Sed /// value of the second register inserted. The first register is often 47210299Sed /// defined by an IMPLICIT_DEF, because it is commonly used to implement 48203954Srdivacky /// anyext operations on target architectures which support it. 49203954Srdivacky INSERT_SUBREG = 7, 50210299Sed 51203954Srdivacky /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 52203954Srdivacky IMPLICIT_DEF = 8, 53210299Sed 54210299Sed /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that 55210299Sed /// the first operand is an immediate integer constant. This constant is 56210299Sed /// often zero, because it is commonly used to assert that the instruction 57210299Sed /// defining the register implicitly clears the high bits. 58203954Srdivacky SUBREG_TO_REG = 9, 59210299Sed 60203954Srdivacky /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 61203954Srdivacky /// register-to-register copy into a specific register class. This is only 62203954Srdivacky /// used between instruction selection and MachineInstr creation, before 63203954Srdivacky /// virtual registers have been created for all the instructions, and it's 64203954Srdivacky /// only needed in cases where the register classes implied by the 65210299Sed /// instructions are insufficient. It is emitted as a COPY MachineInstr. 66203954Srdivacky COPY_TO_REGCLASS = 10, 67207618Srdivacky 68204642Srdivacky /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 69207618Srdivacky DBG_VALUE = 11, 70207618Srdivacky 71207618Srdivacky /// REG_SEQUENCE - This variadic instruction is used to form a register that 72207618Srdivacky /// represent a consecutive sequence of sub-registers. It's used as register 73207618Srdivacky /// coalescing / allocation aid and must be eliminated before code emission. 74224145Sdim // In SDNode form, the first operand encodes the register class created by 75224145Sdim // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 76224145Sdim // pair. Once it has been lowered to a MachineInstr, the regclass operand 77224145Sdim // is no longer present. 78207618Srdivacky /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 79207618Srdivacky /// After register coalescing references of v1024 should be replace with 80207618Srdivacky /// v1027:3, v1025 with v1027:4, etc. 81210299Sed REG_SEQUENCE = 12, 82210299Sed 83210299Sed /// COPY - Target-independent register copy. This instruction can also be 84210299Sed /// used to copy between subregisters of virtual registers. 85234353Sdim COPY = 13, 86234353Sdim 87234353Sdim /// BUNDLE - This instruction represents an instruction bundle. Instructions 88234353Sdim /// which immediately follow a BUNDLE instruction which are marked with 89234353Sdim /// 'InsideBundle' flag are inside the bundle. 90243830Sdim BUNDLE = 14, 91243830Sdim 92243830Sdim /// Lifetime markers. 93243830Sdim LIFETIME_START = 15, 94243830Sdim LIFETIME_END = 16 95203954Srdivacky }; 96203954Srdivacky} // end namespace TargetOpcode 97203954Srdivacky} // end namespace llvm 98203954Srdivacky 99203954Srdivacky#endif 100