Searched refs:vram_start (Results 1 - 18 of 18) sorted by relevance

/freebsd-10-stable/sys/dev/drm2/radeon/
H A Dradeon_test.c97 void **vram_start, **vram_end; local
152 vram_start = vram_map, vram_end = (void *)((uintptr_t)vram_map + size);
153 vram_start < vram_end;
154 gtt_start++, vram_start++) {
155 if (*vram_start != gtt_start) {
159 i, *vram_start, gtt_start,
164 ((uintptr_t)vram_addr - (uintptr_t)rdev->mc.vram_start +
169 *vram_start = vram_start;
198 vram_start
[all...]
H A Dr520.c152 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
155 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
H A Dradeon_device.c361 mc->vram_start = base;
367 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
368 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
373 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
377 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start,
398 size_bf = mc->vram_start & ~mc->gtt_base_align;
404 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
H A Drv770.c269 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
272 rdev->mc.vram_start >> 12);
284 rdev->mc.vram_start >> 12);
290 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
292 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
828 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
835 mc->vram_start = mc->gtt_end + 1;
837 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
839 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start,
H A Drv515.c384 upper_32_bits(rdev->mc.vram_start));
386 upper_32_bits(rdev->mc.vram_start));
389 upper_32_bits(rdev->mc.vram_start));
391 upper_32_bits(rdev->mc.vram_start));
395 (u32)rdev->mc.vram_start);
397 (u32)rdev->mc.vram_start);
399 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
477 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
480 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
H A Dradeon_fb.c245 tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
H A Dradeon_ttm.c162 man->gpu_offset = rdev->mc.vram_start;
237 old_start += rdev->mc.vram_start;
248 new_start += rdev->mc.vram_start;
H A Drs600.c543 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
897 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
900 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
H A Devergreen.c1448 upper_32_bits(rdev->mc.vram_start));
1450 upper_32_bits(rdev->mc.vram_start));
1452 (u32)rdev->mc.vram_start);
1454 (u32)rdev->mc.vram_start);
1456 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1457 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1547 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1550 rdev->mc.vram_start >> 12);
1562 rdev->mc.vram_start >> 12);
1573 tmp |= ((rdev->mc.vram_start >> 2
[all...]
H A Dr600.c1059 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1062 rdev->mc.vram_start >> 12);
1073 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1078 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1080 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1141 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1148 mc->vram_start = mc->gtt_end + 1;
1150 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1152 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start,
H A Drs400.c386 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
H A Drs690.c594 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
597 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
H A Dsi.c2337 rdev->mc.vram_start >> 12);
2343 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2346 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2365 mc->vram_start = base;
2371 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2373 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start,
2382 size_bf = mc->vram_start & ~mc->gtt_base_align;
2388 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
H A Dradeon_object.c236 domain_start = bo->rdev->mc.vram_start;
H A Dr300.c141 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
1334 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
H A Dradeon_legacy_crtc.c446 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
H A Dr100.c3896 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3898 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3951 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
H A Dradeon.h518 u64 vram_start; member in struct:radeon_mc

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