Searched refs:gart (Results 1 - 12 of 12) sorted by relevance

/freebsd-10-stable/sys/dev/drm2/radeon/
H A Dradeon_gart.c61 * radeon_gart_table_ram_alloc - allocate system ram for gart page table
67 * gart table to be in system memory.
74 dmah = drm_pci_alloc(rdev->ddev, rdev->gart.table_size,
79 rdev->gart.dmah = dmah;
80 rdev->gart.ptr = dmah->vaddr;
84 pmap_change_attr((vm_offset_t)rdev->gart.ptr,
85 rdev->gart.table_size >> PAGE_SHIFT, PAT_UNCACHED);
88 rdev->gart.table_addr = dmah->busaddr;
89 memset((void *)rdev->gart.ptr, 0, rdev->gart
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H A Drs400.c42 /* Check gart size */
82 if (rdev->gart.ptr) {
86 /* Check gart size */
99 /* Initialize common gart structure */
105 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
118 /* Check gart size */
164 tmp = (u32)rdev->gart.table_addr & 0xfffff000;
165 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
184 /* Enable gart */
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H A Dradeon_asic.c136 * Removes AGP flags and changes the gart callbacks on AGP
137 * cards when using the internal gart rather than AGP (all asics).
151 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
152 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
156 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
157 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
175 .gart = {
251 .gart = {
327 .gart = {
403 .gart
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H A Drs600.c481 if (rdev->gart.robj) {
485 /* Initialize common gart structure */
490 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
499 if (rdev->gart.robj == NULL) {
537 rdev->gart.table_addr);
554 (unsigned long long)rdev->gart.table_addr);
555 rdev->gart.ready = true;
563 /* FIXME: disable out of gart access */
585 uint64_t *ptr = rdev->gart
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H A Dr300.c79 volatile uint32_t *ptr = rdev->gart.ptr;
81 if (i < 0 || i > rdev->gart.num_gpu_pages) {
99 if (rdev->gart.robj) {
103 /* Initialize common gart structure */
109 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
110 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
111 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
112 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
122 if (rdev->gart
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H A Drv770.c135 if (rdev->gart.robj == NULL) {
165 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
176 (unsigned long long)rdev->gart.table_addr);
177 rdev->gart.ready = true;
H A Dni.c805 if (rdev->gart.robj == NULL) {
833 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
853 rdev->gart.table_addr >> 12);
877 (unsigned long long)rdev->gart.table_addr);
878 rdev->gart.ready = true;
927 /* flush read cache over gart for this vmid */
971 /* flush read cache over gart for this vmid */
H A Dr100.c653 if (rdev->gart.ptr) {
657 /* Initialize common gart structure */
661 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
662 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
663 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
679 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
685 (unsigned long long)rdev->gart.table_addr);
686 rdev->gart.ready = true;
703 u32 *gtt = rdev->gart
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H A Dradeon.h41 * - r600/r700: gart & cp
44 * - Barrier in gart code
1190 /* gart */
1194 } gart; member in struct:radeon_asic
1600 struct radeon_gart gart; member in struct:radeon_device
1826 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1827 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
H A Dr600.c842 volatile uint32_t *ptr = rdev->gart.ptr;
877 if (rdev->gart.robj) {
881 /* Initialize common gart structure */
885 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
894 if (rdev->gart.robj == NULL) {
930 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
941 (unsigned long long)rdev->gart.table_addr);
942 rdev->gart.ready = true;
2567 /* flush read cache over gart */
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H A Dsi.c1802 /* flush read cache over gart */
1868 /* flush read cache over gart for this vmid */
2491 if (rdev->gart.robj == NULL) {
2518 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2540 rdev->gart.table_addr >> 12);
2543 rdev->gart.table_addr >> 12);
2567 (unsigned long long)rdev->gart.table_addr);
2568 rdev->gart.ready = true;
H A Devergreen.c1243 if (rdev->gart.robj == NULL) {
1282 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1292 (unsigned long long)rdev->gart.table_addr);
1293 rdev->gart.ready = true;

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