/freebsd-10-stable/contrib/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.cpp | 1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===// 10 // This file contains the X86 implementation of the TargetRegisterInfo class. 12 // on X86. 17 #include "X86.h" 59 ? X86::RIP : X86::EIP), 63 ? X86::RIP : X86::EIP)), 74 StackPtr = X86::RSP; 75 FramePtr = X86 [all...] |
H A D | X86InstrInfo.cpp | 1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===// 10 // This file contains the X86 implementation of the TargetInstrInfo class. 15 #include "X86.h" 50 " fuse, but the X86 backend currently can't"), 100 ? X86::ADJCALLSTACKDOWN64 101 : X86::ADJCALLSTACKDOWN32), 103 ? X86::ADJCALLSTACKUP64 104 : X86::ADJCALLSTACKUP32)), 108 { X86::ADC32ri, X86 [all...] |
H A D | X86FloatingPoint.cpp | 27 #include "X86.h" 72 virtual const char *getPassName() const { return "X86 FP Stackifier"; } 119 if (Reg < X86::FP0 || Reg > X86::FP6) 121 Mask |= 1 << (Reg - X86::FP0); 214 /// getStackEntry - Return the X86::FP<n> register in register ST(i). 221 /// getSTReg - Return the X86::ST(i) register which contains the specified 224 return StackTop - 1 - getSlot(RegNo) + X86::ST0; 253 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); 262 BuildMI(*MBB, I, dl, TII->get(X86 [all...] |
H A D | X86MCInstLower.cpp | 1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===// 10 // This file contains code to lower X86 MachineInstrs to their corresponding 249 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 267 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw 268 if (Op0 == X86::AX && Op1 == X86::AL) 269 NewOpcode = X86 [all...] |
H A D | X86Relocations.h | 1 //===-- X86Relocations.h - X86 Code Relocations -----------------*- C++ -*-===// 10 // This file defines the X86 target-specific relocation types. 20 namespace X86 { namespace in namespace:llvm
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H A D | X86FrameLowering.cpp | 1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===// 10 // This file contains the X86 implementation of TargetFrameLowering class. 61 return X86::SUB64ri8; 62 return X86::SUB64ri32; 65 return X86::SUB32ri8; 66 return X86::SUB32ri; 73 return X86::ADD64ri8; 74 return X86::ADD64ri32; 77 return X86::ADD32ri8; 78 return X86 [all...] |
H A D | X86Subtarget.cpp | 1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===// 10 // This file implements the X86 specific subclass of TargetSubtargetInfo. 68 // X86-64 in PIC mode. 207 if ((EDX >> 15) & 1) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); } 208 if ((EDX >> 23) & 1) { X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); } 209 if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); } 210 if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); } 211 if (ECX & 0x1) { X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); } 212 if ((ECX >> 9) & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);} 213 if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86 [all...] |
H A D | X86FixupLEAs.cpp | 17 #include "X86.h" 42 virtual const char *getPassName() const { return "X86 Atom LEA Fixup";} 100 case X86::MOV32rr: 101 case X86::MOV64rr: { 105 TII->get( MI->getOpcode() == X86::MOV32rr ? X86::LEA32r : X86::LEA64r)) 111 case X86::ADD64ri32: 112 case X86::ADD64ri8: 113 case X86 [all...] |
H A D | X86FastISel.cpp | 1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===// 10 // This file defines the X86-specific support for the FastISel class. Much 16 #include "X86.h" 191 Opc = X86::MOV8rm; 192 RC = &X86::GR8RegClass; 195 Opc = X86::MOV16rm; 196 RC = &X86::GR16RegClass; 199 Opc = X86::MOV32rm; 200 RC = &X86::GR32RegClass; 204 Opc = X86 [all...] |
H A D | X86ISelDAGToDAG.cpp | 1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===// 10 // This file defines a DAG pattern matching instruction selector for X86, 11 // converting from a legalized dag to a X86 dag. 16 #include "X86.h" 92 return RegNode->getReg() == X86::RIP; 141 /// ISel - X86 specific code to select X86 machine instructions for 160 return "X86 DAG->DAG Instruction Selection"; 497 // late" legalization of these inline with the X86 isel pass. 570 Subtarget->is64Bit() ? X86 [all...] |
/freebsd-10-stable/contrib/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86AsmBackend.cpp | 1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===// 36 cl::desc("Disable relaxation of arithmetic instruction for X86")); 48 case X86::reloc_riprel_4byte: 49 case X86::reloc_riprel_4byte_movq_load: 50 case X86::reloc_signed_4byte: 51 case X86::reloc_global_offset_table: 83 return X86::NumTargetFixupKinds; 87 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = { 138 case X86::JAE_1: return X86 [all...] |
H A D | X86BaseInfo.h | 1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// 11 // the X86 target useful for the compiler back-end and the MC libraries. 27 namespace X86 { namespace in namespace:llvm 44 } // end namespace X86; 53 // X86 Specific MachineOperand flags. 70 /// See the X86-64 ELF ABI supplement for more details. 77 /// See the X86-64 ELF ABI supplement for more details. 85 /// See the X86-64 ELF ABI supplement for more details. 92 /// See the X86-64 ELF ABI supplement for more details. 221 // Instruction encodings. These are the standard/most common forms for X86 [all...] |
H A D | X86FixupKinds.h | 1 //===-- X86FixupKinds.h - X86 Specific Fixup Entries ------------*- C++ -*-===// 16 namespace X86 { namespace in namespace:llvm
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/freebsd-10-stable/contrib/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86InstComments.cpp | 10 // This defines functionality used to emit comments about X86 instructions to 36 case X86::INSERTPSrr: 37 case X86::VINSERTPSrr: 44 case X86::MOVLHPSrr: 45 case X86::VMOVLHPSrr: 52 case X86::MOVHLPSrr: 53 case X86::VMOVHLPSrr: 60 case X86::PALIGNR128rr: 61 case X86::VPALIGNR128rr: 64 case X86 [all...] |
/freebsd-10-stable/lib/clang/include/llvm/Config/ |
H A D | Disassemblers.def | 6 LLVM_DISASSEMBLER(X86)
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H A D | AsmParsers.def | 7 LLVM_ASM_PARSER(X86)
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H A D | AsmPrinters.def | 7 LLVM_ASM_PRINTER(X86)
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H A D | Targets.def | 7 LLVM_TARGET(X86)
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/freebsd-10-stable/lib/clang/libllvmx86utils/ |
H A D | Makefile | 7 SRCDIR= lib/Target/X86/Utils 8 INCDIR= lib/Target/X86
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/freebsd-10-stable/lib/clang/libllvmx86asmparser/ |
H A D | Makefile | 7 SRCDIR= lib/Target/X86/AsmParser 8 INCDIR= lib/Target/X86
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/freebsd-10-stable/lib/clang/libllvmx86disassembler/ |
H A D | Makefile | 7 SRCDIR= lib/Target/X86/Disassembler 8 INCDIR= lib/Target/X86
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/freebsd-10-stable/lib/clang/libllvmx86info/ |
H A D | Makefile | 7 SRCDIR= lib/Target/X86/TargetInfo 8 INCDIR= lib/Target/X86
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/freebsd-10-stable/lib/clang/libllvmx86instprinter/ |
H A D | Makefile | 7 SRCDIR= lib/Target/X86/InstPrinter 8 INCDIR= lib/Target/X86
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/freebsd-10-stable/contrib/llvm/lib/Target/X86/Disassembler/ |
H A D | X86Disassembler.cpp | 10 // This file is part of the X86 Disassembler. 56 namespace X86 { namespace in namespace:llvm 159 #define ENTRY(x) X86::x, 249 // By default sign-extend all X86 immediates based on their encoding. 257 // Special case those X86 instructions that use the imm8 as a set of 259 if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri && 260 Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri && 261 Opcode != X86 [all...] |
/freebsd-10-stable/contrib/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===// 539 return (STI.getFeatureBits() & X86::Mode64Bit) != 0; 542 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit)); 610 /// X86Operand - Instances of this class represent a parsed X86 machine 825 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15; 829 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15; 833 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86 [all...] |