Lines Matching refs:X86
1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
16 #include "X86.h"
191 Opc = X86::MOV8rm;
192 RC = &X86::GR8RegClass;
195 Opc = X86::MOV16rm;
196 RC = &X86::GR16RegClass;
199 Opc = X86::MOV32rm;
200 RC = &X86::GR32RegClass;
204 Opc = X86::MOV64rm;
205 RC = &X86::GR64RegClass;
209 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
210 RC = &X86::FR32RegClass;
212 Opc = X86::LD_Fp32m;
213 RC = &X86::RFP32RegClass;
218 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
219 RC = &X86::FR64RegClass;
221 Opc = X86::LD_Fp64m;
222 RC = &X86::RFP64RegClass;
250 unsigned AndResult = createResultReg(&X86::GR8RegClass);
252 TII.get(X86::AND8ri), AndResult).addReg(ValReg).addImm(1);
256 case MVT::i8: Opc = X86::MOV8mr; break;
257 case MVT::i16: Opc = X86::MOV16mr; break;
258 case MVT::i32: Opc = X86::MOV32mr; break;
259 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
262 (Subtarget->hasAVX() ? X86::VMOVSSmr : X86::MOVSSmr) : X86::ST_Fp32m;
266 (Subtarget->hasAVX() ? X86::VMOVSDmr : X86::MOVSDmr) : X86::ST_Fp64m;
270 Opc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
272 Opc = Subtarget->hasAVX() ? X86::VMOVUPSmr : X86::MOVUPSmr;
276 Opc = Subtarget->hasAVX() ? X86::VMOVAPDmr : X86::MOVAPDmr;
278 Opc = Subtarget->hasAVX() ? X86::VMOVUPDmr : X86::MOVUPDmr;
285 Opc = Subtarget->hasAVX() ? X86::VMOVDQAmr : X86::MOVDQAmr;
287 Opc = Subtarget->hasAVX() ? X86::VMOVDQUmr : X86::MOVDQUmr;
309 case MVT::i8: Opc = X86::MOV8mi; break;
310 case MVT::i16: Opc = X86::MOV16mi; break;
311 case MVT::i32: Opc = X86::MOV32mi; break;
315 Opc = X86::MOV64mi32;
394 AM.Base.Reg = X86::RIP;
419 Opc = X86::MOV64rm;
420 RC = &X86::GR64RegClass;
423 StubAM.Base.Reg = X86::RIP;
425 Opc = X86::MOV32rm;
426 RC = &X86::GR32RegClass;
651 // method, which is not guarantee for X86.
717 AM.Base.Reg = X86::RIP;
833 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
847 assert(DstVT == MVT::i32 && "X86 should always ext to i32");
883 unsigned RetReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
891 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET));
927 case MVT::i8: return X86::CMP8rr;
928 case MVT::i16: return X86::CMP16rr;
929 case MVT::i32: return X86::CMP32rr;
930 case MVT::i64: return X86::CMP64rr;
932 return X86ScalarSSEf32 ? (HasAVX ? X86::VUCOMISSrr : X86::UCOMISSrr) : 0;
934 return X86ScalarSSEf64 ? (HasAVX ? X86::VUCOMISDrr : X86::UCOMISDrr) : 0;
945 case MVT::i8: return X86::CMP8ri;
946 case MVT::i16: return X86::CMP16ri;
947 case MVT::i32: return X86::CMP32ri;
952 return X86::CMP64ri32;
997 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
1005 unsigned EReg = createResultReg(&X86::GR8RegClass);
1006 unsigned NPReg = createResultReg(&X86::GR8RegClass);
1007 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETEr), EReg);
1009 TII.get(X86::SETNPr), NPReg);
1011 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
1019 unsigned NEReg = createResultReg(&X86::GR8RegClass);
1020 unsigned PReg = createResultReg(&X86::GR8RegClass);
1021 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETNEr), NEReg);
1022 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETPr), PReg);
1023 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::OR8rr),ResultReg)
1028 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
1029 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
1030 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
1031 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
1032 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
1033 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
1034 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
1035 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
1036 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
1037 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
1038 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
1039 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
1041 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
1042 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
1043 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
1044 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
1045 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
1046 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
1047 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
1048 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
1049 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
1050 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
1093 case MVT::i8: MovInst = X86::MOVZX32rr8; break;
1094 case MVT::i16: MovInst = X86::MOVZX32rr16; break;
1095 case MVT::i32: MovInst = X86::MOV32rr; break;
1099 unsigned Result32 = createResultReg(&X86::GR32RegClass);
1103 ResultReg = createResultReg(&X86::GR64RegClass);
1106 .addImm(0).addReg(Result32).addImm(X86::sub_32bit);
1141 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
1148 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1149 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
1150 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
1151 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break;
1152 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break;
1153 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1154 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break;
1155 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break;
1156 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
1157 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break;
1158 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break;
1159 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
1160 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
1162 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
1163 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1164 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
1165 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
1166 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
1167 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
1168 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break;
1169 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break;
1170 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break;
1171 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break;
1188 // X86 requires a second branch to handle UNE (and OEQ,
1190 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JP_4))
1207 case MVT::i8: TestOpc = X86::TEST8ri; break;
1208 case MVT::i16: TestOpc = X86::TEST16ri; break;
1209 case MVT::i32: TestOpc = X86::TEST32ri; break;
1210 case MVT::i64: TestOpc = X86::TEST64ri32; break;
1218 unsigned JmpOpc = X86::JNE_4;
1221 JmpOpc = X86::JE_4;
1239 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8ri))
1241 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JNE_4))
1252 CReg = X86::CL;
1253 RC = &X86::GR8RegClass;
1255 case Instruction::LShr: OpReg = X86::SHR8rCL; break;
1256 case Instruction::AShr: OpReg = X86::SAR8rCL; break;
1257 case Instruction::Shl: OpReg = X86::SHL8rCL; break;
1261 CReg = X86::CX;
1262 RC = &X86::GR16RegClass;
1264 case Instruction::LShr: OpReg = X86::SHR16rCL; break;
1265 case Instruction::AShr: OpReg = X86::SAR16rCL; break;
1266 case Instruction::Shl: OpReg = X86::SHL16rCL; break;
1270 CReg = X86::ECX;
1271 RC = &X86::GR32RegClass;
1273 case Instruction::LShr: OpReg = X86::SHR32rCL; break;
1274 case Instruction::AShr: OpReg = X86::SAR32rCL; break;
1275 case Instruction::Shl: OpReg = X86::SHL32rCL; break;
1279 CReg = X86::RCX;
1280 RC = &X86::GR64RegClass;
1282 case Instruction::LShr: OpReg = X86::SHR64rCL; break;
1283 case Instruction::AShr: OpReg = X86::SAR64rCL; break;
1284 case Instruction::Shl: OpReg = X86::SHL64rCL; break;
1303 // The shift instruction uses X86::CL. If we defined a super-register
1304 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
1305 if (CReg != X86::CL)
1307 TII.get(TargetOpcode::KILL), X86::CL)
1323 // For the X86 DIV/IDIV instruction, in most cases the dividend
1348 { &X86::GR8RegClass, X86::AX, 0, {
1349 { X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AL, S }, // SDiv
1350 { X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AH, S }, // SRem
1351 { X86::DIV8r, 0, X86::MOVZX16rr8, X86::AL, U }, // UDiv
1352 { X86::DIV8r, 0, X86::MOVZX16rr8, X86::AH, U }, // URem
1355 { &X86::GR16RegClass, X86::AX, X86::DX, {
1356 { X86::IDIV16r, X86::CWD, Copy, X86::AX, S }, // SDiv
1357 { X86::IDIV16r, X86::CWD, Copy, X86::DX, S }, // SRem
1358 { X86::DIV16r, X86::MOV32r0, Copy, X86::AX, U }, // UDiv
1359 { X86::DIV16r, X86::MOV32r0, Copy, X86::DX, U }, // URem
1362 { &X86::GR32RegClass, X86::EAX, X86::EDX, {
1363 { X86::IDIV32r, X86::CDQ, Copy, X86::EAX, S }, // SDiv
1364 { X86::IDIV32r, X86::CDQ, Copy, X86::EDX, S }, // SRem
1365 { X86::DIV32r, X86::MOV32r0, Copy, X86::EAX, U }, // UDiv
1366 { X86::DIV32r, X86::MOV32r0, Copy, X86::EDX, U }, // URem
1369 { &X86::GR64RegClass, X86::RAX, X86::RDX, {
1370 { X86::IDIV64r, X86::CQO, Copy, X86::RAX, S }, // SDiv
1371 { X86::IDIV64r, X86::CQO, Copy, X86::RDX, S }, // SRem
1372 { X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U }, // UDiv
1373 { X86::DIV64r, X86::MOV32r0, Copy, X86::RDX, U }, // URem
1420 unsigned Zero32 = createResultReg(&X86::GR32RegClass);
1422 TII.get(X86::MOV32r0), Zero32);
1430 .addReg(Zero32, 0, X86::sub_16bit);
1438 .addImm(0).addReg(Zero32).addImm(X86::sub_32bit);
1456 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) {
1457 unsigned SourceSuperReg = createResultReg(&X86::GR16RegClass);
1458 unsigned ResultSuperReg = createResultReg(&X86::GR16RegClass);
1460 TII.get(Copy), SourceSuperReg).addReg(X86::AX);
1463 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SHR16ri),
1468 /*Kill=*/true, X86::sub_8bit);
1492 Opc = X86::CMOVE16rr;
1493 RC = &X86::GR16RegClass;
1495 Opc = X86::CMOVE32rr;
1496 RC = &X86::GR32RegClass;
1498 Opc = X86::CMOVE64rr;
1499 RC = &X86::GR64RegClass;
1511 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
1528 unsigned ResultReg = createResultReg(&X86::FR64RegClass);
1530 TII.get(X86::CVTSS2SDrr), ResultReg)
1547 unsigned ResultReg = createResultReg(&X86::FR32RegClass);
1549 TII.get(X86::CVTSD2SSrr), ResultReg)
1585 (const TargetRegisterClass*)&X86::GR16_ABCDRegClass :
1586 (const TargetRegisterClass*)&X86::GR32_ABCDRegClass;
1596 X86::sub_8bit);
1719 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TRAP));
1747 OpC = X86::ADD32rr;
1749 OpC = X86::ADD64rr;
1759 unsigned Opc = X86::SETBr;
1761 Opc = X86::SETOr;
1817 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1820 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9
1907 if (X86::isCalleePop(CC, Subtarget->is64Bit(), isVarArg,
2146 X86::EBX).addReg(Base);
2152 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2153 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2156 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::MOV8ri),
2157 X86::AL).addImm(NumXMMRegs);
2166 CallOpc = X86::CALL64r;
2168 CallOpc = X86::CALL32r;
2177 CallOpc = X86::CALL64pcrel32;
2179 CallOpc = X86::CALLpcrel32;
2184 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2216 MIB.addReg(X86::EBX, RegState::Implicit);
2219 MIB.addReg(X86::AL, RegState::Implicit);
2268 if ((RVLocs[i].getLocReg() == X86::ST0 ||
2269 RVLocs[i].getLocReg() == X86::ST1)) {
2272 CopyReg = createResultReg(&X86::RFP80RegClass);
2274 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::FpPOP_RETVAL),
2287 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
2293 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
2378 Opc = X86::MOV8rm;
2379 RC = &X86::GR8RegClass;
2382 Opc = X86::MOV16rm;
2383 RC = &X86::GR16RegClass;
2386 Opc = X86::MOV32rm;
2387 RC = &X86::GR32RegClass;
2391 Opc = X86::MOV64rm;
2392 RC = &X86::GR64RegClass;
2396 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
2397 RC = &X86::FR32RegClass;
2399 Opc = X86::LD_Fp32m;
2400 RC = &X86::RFP32RegClass;
2405 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
2406 RC = &X86::FR64RegClass;
2408 Opc = X86::LD_Fp64m;
2409 RC = &X86::RFP64RegClass;
2427 Opc = TLI.getPointerTy() == MVT::i32 ? X86::LEA32r : X86::LEA64r;
2454 PICBase = X86::RIP;
2481 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
2501 Opc = X86::FsFLD0SS;
2502 RC = &X86::FR32RegClass;
2504 Opc = X86::LD_Fp032;
2505 RC = &X86::RFP32RegClass;
2510 Opc = X86::FsFLD0SD;
2511 RC = &X86::FR64RegClass;
2513 Opc = X86::LD_Fp064;
2514 RC = &X86::RFP64RegClass;
2553 FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo,