Searched refs:WREG32_MC (Results 1 - 6 of 6) sorted by relevance
/freebsd-10-stable/sys/dev/drm2/radeon/ |
H A D | rs400.c | 67 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); 75 WREG32_MC(RS480_GART_CACHE_CNTRL, 0); 117 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 146 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); 147 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); 155 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); 167 WREG32_MC(RS480_GART_BASE, tmp); 169 WREG32_MC(RS480_GART_FEATURE_ID, 173 WREG32_MC(RS480_AGP_MODE_CNTL, 179 WREG32_MC(RS480_MC_MISC_CNT [all...] |
H A D | r520.c | 151 WREG32_MC(R_000004_MC_FB_LOCATION, 157 WREG32_MC(R_000005_MC_AGP_LOCATION, 160 WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 161 WREG32_MC(R_000007_AGP_BASE_2, 164 WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF); 165 WREG32_MC(R_000006_AGP_BASE, 0); 166 WREG32_MC(R_000007_AGP_BASE_2, 0);
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H A D | rs600.c | 465 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 469 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 473 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 511 WREG32_MC(R_000100_MC_PT0_CNTL, 516 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, 527 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, 533 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); 536 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, 538 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); 539 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADD [all...] |
H A D | rv515.c | 476 WREG32_MC(R_000001_MC_FB_LOCATION, 482 WREG32_MC(R_000002_MC_AGP_LOCATION, 485 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 486 WREG32_MC(R_000004_MC_AGP_BASE_2, 489 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); 490 WREG32_MC(R_000003_MC_AGP_BASE, 0); 491 WREG32_MC(R_000004_MC_AGP_BASE_2, 0); 1247 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
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H A D | rs690.c | 433 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp); 593 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
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H A D | radeon.h | 1699 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) macro
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Completed in 195 milliseconds