/freebsd-10-stable/sys/arm/xscale/ixp425/ |
H A D | ixp425_wdog.c | 60 WR4(struct ixpwdog_softc *sc, bus_size_t off, uint32_t val) function 71 WR4(sc, IXP425_OST_WDOG_KEY, OST_WDOG_KEY_MAJICK); 73 WR4(sc, IXP425_OST_WDOG_ENAB, 0); 75 WR4(sc, IXP425_OST_WDOG, 2<<(u - 4)); 77 WR4(sc, IXP425_OST_WDOG_ENAB, 82 WR4(sc, IXP425_OST_WDOG_ENAB, 0); 84 WR4(sc, IXP425_OST_WDOG_KEY, 0);
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H A D | if_npe.c | 206 WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) function 461 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 462 WR4(sc, NPE_MAC_ADDR(i), addr[i]); 661 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 664 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 966 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 967 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 968 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 969 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 970 WR4(s [all...] |
/freebsd-10-stable/sys/arm/at91/ |
H A D | at91_spi.c | 84 WR4(struct at91_spi_softc *sc, bus_size_t off, uint32_t val) function 147 WR4(sc, SPI_CR, SPI_CR_SWRST); 149 WR4(sc, SPI_CR, SPI_CR_SWRST); 150 WR4(sc, SPI_IDR, 0xffffffff); 152 WR4(sc, SPI_MR, (0xf << 24) | SPI_MR_MSTR | SPI_MR_MODFDIS | 172 WR4(sc, SPI_CSR0, csr); 173 WR4(sc, SPI_CSR1, csr); 174 WR4(sc, SPI_CSR2, csr); 175 WR4(sc, SPI_CSR3, csr); 177 WR4(s [all...] |
H A D | at91_aic.c | 70 WR4(struct aic_softc *sc, bus_size_t off, uint32_t val) function 80 WR4(sc, IC_IDCR, 1 << nb); 92 WR4(sc, IC_EOICR, 1); 102 WR4(sc, IC_IECR, 1 << nb); 103 WR4(sc, IC_EOICR, 0); 140 WR4(sc, IC_SVR + i * 4, i); 142 WR4(sc, IC_SMR + i * 4, soc_info.soc_data->soc_irq_prio[i]); 144 WR4(sc, IC_EOICR, 1); 147 WR4(sc, IC_SPU, 32); 149 WR4(s [all...] |
H A D | at91_mci.c | 192 WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val) function 245 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); 246 WR4(sc, PDC_RPR, 0); 247 WR4(sc, PDC_RCR, 0); 248 WR4(sc, PDC_RNPR, 0); 249 WR4(sc, PDC_RNCR, 0); 250 WR4(sc, PDC_TPR, 0); 251 WR4(sc, PDC_TCR, 0); 252 WR4(sc, PDC_TNPR, 0); 253 WR4(s [all...] |
H A D | at91_rtc.c | 87 WR4(struct at91_rtc_softc *sc, bus_size_t off, uint32_t val) function 123 WR4(sc, RTC_SCCR, status); 159 WR4(sc, RTC_IDR, 0xffffffff); 160 WR4(sc, RTC_SCCR, 0x1f); 161 WR4(sc, RTC_MR, 0); 179 WR4(sc, RTC_CALR, 0); 232 WR4(sc, RTC_IDR, 0xffffffff); 318 WR4(sc, RTC_CR, RTC_CR_UPDCAL | RTC_CR_UPDTIM); 321 WR4(sc, RTC_SCCR, RTC_SR_ACKUPD); 327 WR4(s [all...] |
H A D | uart_dev_at91usart.c | 86 #define WR4(bas, reg, value) \ macro 199 WR4(bas, USART_MR, mr); 205 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate)); 216 WR4(bas, USART_RTOR, 20); 218 WR4(bas, USART_RTOR, baudrate / 2000); 219 WR4(bas, USART_CR, USART_CR_STTTO); 290 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX); 291 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); 292 WR4(bas, USART_IDR, 0xffffffff); 316 WR4(ba [all...] |
H A D | at91_pio.c | 84 WR4(struct at91_pio_softc *sc, bus_size_t off, uint32_t val) function 185 WR4(sc, PIO_IDR, 0xffffffff); 368 WR4(sc, PIO_SODR, datapin); 370 WR4(sc, PIO_CODR, datapin); 372 WR4(sc, PIO_CODR, clockpin); 373 WR4(sc, PIO_SODR, clockpin); 385 WR4(sc, PIO_SODR, datapin); 387 WR4(sc, PIO_CODR, datapin); 389 WR4(sc, PIO_CODR, clockpin); 390 WR4(s [all...] |
H A D | at91_st.c | 71 WR4(bus_size_t off, uint32_t val) function 149 WR4(ST_WDMR, ST_WDMR_RSTEN | 2); 150 WR4(ST_CR, ST_CR_WDRST); 197 WR4(ST_IDR, 0xffffffff); 282 WR4(ST_WDMR, wdog); 283 WR4(ST_CR, ST_CR_WDRST); 295 WR4(ST_RTMR, 1); 297 WR4(ST_WDMR, 0); 308 WR4(ST_PIMR, rel_value); 311 WR4(ST_IE [all...] |
H A D | at91_twi.c | 83 WR4(struct at91_twi_softc *sc, bus_size_t off, uint32_t val) function 158 WR4(sc, TWI_CR, TWI_CR_SWRST); 159 WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS); 160 WR4(sc, TWI_CWGR, sc->cwgr); 249 WR4(sc, TWI_IDR, status); 305 WR4(sc, TWI_CR, TWI_CR_SWRST); 306 WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS); 307 WR4(sc, TWI_CWGR, sc->cwgr); 355 WR4(sc, TWI_MMR, TWI_MMR_DADR(msgs[i].slave) | rdwr); 364 WR4(s [all...] |
H A D | if_ate.c | 174 WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) function 475 WR4(sc, ETH_HSL, 0xffffffff); 476 WR4(sc, ETH_HSH, 0xffffffff); 500 WR4(sc, ETH_HSL, mcaf[0]); 501 WR4(sc, ETH_HSH, mcaf[1]); 580 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 618 WR4(sc, ETHB_TBQP, sc->tx_desc_phys); 621 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) | ETHB_UIO_CLKE); 688 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); 739 WR4(s [all...] |
H A D | at91_ssc.c | 61 WR4(struct at91_ssc_softc *sc, bus_size_t off, uint32_t val) function 142 WR4(sc, SSC_CR, SSC_CR_SWRST); 143 WR4(sc, SSC_CMR, 0); // clock divider unused 144 WR4(sc, SSC_RCMR, 146 WR4(sc, SSC_RFMR, 148 WR4(sc, SSC_TCMR, 150 WR4(sc, SSC_TFMR,
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H A D | at91_rst.c | 75 WR4(struct at91_rst_softc *sc, bus_size_t off, uint32_t val) function 91 WR4(at91_rst_sc, RST_MR, 94 WR4(at91_rst_sc, RST_CR, 154 WR4(at91_rst_sc, RST_MR, RST_MR_ERSTL(0xd) | RST_MR_URSIEN | RST_MR_KEY);
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H A D | at91_pmc.c | 186 WR4(struct at91_pmc_softc *sc, bus_size_t off, uint32_t val) function 245 WR4(sc, CKGR_PLLBR, value); 263 WR4(sc, CKGR_UCKR, RD4(sc, CKGR_UCKR) | value); 267 WR4(sc, PMC_USB, PMC_USB_USBDIV(9) | PMC_USB_USBS); 268 WR4(sc, PMC_SCER, PMC_SCER_UHP_SAM9); 276 WR4(sc, on ? PMC_SCER : PMC_SCDR, clk->pmc_mask); 290 WR4(sc, on ? PMC_PCER : PMC_PCDR, clk->pmc_mask); 580 WR4(sc, PMC_SCDR, PMC_SCER_UHP | PMC_SCER_UDP); 581 WR4(sc, PMC_SCER, PMC_SCER_MCKUDP); 583 WR4(s [all...] |
H A D | at91_wdt.c | 75 WR4(struct wdt_softc *sc, bus_size_t off, uint32_t val) function 133 WR4(sc, WDT_CR, WDT_KEY|WDT_WDRSTT); 178 WR4(sc, WDT_MR, WDT_WDDBGHLT | WDT_WDD(0xC00)| 182 WR4(sc, WDT_MR, WDT_WDDBGHLT | WDT_WDD(0xC00)|
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H A D | at91_pit.c | 81 WR4(struct pit_softc *sc, bus_size_t off, uint32_t val) function 167 WR4(sc, PIT_MR, PIT_PIV(at91_master_clock / PIT_PRESCALE / hz) |
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/freebsd-10-stable/sys/arm/freescale/imx/ |
H A D | imx6_ccm.c | 73 WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val) function 92 WR4(sc, CCM_CCGR0, 0x0000003f); /* ahpbdma, aipstz 1 & 2 busses */ 93 WR4(sc, CCM_CCGR1, 0x00300c00); /* gpt, enet */ 94 WR4(sc, CCM_CCGR2, 0x0fffffc0); /* ipmux & ipsync (bridges), iomux, i2c */ 95 WR4(sc, CCM_CCGR3, 0x3ff00000); /* DDR memory controller */ 96 WR4(sc, CCM_CCGR4, 0x0000f300); /* pl301 bus crossbar */ 97 WR4(sc, CCM_CCGR5, 0x0ffc00c0); /* uarts, ssi, sdma */ 98 WR4(sc, CCM_CCGR6, 0x000000ff); /* usdhc 1-4 */ 150 WR4(sc, CCM_CGPR, reg); 153 WR4(s [all...] |
H A D | imx_iomux.c | 114 WR4(struct iomux_softc *sc, bus_size_t off, uint32_t val) function 143 WR4(sc, reg, val); 165 WR4(sc, cfg->mux_reg, cfg->mux_val | sion); 168 WR4(sc, cfg->padconf_reg, cfg->padconf_val); 284 WR4(iomux_sc, regnum * 4, val); 300 WR4(iomux_sc, regnum * 4, val);
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H A D | imx_sdhci.c | 170 WR4(struct imx_sdhci_softc *sc, bus_size_t off, uint32_t val) function 385 WR4(sc, SDHC_PROT_CTRL, val32); 398 WR4(sc, off & ~3, val32); 414 WR4(sc, USDHC_MIX_CONTROL, val32); 457 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 458 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 467 WR4(sc, off & ~3, val32); 480 WR4(sc, off, val); 514 WR4(sc, SDHC_VEND_SPEC, 516 WR4(s [all...] |
/freebsd-10-stable/sys/arm/xilinx/ |
H A D | zy7_gpio.c | 95 #define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val)) macro 196 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), 200 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 204 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 209 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), 211 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 231 WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5), 235 WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5), 267 WR4(sc, ZY7_GPIO_DATA(pin >> 5), 295 WR4(s [all...] |
H A D | uart_dev_cdnc.c | 62 #define WR4(bas, reg, value) \ macro 215 WR4(bas, CDNC_UART_BAUDDIV_REG, best_bauddiv); 216 WR4(bas, CDNC_UART_BAUDGEN_REG, best_baudgen); 263 WR4(bas, CDNC_UART_MODE_REG, mode_reg_value); 276 WR4(bas, CDNC_UART_CTRL_REG, 280 WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_ALL); 281 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_ALL); 284 WR4(bas, CDNC_UART_MODEM_STAT_REG, 289 WR4(bas, CDNC_UART_RX_WATER_REG, UART_FIFO_SIZE/2); 290 WR4(ba [all...] |
H A D | zy7_slcr.c | 78 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro 118 WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC); 126 WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC); 141 WR4(sc, ZY7_SLCR_REBOOT_STAT, 145 WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET); 168 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL); 171 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0); 199 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL); 202 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0); 244 WR4(s [all...] |
H A D | zy7_devcfg.c | 88 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro 242 WR4(sc, ZY7_DEVCFG_CTRL, 255 WR4(sc, ZY7_DEVCFG_MCTRL, RD4(sc, ZY7_DEVCFG_MCTRL) & 271 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); 272 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE); 276 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); 285 WR4(sc, ZY7_DEVCFG_INT_MASK, ~0); 296 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); 308 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); 309 WR4(s [all...] |
/freebsd-10-stable/sys/dev/ffec/ |
H A D | if_ffec.c | 216 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) function 309 WR4(sc, FEC_IER_REG, FEC_IER_MII); 311 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | 333 WR4(sc, FEC_IER_REG, FEC_IER_MII); 335 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | 418 WR4(sc, FEC_RCR_REG, rcr); 419 WR4(sc, FEC_TCR_REG, tcr); 420 WR4(sc, FEC_ECR_REG, ecr); 463 WR4(sc, FEC_RMON_R_PACKETS, 0); 464 WR4(s [all...] |
/freebsd-10-stable/sys/dev/cadence/ |
H A D | if_cgem.c | 195 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro 259 WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) | 261 WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]); 264 WR4(sc, CGEM_SPEC_ADDR_LOW(i), 0); 265 WR4(sc, CGEM_SPEC_ADDR_HI(i), 0); 343 WR4(sc, CGEM_HASH_TOP, hash_hi); 344 WR4(sc, CGEM_HASH_BOT, hash_lo); 345 WR4(sc, CGEM_NET_CFG, net_cfg); 781 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow | 888 WR4(s [all...] |