1249997Swkoszek/*- 2273645Sian * Copyright (c) 2012-2014 Thomas Skibo <thomasskibo@yahoo.com> 3249997Swkoszek * All rights reserved. 4249997Swkoszek * 5249997Swkoszek * Redistribution and use in source and binary forms, with or without 6249997Swkoszek * modification, are permitted provided that the following conditions 7249997Swkoszek * are met: 8249997Swkoszek * 1. Redistributions of source code must retain the above copyright 9249997Swkoszek * notice, this list of conditions and the following disclaimer. 10249997Swkoszek * 2. Redistributions in binary form must reproduce the above copyright 11249997Swkoszek * notice, this list of conditions and the following disclaimer in the 12249997Swkoszek * documentation and/or other materials provided with the distribution. 13249997Swkoszek * 14249997Swkoszek * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15249997Swkoszek * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16249997Swkoszek * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17249997Swkoszek * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18249997Swkoszek * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19249997Swkoszek * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20249997Swkoszek * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21249997Swkoszek * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22249997Swkoszek * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23249997Swkoszek * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24249997Swkoszek * SUCH DAMAGE. 25249997Swkoszek */ 26249997Swkoszek 27250015Swkoszek/* 28250015Swkoszek * A network interface driver for Cadence GEM Gigabit Ethernet 29249997Swkoszek * interface such as the one used in Xilinx Zynq-7000 SoC. 30249997Swkoszek * 31249997Swkoszek * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 32249997Swkoszek * (v1.4) November 16, 2012. Xilinx doc UG585. GEM is covered in Ch. 16 33249997Swkoszek * and register definitions are in appendix B.18. 34249997Swkoszek */ 35249997Swkoszek 36249997Swkoszek#include <sys/cdefs.h> 37249997Swkoszek__FBSDID("$FreeBSD$"); 38249997Swkoszek 39249997Swkoszek#include <sys/param.h> 40249997Swkoszek#include <sys/systm.h> 41249997Swkoszek#include <sys/bus.h> 42249997Swkoszek#include <sys/kernel.h> 43249997Swkoszek#include <sys/malloc.h> 44249997Swkoszek#include <sys/mbuf.h> 45249997Swkoszek#include <sys/module.h> 46249997Swkoszek#include <sys/rman.h> 47249997Swkoszek#include <sys/socket.h> 48249997Swkoszek#include <sys/sockio.h> 49249997Swkoszek#include <sys/sysctl.h> 50249997Swkoszek 51249997Swkoszek#include <machine/bus.h> 52249997Swkoszek 53249997Swkoszek#include <net/ethernet.h> 54249997Swkoszek#include <net/if.h> 55249997Swkoszek#include <net/if_arp.h> 56249997Swkoszek#include <net/if_dl.h> 57249997Swkoszek#include <net/if_media.h> 58249997Swkoszek#include <net/if_mib.h> 59249997Swkoszek#include <net/if_types.h> 60249997Swkoszek 61249997Swkoszek#ifdef INET 62249997Swkoszek#include <netinet/in.h> 63249997Swkoszek#include <netinet/in_systm.h> 64249997Swkoszek#include <netinet/in_var.h> 65249997Swkoszek#include <netinet/ip.h> 66249997Swkoszek#endif 67249997Swkoszek 68249997Swkoszek#include <net/bpf.h> 69249997Swkoszek#include <net/bpfdesc.h> 70249997Swkoszek 71249997Swkoszek#include <dev/fdt/fdt_common.h> 72249997Swkoszek#include <dev/ofw/ofw_bus.h> 73249997Swkoszek#include <dev/ofw/ofw_bus_subr.h> 74249997Swkoszek 75249997Swkoszek#include <dev/mii/mii.h> 76249997Swkoszek#include <dev/mii/miivar.h> 77249997Swkoszek 78249997Swkoszek#include <dev/cadence/if_cgem_hw.h> 79249997Swkoszek 80249997Swkoszek#include "miibus_if.h" 81249997Swkoszek 82249997Swkoszek#define IF_CGEM_NAME "cgem" 83249997Swkoszek 84273645Sian#define CGEM_NUM_RX_DESCS 512 /* size of receive descriptor ring */ 85273645Sian#define CGEM_NUM_TX_DESCS 512 /* size of transmit descriptor ring */ 86249997Swkoszek 87249997Swkoszek#define MAX_DESC_RING_SIZE (MAX(CGEM_NUM_RX_DESCS*sizeof(struct cgem_rx_desc),\ 88249997Swkoszek CGEM_NUM_TX_DESCS*sizeof(struct cgem_tx_desc))) 89249997Swkoszek 90249997Swkoszek 91249997Swkoszek/* Default for sysctl rxbufs. Must be < CGEM_NUM_RX_DESCS of course. */ 92273645Sian#define DEFAULT_NUM_RX_BUFS 256 /* number of receive bufs to queue. */ 93249997Swkoszek 94273645Sian#define TX_MAX_DMA_SEGS 8 /* maximum segs in a tx mbuf dma */ 95249997Swkoszek 96249997Swkoszek#define CGEM_CKSUM_ASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP | \ 97249997Swkoszek CSUM_TCP_IPV6 | CSUM_UDP_IPV6) 98249997Swkoszek 99249997Swkoszekstruct cgem_softc { 100249997Swkoszek struct ifnet *ifp; 101249997Swkoszek struct mtx sc_mtx; 102249997Swkoszek device_t dev; 103249997Swkoszek device_t miibus; 104273645Sian u_int mii_media_active; /* last active media */ 105249997Swkoszek int if_old_flags; 106249997Swkoszek struct resource *mem_res; 107249997Swkoszek struct resource *irq_res; 108249997Swkoszek void *intrhand; 109249997Swkoszek struct callout tick_ch; 110249997Swkoszek uint32_t net_ctl_shadow; 111273645Sian int ref_clk_num; 112249997Swkoszek u_char eaddr[6]; 113249997Swkoszek 114249997Swkoszek bus_dma_tag_t desc_dma_tag; 115249997Swkoszek bus_dma_tag_t mbuf_dma_tag; 116249997Swkoszek 117249997Swkoszek /* receive descriptor ring */ 118249997Swkoszek struct cgem_rx_desc *rxring; 119249997Swkoszek bus_addr_t rxring_physaddr; 120249997Swkoszek struct mbuf *rxring_m[CGEM_NUM_RX_DESCS]; 121249997Swkoszek bus_dmamap_t rxring_m_dmamap[CGEM_NUM_RX_DESCS]; 122249997Swkoszek int rxring_hd_ptr; /* where to put rcv bufs */ 123249997Swkoszek int rxring_tl_ptr; /* where to get receives */ 124249997Swkoszek int rxring_queued; /* how many rcv bufs queued */ 125249997Swkoszek bus_dmamap_t rxring_dma_map; 126249997Swkoszek int rxbufs; /* tunable number rcv bufs */ 127273645Sian int rxhangwar; /* rx hang work-around */ 128273645Sian u_int rxoverruns; /* rx overruns */ 129273645Sian u_int rxnobufs; /* rx buf ring empty events */ 130273645Sian u_int rxdmamapfails; /* rx dmamap failures */ 131273645Sian uint32_t rx_frames_prev; 132249997Swkoszek 133249997Swkoszek /* transmit descriptor ring */ 134249997Swkoszek struct cgem_tx_desc *txring; 135249997Swkoszek bus_addr_t txring_physaddr; 136249997Swkoszek struct mbuf *txring_m[CGEM_NUM_TX_DESCS]; 137249997Swkoszek bus_dmamap_t txring_m_dmamap[CGEM_NUM_TX_DESCS]; 138249997Swkoszek int txring_hd_ptr; /* where to put next xmits */ 139249997Swkoszek int txring_tl_ptr; /* next xmit mbuf to free */ 140249997Swkoszek int txring_queued; /* num xmits segs queued */ 141249997Swkoszek bus_dmamap_t txring_dma_map; 142273645Sian u_int txfull; /* tx ring full events */ 143273645Sian u_int txdefrags; /* tx calls to m_defrag() */ 144273645Sian u_int txdefragfails; /* tx m_defrag() failures */ 145273645Sian u_int txdmamapfails; /* tx dmamap failures */ 146273645Sian 147273645Sian /* hardware provided statistics */ 148273645Sian struct cgem_hw_stats { 149273645Sian uint64_t tx_bytes; 150273645Sian uint32_t tx_frames; 151273645Sian uint32_t tx_frames_bcast; 152273645Sian uint32_t tx_frames_multi; 153273645Sian uint32_t tx_frames_pause; 154273645Sian uint32_t tx_frames_64b; 155273645Sian uint32_t tx_frames_65to127b; 156273645Sian uint32_t tx_frames_128to255b; 157273645Sian uint32_t tx_frames_256to511b; 158273645Sian uint32_t tx_frames_512to1023b; 159273645Sian uint32_t tx_frames_1024to1536b; 160273645Sian uint32_t tx_under_runs; 161273645Sian uint32_t tx_single_collisn; 162273645Sian uint32_t tx_multi_collisn; 163273645Sian uint32_t tx_excsv_collisn; 164273645Sian uint32_t tx_late_collisn; 165273645Sian uint32_t tx_deferred_frames; 166273645Sian uint32_t tx_carrier_sense_errs; 167273645Sian 168273645Sian uint64_t rx_bytes; 169273645Sian uint32_t rx_frames; 170273645Sian uint32_t rx_frames_bcast; 171273645Sian uint32_t rx_frames_multi; 172273645Sian uint32_t rx_frames_pause; 173273645Sian uint32_t rx_frames_64b; 174273645Sian uint32_t rx_frames_65to127b; 175273645Sian uint32_t rx_frames_128to255b; 176273645Sian uint32_t rx_frames_256to511b; 177273645Sian uint32_t rx_frames_512to1023b; 178273645Sian uint32_t rx_frames_1024to1536b; 179273645Sian uint32_t rx_frames_undersize; 180273645Sian uint32_t rx_frames_oversize; 181273645Sian uint32_t rx_frames_jabber; 182273645Sian uint32_t rx_frames_fcs_errs; 183273645Sian uint32_t rx_frames_length_errs; 184273645Sian uint32_t rx_symbol_errs; 185273645Sian uint32_t rx_align_errs; 186273645Sian uint32_t rx_resource_errs; 187273645Sian uint32_t rx_overrun_errs; 188273645Sian uint32_t rx_ip_hdr_csum_errs; 189273645Sian uint32_t rx_tcp_csum_errs; 190273645Sian uint32_t rx_udp_csum_errs; 191273645Sian } stats; 192249997Swkoszek}; 193249997Swkoszek 194249997Swkoszek#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) 195249997Swkoszek#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) 196249997Swkoszek#define BARRIER(sc, off, len, flags) \ 197249997Swkoszek (bus_barrier((sc)->mem_res, (off), (len), (flags)) 198249997Swkoszek 199249997Swkoszek#define CGEM_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 200249997Swkoszek#define CGEM_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 201249997Swkoszek#define CGEM_LOCK_INIT(sc) \ 202249997Swkoszek mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \ 203249997Swkoszek MTX_NETWORK_LOCK, MTX_DEF) 204249997Swkoszek#define CGEM_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx) 205249997Swkoszek#define CGEM_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 206249997Swkoszek 207273645Sian/* Allow platforms to optionally provide a way to set the reference clock. */ 208273645Sianint cgem_set_ref_clk(int unit, int frequency); 209273645Sian 210249997Swkoszekstatic devclass_t cgem_devclass; 211249997Swkoszek 212249997Swkoszekstatic int cgem_probe(device_t dev); 213249997Swkoszekstatic int cgem_attach(device_t dev); 214249997Swkoszekstatic int cgem_detach(device_t dev); 215249997Swkoszekstatic void cgem_tick(void *); 216249997Swkoszekstatic void cgem_intr(void *); 217249997Swkoszek 218273645Sianstatic void cgem_mediachange(struct cgem_softc *, struct mii_data *); 219273645Sian 220249997Swkoszekstatic void 221249997Swkoszekcgem_get_mac(struct cgem_softc *sc, u_char eaddr[]) 222249997Swkoszek{ 223249997Swkoszek int i; 224249997Swkoszek uint32_t rnd; 225249997Swkoszek 226249997Swkoszek /* See if boot loader gave us a MAC address already. */ 227249997Swkoszek for (i = 0; i < 4; i++) { 228249997Swkoszek uint32_t low = RD4(sc, CGEM_SPEC_ADDR_LOW(i)); 229249997Swkoszek uint32_t high = RD4(sc, CGEM_SPEC_ADDR_HI(i)) & 0xffff; 230249997Swkoszek if (low != 0 || high != 0) { 231249997Swkoszek eaddr[0] = low & 0xff; 232249997Swkoszek eaddr[1] = (low >> 8) & 0xff; 233249997Swkoszek eaddr[2] = (low >> 16) & 0xff; 234249997Swkoszek eaddr[3] = (low >> 24) & 0xff; 235249997Swkoszek eaddr[4] = high & 0xff; 236249997Swkoszek eaddr[5] = (high >> 8) & 0xff; 237249997Swkoszek break; 238249997Swkoszek } 239249997Swkoszek } 240249997Swkoszek 241249997Swkoszek /* No MAC from boot loader? Assign a random one. */ 242249997Swkoszek if (i == 4) { 243249997Swkoszek rnd = arc4random(); 244249997Swkoszek 245249997Swkoszek eaddr[0] = 'b'; 246249997Swkoszek eaddr[1] = 's'; 247249997Swkoszek eaddr[2] = 'd'; 248249997Swkoszek eaddr[3] = (rnd >> 16) & 0xff; 249249997Swkoszek eaddr[4] = (rnd >> 8) & 0xff; 250249997Swkoszek eaddr[5] = rnd & 0xff; 251249997Swkoszek 252249997Swkoszek device_printf(sc->dev, "no mac address found, assigning " 253249997Swkoszek "random: %02x:%02x:%02x:%02x:%02x:%02x\n", 254249997Swkoszek eaddr[0], eaddr[1], eaddr[2], 255249997Swkoszek eaddr[3], eaddr[4], eaddr[5]); 256273645Sian } 257249997Swkoszek 258273645Sian /* Move address to first slot and zero out the rest. */ 259273645Sian WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) | 260273645Sian (eaddr[2] << 16) | (eaddr[1] << 8) | eaddr[0]); 261273645Sian WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]); 262273645Sian 263273645Sian for (i = 1; i < 4; i++) { 264273645Sian WR4(sc, CGEM_SPEC_ADDR_LOW(i), 0); 265273645Sian WR4(sc, CGEM_SPEC_ADDR_HI(i), 0); 266249997Swkoszek } 267249997Swkoszek} 268249997Swkoszek 269249997Swkoszek/* cgem_mac_hash(): map 48-bit address to a 6-bit hash. 270249997Swkoszek * The 6-bit hash corresponds to a bit in a 64-bit hash 271249997Swkoszek * register. Setting that bit in the hash register enables 272249997Swkoszek * reception of all frames with a destination address that hashes 273249997Swkoszek * to that 6-bit value. 274249997Swkoszek * 275249997Swkoszek * The hash function is described in sec. 16.2.3 in the Zynq-7000 Tech 276249997Swkoszek * Reference Manual. Bits 0-5 in the hash are the exclusive-or of 277249997Swkoszek * every sixth bit in the destination address. 278249997Swkoszek */ 279249997Swkoszekstatic int 280249997Swkoszekcgem_mac_hash(u_char eaddr[]) 281249997Swkoszek{ 282249997Swkoszek int hash; 283249997Swkoszek int i, j; 284249997Swkoszek 285249997Swkoszek hash = 0; 286249997Swkoszek for (i = 0; i < 6; i++) 287249997Swkoszek for (j = i; j < 48; j += 6) 288249997Swkoszek if ((eaddr[j >> 3] & (1 << (j & 7))) != 0) 289249997Swkoszek hash ^= (1 << i); 290249997Swkoszek 291249997Swkoszek return hash; 292249997Swkoszek} 293249997Swkoszek 294249997Swkoszek/* After any change in rx flags or multi-cast addresses, set up 295249997Swkoszek * hash registers and net config register bits. 296249997Swkoszek */ 297249997Swkoszekstatic void 298249997Swkoszekcgem_rx_filter(struct cgem_softc *sc) 299249997Swkoszek{ 300249997Swkoszek struct ifnet *ifp = sc->ifp; 301249997Swkoszek struct ifmultiaddr *ifma; 302249997Swkoszek int index; 303249997Swkoszek uint32_t hash_hi, hash_lo; 304249997Swkoszek uint32_t net_cfg; 305249997Swkoszek 306249997Swkoszek hash_hi = 0; 307249997Swkoszek hash_lo = 0; 308249997Swkoszek 309249997Swkoszek net_cfg = RD4(sc, CGEM_NET_CFG); 310249997Swkoszek 311249997Swkoszek net_cfg &= ~(CGEM_NET_CFG_MULTI_HASH_EN | 312249997Swkoszek CGEM_NET_CFG_NO_BCAST | 313249997Swkoszek CGEM_NET_CFG_COPY_ALL); 314249997Swkoszek 315249997Swkoszek if ((ifp->if_flags & IFF_PROMISC) != 0) 316249997Swkoszek net_cfg |= CGEM_NET_CFG_COPY_ALL; 317249997Swkoszek else { 318249997Swkoszek if ((ifp->if_flags & IFF_BROADCAST) == 0) 319249997Swkoszek net_cfg |= CGEM_NET_CFG_NO_BCAST; 320249997Swkoszek if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 321249997Swkoszek hash_hi = 0xffffffff; 322249997Swkoszek hash_lo = 0xffffffff; 323249997Swkoszek } else { 324249997Swkoszek if_maddr_rlock(ifp); 325249997Swkoszek TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 326249997Swkoszek if (ifma->ifma_addr->sa_family != AF_LINK) 327249997Swkoszek continue; 328249997Swkoszek index = cgem_mac_hash( 329249997Swkoszek LLADDR((struct sockaddr_dl *) 330249997Swkoszek ifma->ifma_addr)); 331249997Swkoszek if (index > 31) 332249997Swkoszek hash_hi |= (1<<(index-32)); 333249997Swkoszek else 334249997Swkoszek hash_lo |= (1<<index); 335249997Swkoszek } 336249997Swkoszek if_maddr_runlock(ifp); 337249997Swkoszek } 338249997Swkoszek 339249997Swkoszek if (hash_hi != 0 || hash_lo != 0) 340249997Swkoszek net_cfg |= CGEM_NET_CFG_MULTI_HASH_EN; 341249997Swkoszek } 342249997Swkoszek 343249997Swkoszek WR4(sc, CGEM_HASH_TOP, hash_hi); 344249997Swkoszek WR4(sc, CGEM_HASH_BOT, hash_lo); 345249997Swkoszek WR4(sc, CGEM_NET_CFG, net_cfg); 346249997Swkoszek} 347249997Swkoszek 348249997Swkoszek/* For bus_dmamap_load() callback. */ 349249997Swkoszekstatic void 350249997Swkoszekcgem_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 351249997Swkoszek{ 352249997Swkoszek 353249997Swkoszek if (nsegs != 1 || error != 0) 354249997Swkoszek return; 355249997Swkoszek *(bus_addr_t *)arg = segs[0].ds_addr; 356249997Swkoszek} 357249997Swkoszek 358249997Swkoszek/* Create DMA'able descriptor rings. */ 359249997Swkoszekstatic int 360249997Swkoszekcgem_setup_descs(struct cgem_softc *sc) 361249997Swkoszek{ 362249997Swkoszek int i, err; 363249997Swkoszek 364249997Swkoszek sc->txring = NULL; 365249997Swkoszek sc->rxring = NULL; 366249997Swkoszek 367249997Swkoszek /* Allocate non-cached DMA space for RX and TX descriptors. 368249997Swkoszek */ 369249997Swkoszek err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 370249997Swkoszek BUS_SPACE_MAXADDR_32BIT, 371249997Swkoszek BUS_SPACE_MAXADDR, 372249997Swkoszek NULL, NULL, 373249997Swkoszek MAX_DESC_RING_SIZE, 374249997Swkoszek 1, 375249997Swkoszek MAX_DESC_RING_SIZE, 376249997Swkoszek 0, 377249997Swkoszek busdma_lock_mutex, 378249997Swkoszek &sc->sc_mtx, 379249997Swkoszek &sc->desc_dma_tag); 380249997Swkoszek if (err) 381249997Swkoszek return (err); 382249997Swkoszek 383249997Swkoszek /* Set up a bus_dma_tag for mbufs. */ 384249997Swkoszek err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 385249997Swkoszek BUS_SPACE_MAXADDR_32BIT, 386249997Swkoszek BUS_SPACE_MAXADDR, 387249997Swkoszek NULL, NULL, 388249997Swkoszek MCLBYTES, 389249997Swkoszek TX_MAX_DMA_SEGS, 390249997Swkoszek MCLBYTES, 391249997Swkoszek 0, 392249997Swkoszek busdma_lock_mutex, 393249997Swkoszek &sc->sc_mtx, 394249997Swkoszek &sc->mbuf_dma_tag); 395249997Swkoszek if (err) 396249997Swkoszek return (err); 397249997Swkoszek 398249997Swkoszek /* Allocate DMA memory in non-cacheable space. */ 399249997Swkoszek err = bus_dmamem_alloc(sc->desc_dma_tag, 400249997Swkoszek (void **)&sc->rxring, 401249997Swkoszek BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 402249997Swkoszek &sc->rxring_dma_map); 403249997Swkoszek if (err) 404249997Swkoszek return (err); 405249997Swkoszek 406249997Swkoszek /* Load descriptor DMA memory. */ 407249997Swkoszek err = bus_dmamap_load(sc->desc_dma_tag, sc->rxring_dma_map, 408249997Swkoszek (void *)sc->rxring, 409249997Swkoszek CGEM_NUM_RX_DESCS*sizeof(struct cgem_rx_desc), 410249997Swkoszek cgem_getaddr, &sc->rxring_physaddr, 411249997Swkoszek BUS_DMA_NOWAIT); 412249997Swkoszek if (err) 413249997Swkoszek return (err); 414249997Swkoszek 415249997Swkoszek /* Initialize RX descriptors. */ 416249997Swkoszek for (i = 0; i < CGEM_NUM_RX_DESCS; i++) { 417249997Swkoszek sc->rxring[i].addr = CGEM_RXDESC_OWN; 418249997Swkoszek sc->rxring[i].ctl = 0; 419249997Swkoszek sc->rxring_m[i] = NULL; 420249997Swkoszek err = bus_dmamap_create(sc->mbuf_dma_tag, 0, 421249997Swkoszek &sc->rxring_m_dmamap[i]); 422249997Swkoszek if (err) 423249997Swkoszek return (err); 424249997Swkoszek } 425249997Swkoszek sc->rxring[CGEM_NUM_RX_DESCS - 1].addr |= CGEM_RXDESC_WRAP; 426249997Swkoszek 427249997Swkoszek sc->rxring_hd_ptr = 0; 428249997Swkoszek sc->rxring_tl_ptr = 0; 429249997Swkoszek sc->rxring_queued = 0; 430249997Swkoszek 431249997Swkoszek /* Allocate DMA memory for TX descriptors in non-cacheable space. */ 432249997Swkoszek err = bus_dmamem_alloc(sc->desc_dma_tag, 433249997Swkoszek (void **)&sc->txring, 434249997Swkoszek BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 435249997Swkoszek &sc->txring_dma_map); 436249997Swkoszek if (err) 437249997Swkoszek return (err); 438249997Swkoszek 439249997Swkoszek /* Load TX descriptor DMA memory. */ 440249997Swkoszek err = bus_dmamap_load(sc->desc_dma_tag, sc->txring_dma_map, 441249997Swkoszek (void *)sc->txring, 442249997Swkoszek CGEM_NUM_TX_DESCS*sizeof(struct cgem_tx_desc), 443249997Swkoszek cgem_getaddr, &sc->txring_physaddr, 444249997Swkoszek BUS_DMA_NOWAIT); 445249997Swkoszek if (err) 446249997Swkoszek return (err); 447249997Swkoszek 448249997Swkoszek /* Initialize TX descriptor ring. */ 449249997Swkoszek for (i = 0; i < CGEM_NUM_TX_DESCS; i++) { 450249997Swkoszek sc->txring[i].addr = 0; 451249997Swkoszek sc->txring[i].ctl = CGEM_TXDESC_USED; 452249997Swkoszek sc->txring_m[i] = NULL; 453249997Swkoszek err = bus_dmamap_create(sc->mbuf_dma_tag, 0, 454249997Swkoszek &sc->txring_m_dmamap[i]); 455249997Swkoszek if (err) 456249997Swkoszek return (err); 457249997Swkoszek } 458249997Swkoszek sc->txring[CGEM_NUM_TX_DESCS - 1].ctl |= CGEM_TXDESC_WRAP; 459249997Swkoszek 460249997Swkoszek sc->txring_hd_ptr = 0; 461249997Swkoszek sc->txring_tl_ptr = 0; 462249997Swkoszek sc->txring_queued = 0; 463249997Swkoszek 464249997Swkoszek return (0); 465249997Swkoszek} 466249997Swkoszek 467249997Swkoszek/* Fill receive descriptor ring with mbufs. */ 468249997Swkoszekstatic void 469249997Swkoszekcgem_fill_rqueue(struct cgem_softc *sc) 470249997Swkoszek{ 471249997Swkoszek struct mbuf *m = NULL; 472249997Swkoszek bus_dma_segment_t segs[TX_MAX_DMA_SEGS]; 473249997Swkoszek int nsegs; 474249997Swkoszek 475249997Swkoszek CGEM_ASSERT_LOCKED(sc); 476249997Swkoszek 477249997Swkoszek while (sc->rxring_queued < sc->rxbufs) { 478249997Swkoszek /* Get a cluster mbuf. */ 479249997Swkoszek m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 480249997Swkoszek if (m == NULL) 481249997Swkoszek break; 482249997Swkoszek 483249997Swkoszek m->m_len = MCLBYTES; 484249997Swkoszek m->m_pkthdr.len = MCLBYTES; 485249997Swkoszek m->m_pkthdr.rcvif = sc->ifp; 486249997Swkoszek 487249997Swkoszek /* Load map and plug in physical address. */ 488249997Swkoszek if (bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag, 489249997Swkoszek sc->rxring_m_dmamap[sc->rxring_hd_ptr], m, 490249997Swkoszek segs, &nsegs, BUS_DMA_NOWAIT)) { 491273645Sian sc->rxdmamapfails++; 492249997Swkoszek m_free(m); 493249997Swkoszek break; 494249997Swkoszek } 495249997Swkoszek sc->rxring_m[sc->rxring_hd_ptr] = m; 496249997Swkoszek 497249997Swkoszek /* Sync cache with receive buffer. */ 498249997Swkoszek bus_dmamap_sync(sc->mbuf_dma_tag, 499249997Swkoszek sc->rxring_m_dmamap[sc->rxring_hd_ptr], 500249997Swkoszek BUS_DMASYNC_PREREAD); 501249997Swkoszek 502249997Swkoszek /* Write rx descriptor and increment head pointer. */ 503249997Swkoszek sc->rxring[sc->rxring_hd_ptr].ctl = 0; 504249997Swkoszek if (sc->rxring_hd_ptr == CGEM_NUM_RX_DESCS - 1) { 505249997Swkoszek sc->rxring[sc->rxring_hd_ptr].addr = segs[0].ds_addr | 506249997Swkoszek CGEM_RXDESC_WRAP; 507249997Swkoszek sc->rxring_hd_ptr = 0; 508249997Swkoszek } else 509249997Swkoszek sc->rxring[sc->rxring_hd_ptr++].addr = segs[0].ds_addr; 510249997Swkoszek 511249997Swkoszek sc->rxring_queued++; 512249997Swkoszek } 513249997Swkoszek} 514249997Swkoszek 515249997Swkoszek/* Pull received packets off of receive descriptor ring. */ 516249997Swkoszekstatic void 517249997Swkoszekcgem_recv(struct cgem_softc *sc) 518249997Swkoszek{ 519249997Swkoszek struct ifnet *ifp = sc->ifp; 520273645Sian struct mbuf *m, *m_hd, **m_tl; 521249997Swkoszek uint32_t ctl; 522249997Swkoszek 523249997Swkoszek CGEM_ASSERT_LOCKED(sc); 524249997Swkoszek 525249997Swkoszek /* Pick up all packets in which the OWN bit is set. */ 526273645Sian m_hd = NULL; 527273645Sian m_tl = &m_hd; 528249997Swkoszek while (sc->rxring_queued > 0 && 529249997Swkoszek (sc->rxring[sc->rxring_tl_ptr].addr & CGEM_RXDESC_OWN) != 0) { 530249997Swkoszek 531249997Swkoszek ctl = sc->rxring[sc->rxring_tl_ptr].ctl; 532249997Swkoszek 533249997Swkoszek /* Grab filled mbuf. */ 534249997Swkoszek m = sc->rxring_m[sc->rxring_tl_ptr]; 535249997Swkoszek sc->rxring_m[sc->rxring_tl_ptr] = NULL; 536249997Swkoszek 537249997Swkoszek /* Sync cache with receive buffer. */ 538249997Swkoszek bus_dmamap_sync(sc->mbuf_dma_tag, 539249997Swkoszek sc->rxring_m_dmamap[sc->rxring_tl_ptr], 540249997Swkoszek BUS_DMASYNC_POSTREAD); 541249997Swkoszek 542249997Swkoszek /* Unload dmamap. */ 543249997Swkoszek bus_dmamap_unload(sc->mbuf_dma_tag, 544249997Swkoszek sc->rxring_m_dmamap[sc->rxring_tl_ptr]); 545249997Swkoszek 546249997Swkoszek /* Increment tail pointer. */ 547249997Swkoszek if (++sc->rxring_tl_ptr == CGEM_NUM_RX_DESCS) 548249997Swkoszek sc->rxring_tl_ptr = 0; 549249997Swkoszek sc->rxring_queued--; 550249997Swkoszek 551249997Swkoszek /* Check FCS and make sure entire packet landed in one mbuf 552249997Swkoszek * cluster (which is much bigger than the largest ethernet 553249997Swkoszek * packet). 554249997Swkoszek */ 555249997Swkoszek if ((ctl & CGEM_RXDESC_BAD_FCS) != 0 || 556249997Swkoszek (ctl & (CGEM_RXDESC_SOF | CGEM_RXDESC_EOF)) != 557249997Swkoszek (CGEM_RXDESC_SOF | CGEM_RXDESC_EOF)) { 558249997Swkoszek /* discard. */ 559249997Swkoszek m_free(m); 560249997Swkoszek ifp->if_ierrors++; 561249997Swkoszek continue; 562249997Swkoszek } 563249997Swkoszek 564273645Sian /* Ready it to hand off to upper layers. */ 565249997Swkoszek m->m_data += ETHER_ALIGN; 566249997Swkoszek m->m_len = (ctl & CGEM_RXDESC_LENGTH_MASK); 567249997Swkoszek m->m_pkthdr.rcvif = ifp; 568249997Swkoszek m->m_pkthdr.len = m->m_len; 569249997Swkoszek 570249997Swkoszek /* Are we using hardware checksumming? Check the 571249997Swkoszek * status in the receive descriptor. 572249997Swkoszek */ 573249997Swkoszek if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 574249997Swkoszek /* TCP or UDP checks out, IP checks out too. */ 575249997Swkoszek if ((ctl & CGEM_RXDESC_CKSUM_STAT_MASK) == 576249997Swkoszek CGEM_RXDESC_CKSUM_STAT_TCP_GOOD || 577249997Swkoszek (ctl & CGEM_RXDESC_CKSUM_STAT_MASK) == 578249997Swkoszek CGEM_RXDESC_CKSUM_STAT_UDP_GOOD) { 579249997Swkoszek m->m_pkthdr.csum_flags |= 580249997Swkoszek CSUM_IP_CHECKED | CSUM_IP_VALID | 581249997Swkoszek CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 582249997Swkoszek m->m_pkthdr.csum_data = 0xffff; 583249997Swkoszek } else if ((ctl & CGEM_RXDESC_CKSUM_STAT_MASK) == 584249997Swkoszek CGEM_RXDESC_CKSUM_STAT_IP_GOOD) { 585249997Swkoszek /* Only IP checks out. */ 586249997Swkoszek m->m_pkthdr.csum_flags |= 587249997Swkoszek CSUM_IP_CHECKED | CSUM_IP_VALID; 588249997Swkoszek m->m_pkthdr.csum_data = 0xffff; 589249997Swkoszek } 590249997Swkoszek } 591249997Swkoszek 592273645Sian /* Queue it up for delivery below. */ 593273645Sian *m_tl = m; 594273645Sian m_tl = &m->m_next; 595273645Sian } 596273645Sian 597273645Sian /* Replenish receive buffers. */ 598273645Sian cgem_fill_rqueue(sc); 599273645Sian 600273645Sian /* Unlock and send up packets. */ 601273645Sian CGEM_UNLOCK(sc); 602273645Sian while (m_hd != NULL) { 603273645Sian m = m_hd; 604273645Sian m_hd = m_hd->m_next; 605273645Sian m->m_next = NULL; 606249997Swkoszek ifp->if_ipackets++; 607249997Swkoszek (*ifp->if_input)(ifp, m); 608249997Swkoszek } 609273645Sian CGEM_LOCK(sc); 610249997Swkoszek} 611249997Swkoszek 612249997Swkoszek/* Find completed transmits and free their mbufs. */ 613249997Swkoszekstatic void 614249997Swkoszekcgem_clean_tx(struct cgem_softc *sc) 615249997Swkoszek{ 616249997Swkoszek struct mbuf *m; 617249997Swkoszek uint32_t ctl; 618249997Swkoszek 619249997Swkoszek CGEM_ASSERT_LOCKED(sc); 620249997Swkoszek 621249997Swkoszek /* free up finished transmits. */ 622249997Swkoszek while (sc->txring_queued > 0 && 623249997Swkoszek ((ctl = sc->txring[sc->txring_tl_ptr].ctl) & 624249997Swkoszek CGEM_TXDESC_USED) != 0) { 625249997Swkoszek 626249997Swkoszek /* Sync cache. nop? */ 627249997Swkoszek bus_dmamap_sync(sc->mbuf_dma_tag, 628249997Swkoszek sc->txring_m_dmamap[sc->txring_tl_ptr], 629249997Swkoszek BUS_DMASYNC_POSTWRITE); 630249997Swkoszek 631249997Swkoszek /* Unload DMA map. */ 632249997Swkoszek bus_dmamap_unload(sc->mbuf_dma_tag, 633249997Swkoszek sc->txring_m_dmamap[sc->txring_tl_ptr]); 634249997Swkoszek 635249997Swkoszek /* Free up the mbuf. */ 636249997Swkoszek m = sc->txring_m[sc->txring_tl_ptr]; 637249997Swkoszek sc->txring_m[sc->txring_tl_ptr] = NULL; 638249997Swkoszek m_freem(m); 639249997Swkoszek 640249997Swkoszek /* Check the status. */ 641249997Swkoszek if ((ctl & CGEM_TXDESC_AHB_ERR) != 0) { 642249997Swkoszek /* Serious bus error. log to console. */ 643249997Swkoszek device_printf(sc->dev, "cgem_clean_tx: Whoa! " 644249997Swkoszek "AHB error, addr=0x%x\n", 645249997Swkoszek sc->txring[sc->txring_tl_ptr].addr); 646249997Swkoszek } else if ((ctl & (CGEM_TXDESC_RETRY_ERR | 647249997Swkoszek CGEM_TXDESC_LATE_COLL)) != 0) { 648249997Swkoszek sc->ifp->if_oerrors++; 649249997Swkoszek } else 650249997Swkoszek sc->ifp->if_opackets++; 651249997Swkoszek 652249997Swkoszek /* If the packet spanned more than one tx descriptor, 653249997Swkoszek * skip descriptors until we find the end so that only 654249997Swkoszek * start-of-frame descriptors are processed. 655249997Swkoszek */ 656249997Swkoszek while ((ctl & CGEM_TXDESC_LAST_BUF) == 0) { 657249997Swkoszek if ((ctl & CGEM_TXDESC_WRAP) != 0) 658249997Swkoszek sc->txring_tl_ptr = 0; 659249997Swkoszek else 660249997Swkoszek sc->txring_tl_ptr++; 661249997Swkoszek sc->txring_queued--; 662249997Swkoszek 663249997Swkoszek ctl = sc->txring[sc->txring_tl_ptr].ctl; 664249997Swkoszek 665249997Swkoszek sc->txring[sc->txring_tl_ptr].ctl = 666249997Swkoszek ctl | CGEM_TXDESC_USED; 667249997Swkoszek } 668249997Swkoszek 669249997Swkoszek /* Next descriptor. */ 670249997Swkoszek if ((ctl & CGEM_TXDESC_WRAP) != 0) 671249997Swkoszek sc->txring_tl_ptr = 0; 672249997Swkoszek else 673249997Swkoszek sc->txring_tl_ptr++; 674249997Swkoszek sc->txring_queued--; 675273645Sian 676273645Sian sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 677249997Swkoszek } 678249997Swkoszek} 679249997Swkoszek 680249997Swkoszek/* Start transmits. */ 681249997Swkoszekstatic void 682249997Swkoszekcgem_start_locked(struct ifnet *ifp) 683249997Swkoszek{ 684249997Swkoszek struct cgem_softc *sc = (struct cgem_softc *) ifp->if_softc; 685249997Swkoszek struct mbuf *m; 686249997Swkoszek bus_dma_segment_t segs[TX_MAX_DMA_SEGS]; 687249997Swkoszek uint32_t ctl; 688249997Swkoszek int i, nsegs, wrap, err; 689249997Swkoszek 690249997Swkoszek CGEM_ASSERT_LOCKED(sc); 691249997Swkoszek 692249997Swkoszek if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) 693249997Swkoszek return; 694249997Swkoszek 695249997Swkoszek for (;;) { 696249997Swkoszek /* Check that there is room in the descriptor ring. */ 697273645Sian if (sc->txring_queued >= 698273645Sian CGEM_NUM_TX_DESCS - TX_MAX_DMA_SEGS * 2) { 699249997Swkoszek 700249997Swkoszek /* Try to make room. */ 701249997Swkoszek cgem_clean_tx(sc); 702249997Swkoszek 703249997Swkoszek /* Still no room? */ 704273645Sian if (sc->txring_queued >= 705273645Sian CGEM_NUM_TX_DESCS - TX_MAX_DMA_SEGS * 2) { 706249997Swkoszek ifp->if_drv_flags |= IFF_DRV_OACTIVE; 707273645Sian sc->txfull++; 708249997Swkoszek break; 709249997Swkoszek } 710249997Swkoszek } 711249997Swkoszek 712249997Swkoszek /* Grab next transmit packet. */ 713249997Swkoszek IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 714249997Swkoszek if (m == NULL) 715249997Swkoszek break; 716249997Swkoszek 717249997Swkoszek /* Load DMA map. */ 718249997Swkoszek err = bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag, 719249997Swkoszek sc->txring_m_dmamap[sc->txring_hd_ptr], 720249997Swkoszek m, segs, &nsegs, BUS_DMA_NOWAIT); 721249997Swkoszek if (err == EFBIG) { 722249997Swkoszek /* Too many segments! defrag and try again. */ 723249997Swkoszek struct mbuf *m2 = m_defrag(m, M_NOWAIT); 724249997Swkoszek 725249997Swkoszek if (m2 == NULL) { 726273645Sian sc->txdefragfails++; 727249997Swkoszek m_freem(m); 728249997Swkoszek continue; 729249997Swkoszek } 730249997Swkoszek m = m2; 731249997Swkoszek err = bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag, 732249997Swkoszek sc->txring_m_dmamap[sc->txring_hd_ptr], 733249997Swkoszek m, segs, &nsegs, BUS_DMA_NOWAIT); 734273645Sian sc->txdefrags++; 735249997Swkoszek } 736249997Swkoszek if (err) { 737249997Swkoszek /* Give up. */ 738249997Swkoszek m_freem(m); 739273645Sian sc->txdmamapfails++; 740249997Swkoszek continue; 741249997Swkoszek } 742249997Swkoszek sc->txring_m[sc->txring_hd_ptr] = m; 743249997Swkoszek 744249997Swkoszek /* Sync tx buffer with cache. */ 745249997Swkoszek bus_dmamap_sync(sc->mbuf_dma_tag, 746249997Swkoszek sc->txring_m_dmamap[sc->txring_hd_ptr], 747249997Swkoszek BUS_DMASYNC_PREWRITE); 748249997Swkoszek 749249997Swkoszek /* Set wrap flag if next packet might run off end of ring. */ 750249997Swkoszek wrap = sc->txring_hd_ptr + nsegs + TX_MAX_DMA_SEGS >= 751249997Swkoszek CGEM_NUM_TX_DESCS; 752249997Swkoszek 753249997Swkoszek /* Fill in the TX descriptors back to front so that USED 754249997Swkoszek * bit in first descriptor is cleared last. 755249997Swkoszek */ 756249997Swkoszek for (i = nsegs - 1; i >= 0; i--) { 757249997Swkoszek /* Descriptor address. */ 758249997Swkoszek sc->txring[sc->txring_hd_ptr + i].addr = 759249997Swkoszek segs[i].ds_addr; 760249997Swkoszek 761249997Swkoszek /* Descriptor control word. */ 762249997Swkoszek ctl = segs[i].ds_len; 763249997Swkoszek if (i == nsegs - 1) { 764249997Swkoszek ctl |= CGEM_TXDESC_LAST_BUF; 765249997Swkoszek if (wrap) 766249997Swkoszek ctl |= CGEM_TXDESC_WRAP; 767249997Swkoszek } 768249997Swkoszek sc->txring[sc->txring_hd_ptr + i].ctl = ctl; 769249997Swkoszek 770249997Swkoszek if (i != 0) 771249997Swkoszek sc->txring_m[sc->txring_hd_ptr + i] = NULL; 772249997Swkoszek } 773249997Swkoszek 774249997Swkoszek if (wrap) 775249997Swkoszek sc->txring_hd_ptr = 0; 776249997Swkoszek else 777249997Swkoszek sc->txring_hd_ptr += nsegs; 778249997Swkoszek sc->txring_queued += nsegs; 779249997Swkoszek 780249997Swkoszek /* Kick the transmitter. */ 781249997Swkoszek WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow | 782249997Swkoszek CGEM_NET_CTRL_START_TX); 783273645Sian 784273645Sian /* If there is a BPF listener, bounce a copy to to him. */ 785273645Sian ETHER_BPF_MTAP(ifp, m); 786249997Swkoszek } 787249997Swkoszek} 788249997Swkoszek 789249997Swkoszekstatic void 790249997Swkoszekcgem_start(struct ifnet *ifp) 791249997Swkoszek{ 792249997Swkoszek struct cgem_softc *sc = (struct cgem_softc *) ifp->if_softc; 793249997Swkoszek 794249997Swkoszek CGEM_LOCK(sc); 795249997Swkoszek cgem_start_locked(ifp); 796249997Swkoszek CGEM_UNLOCK(sc); 797249997Swkoszek} 798249997Swkoszek 799249997Swkoszekstatic void 800273645Siancgem_poll_hw_stats(struct cgem_softc *sc) 801249997Swkoszek{ 802273645Sian uint32_t n; 803249997Swkoszek 804249997Swkoszek CGEM_ASSERT_LOCKED(sc); 805249997Swkoszek 806273645Sian sc->stats.tx_bytes += RD4(sc, CGEM_OCTETS_TX_BOT); 807273645Sian sc->stats.tx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_TX_TOP) << 32; 808249997Swkoszek 809273645Sian sc->stats.tx_frames += RD4(sc, CGEM_FRAMES_TX); 810273645Sian sc->stats.tx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_TX); 811273645Sian sc->stats.tx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_TX); 812273645Sian sc->stats.tx_frames_pause += RD4(sc, CGEM_PAUSE_FRAMES_TX); 813273645Sian sc->stats.tx_frames_64b += RD4(sc, CGEM_FRAMES_64B_TX); 814273645Sian sc->stats.tx_frames_65to127b += RD4(sc, CGEM_FRAMES_65_127B_TX); 815273645Sian sc->stats.tx_frames_128to255b += RD4(sc, CGEM_FRAMES_128_255B_TX); 816273645Sian sc->stats.tx_frames_256to511b += RD4(sc, CGEM_FRAMES_256_511B_TX); 817273645Sian sc->stats.tx_frames_512to1023b += RD4(sc, CGEM_FRAMES_512_1023B_TX); 818273645Sian sc->stats.tx_frames_1024to1536b += RD4(sc, CGEM_FRAMES_1024_1518B_TX); 819273645Sian sc->stats.tx_under_runs += RD4(sc, CGEM_TX_UNDERRUNS); 820249997Swkoszek 821273645Sian n = RD4(sc, CGEM_SINGLE_COLL_FRAMES); 822273645Sian sc->stats.tx_single_collisn += n; 823273645Sian sc->ifp->if_collisions += n; 824273645Sian n = RD4(sc, CGEM_MULTI_COLL_FRAMES); 825273645Sian sc->stats.tx_multi_collisn += n; 826273645Sian sc->ifp->if_collisions += n; 827273645Sian n = RD4(sc, CGEM_EXCESSIVE_COLL_FRAMES); 828273645Sian sc->stats.tx_excsv_collisn += n; 829273645Sian sc->ifp->if_collisions += n; 830273645Sian n = RD4(sc, CGEM_LATE_COLL); 831273645Sian sc->stats.tx_late_collisn += n; 832273645Sian sc->ifp->if_collisions += n; 833273645Sian 834273645Sian sc->stats.tx_deferred_frames += RD4(sc, CGEM_DEFERRED_TX_FRAMES); 835273645Sian sc->stats.tx_carrier_sense_errs += RD4(sc, CGEM_CARRIER_SENSE_ERRS); 836273645Sian 837273645Sian sc->stats.rx_bytes += RD4(sc, CGEM_OCTETS_RX_BOT); 838273645Sian sc->stats.rx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_RX_TOP) << 32; 839273645Sian 840273645Sian sc->stats.rx_frames += RD4(sc, CGEM_FRAMES_RX); 841273645Sian sc->stats.rx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_RX); 842273645Sian sc->stats.rx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_RX); 843273645Sian sc->stats.rx_frames_pause += RD4(sc, CGEM_PAUSE_FRAMES_RX); 844273645Sian sc->stats.rx_frames_64b += RD4(sc, CGEM_FRAMES_64B_RX); 845273645Sian sc->stats.rx_frames_65to127b += RD4(sc, CGEM_FRAMES_65_127B_RX); 846273645Sian sc->stats.rx_frames_128to255b += RD4(sc, CGEM_FRAMES_128_255B_RX); 847273645Sian sc->stats.rx_frames_256to511b += RD4(sc, CGEM_FRAMES_256_511B_RX); 848273645Sian sc->stats.rx_frames_512to1023b += RD4(sc, CGEM_FRAMES_512_1023B_RX); 849273645Sian sc->stats.rx_frames_1024to1536b += RD4(sc, CGEM_FRAMES_1024_1518B_RX); 850273645Sian sc->stats.rx_frames_undersize += RD4(sc, CGEM_UNDERSZ_RX); 851273645Sian sc->stats.rx_frames_oversize += RD4(sc, CGEM_OVERSZ_RX); 852273645Sian sc->stats.rx_frames_jabber += RD4(sc, CGEM_JABBERS_RX); 853273645Sian sc->stats.rx_frames_fcs_errs += RD4(sc, CGEM_FCS_ERRS); 854273645Sian sc->stats.rx_frames_length_errs += RD4(sc, CGEM_LENGTH_FIELD_ERRS); 855273645Sian sc->stats.rx_symbol_errs += RD4(sc, CGEM_RX_SYMBOL_ERRS); 856273645Sian sc->stats.rx_align_errs += RD4(sc, CGEM_ALIGN_ERRS); 857273645Sian sc->stats.rx_resource_errs += RD4(sc, CGEM_RX_RESOURCE_ERRS); 858273645Sian sc->stats.rx_overrun_errs += RD4(sc, CGEM_RX_OVERRUN_ERRS); 859273645Sian sc->stats.rx_ip_hdr_csum_errs += RD4(sc, CGEM_IP_HDR_CKSUM_ERRS); 860273645Sian sc->stats.rx_tcp_csum_errs += RD4(sc, CGEM_TCP_CKSUM_ERRS); 861273645Sian sc->stats.rx_udp_csum_errs += RD4(sc, CGEM_UDP_CKSUM_ERRS); 862249997Swkoszek} 863249997Swkoszek 864249997Swkoszekstatic void 865249997Swkoszekcgem_tick(void *arg) 866249997Swkoszek{ 867249997Swkoszek struct cgem_softc *sc = (struct cgem_softc *)arg; 868249997Swkoszek struct mii_data *mii; 869249997Swkoszek 870249997Swkoszek CGEM_ASSERT_LOCKED(sc); 871249997Swkoszek 872249997Swkoszek /* Poll the phy. */ 873249997Swkoszek if (sc->miibus != NULL) { 874249997Swkoszek mii = device_get_softc(sc->miibus); 875249997Swkoszek mii_tick(mii); 876249997Swkoszek } 877249997Swkoszek 878273645Sian /* Poll statistics registers. */ 879273645Sian cgem_poll_hw_stats(sc); 880273645Sian 881273645Sian /* Check for receiver hang. */ 882273645Sian if (sc->rxhangwar && sc->rx_frames_prev == sc->stats.rx_frames) { 883273645Sian /* 884273645Sian * Reset receiver logic by toggling RX_EN bit. 1usec 885273645Sian * delay is necessary especially when operating at 100mbps 886273645Sian * and 10mbps speeds. 887273645Sian */ 888273645Sian WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow & 889273645Sian ~CGEM_NET_CTRL_RX_EN); 890273645Sian DELAY(1); 891273645Sian WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow); 892273645Sian } 893273645Sian sc->rx_frames_prev = sc->stats.rx_frames; 894273645Sian 895249997Swkoszek /* Next callout in one second. */ 896249997Swkoszek callout_reset(&sc->tick_ch, hz, cgem_tick, sc); 897249997Swkoszek} 898249997Swkoszek 899249997Swkoszek/* Interrupt handler. */ 900249997Swkoszekstatic void 901249997Swkoszekcgem_intr(void *arg) 902249997Swkoszek{ 903249997Swkoszek struct cgem_softc *sc = (struct cgem_softc *)arg; 904249997Swkoszek uint32_t istatus; 905249997Swkoszek 906249997Swkoszek CGEM_LOCK(sc); 907249997Swkoszek 908249997Swkoszek if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 909249997Swkoszek CGEM_UNLOCK(sc); 910249997Swkoszek return; 911249997Swkoszek } 912249997Swkoszek 913273645Sian /* Read interrupt status and immediately clear the bits. */ 914249997Swkoszek istatus = RD4(sc, CGEM_INTR_STAT); 915273645Sian WR4(sc, CGEM_INTR_STAT, istatus); 916249997Swkoszek 917273645Sian /* Packets received. */ 918273645Sian if ((istatus & CGEM_INTR_RX_COMPLETE) != 0) 919273645Sian cgem_recv(sc); 920273645Sian 921273645Sian /* Free up any completed transmit buffers. */ 922273645Sian cgem_clean_tx(sc); 923273645Sian 924273645Sian /* Hresp not ok. Something is very bad with DMA. Try to clear. */ 925249997Swkoszek if ((istatus & CGEM_INTR_HRESP_NOT_OK) != 0) { 926273645Sian device_printf(sc->dev, "cgem_intr: hresp not okay! " 927273645Sian "rx_status=0x%x\n", RD4(sc, CGEM_RX_STAT)); 928249997Swkoszek WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_HRESP_NOT_OK); 929249997Swkoszek } 930249997Swkoszek 931273645Sian /* Receiver overrun. */ 932273645Sian if ((istatus & CGEM_INTR_RX_OVERRUN) != 0) { 933273645Sian /* Clear status bit. */ 934273645Sian WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_OVERRUN); 935273645Sian sc->rxoverruns++; 936273645Sian } 937249997Swkoszek 938273645Sian /* Receiver ran out of bufs. */ 939273645Sian if ((istatus & CGEM_INTR_RX_USED_READ) != 0) { 940273645Sian WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow | 941273645Sian CGEM_NET_CTRL_FLUSH_DPRAM_PKT); 942249997Swkoszek cgem_fill_rqueue(sc); 943273645Sian sc->rxnobufs++; 944249997Swkoszek } 945249997Swkoszek 946273645Sian /* Restart transmitter if needed. */ 947273645Sian if (!IFQ_DRV_IS_EMPTY(&sc->ifp->if_snd)) 948273645Sian cgem_start_locked(sc->ifp); 949273645Sian 950249997Swkoszek CGEM_UNLOCK(sc); 951249997Swkoszek} 952249997Swkoszek 953249997Swkoszek/* Reset hardware. */ 954249997Swkoszekstatic void 955249997Swkoszekcgem_reset(struct cgem_softc *sc) 956249997Swkoszek{ 957249997Swkoszek 958249997Swkoszek CGEM_ASSERT_LOCKED(sc); 959249997Swkoszek 960249997Swkoszek WR4(sc, CGEM_NET_CTRL, 0); 961249997Swkoszek WR4(sc, CGEM_NET_CFG, 0); 962249997Swkoszek WR4(sc, CGEM_NET_CTRL, CGEM_NET_CTRL_CLR_STAT_REGS); 963249997Swkoszek WR4(sc, CGEM_TX_STAT, CGEM_TX_STAT_ALL); 964249997Swkoszek WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_ALL); 965249997Swkoszek WR4(sc, CGEM_INTR_DIS, CGEM_INTR_ALL); 966249997Swkoszek WR4(sc, CGEM_HASH_BOT, 0); 967249997Swkoszek WR4(sc, CGEM_HASH_TOP, 0); 968249997Swkoszek WR4(sc, CGEM_TX_QBAR, 0); /* manual says do this. */ 969249997Swkoszek WR4(sc, CGEM_RX_QBAR, 0); 970249997Swkoszek 971249997Swkoszek /* Get management port running even if interface is down. */ 972249997Swkoszek WR4(sc, CGEM_NET_CFG, 973249997Swkoszek CGEM_NET_CFG_DBUS_WIDTH_32 | 974249997Swkoszek CGEM_NET_CFG_MDC_CLK_DIV_64); 975249997Swkoszek 976249997Swkoszek sc->net_ctl_shadow = CGEM_NET_CTRL_MGMT_PORT_EN; 977249997Swkoszek WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow); 978249997Swkoszek} 979249997Swkoszek 980249997Swkoszek/* Bring up the hardware. */ 981249997Swkoszekstatic void 982249997Swkoszekcgem_config(struct cgem_softc *sc) 983249997Swkoszek{ 984249997Swkoszek uint32_t net_cfg; 985249997Swkoszek uint32_t dma_cfg; 986273645Sian u_char *eaddr = IF_LLADDR(sc->ifp); 987249997Swkoszek 988249997Swkoszek CGEM_ASSERT_LOCKED(sc); 989249997Swkoszek 990249997Swkoszek /* Program Net Config Register. */ 991249997Swkoszek net_cfg = CGEM_NET_CFG_DBUS_WIDTH_32 | 992249997Swkoszek CGEM_NET_CFG_MDC_CLK_DIV_64 | 993249997Swkoszek CGEM_NET_CFG_FCS_REMOVE | 994249997Swkoszek CGEM_NET_CFG_RX_BUF_OFFSET(ETHER_ALIGN) | 995249997Swkoszek CGEM_NET_CFG_GIGE_EN | 996273645Sian CGEM_NET_CFG_1536RXEN | 997249997Swkoszek CGEM_NET_CFG_FULL_DUPLEX | 998249997Swkoszek CGEM_NET_CFG_SPEED100; 999249997Swkoszek 1000249997Swkoszek /* Enable receive checksum offloading? */ 1001249997Swkoszek if ((sc->ifp->if_capenable & IFCAP_RXCSUM) != 0) 1002249997Swkoszek net_cfg |= CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN; 1003249997Swkoszek 1004249997Swkoszek WR4(sc, CGEM_NET_CFG, net_cfg); 1005249997Swkoszek 1006249997Swkoszek /* Program DMA Config Register. */ 1007249997Swkoszek dma_cfg = CGEM_DMA_CFG_RX_BUF_SIZE(MCLBYTES) | 1008249997Swkoszek CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_8K | 1009249997Swkoszek CGEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL | 1010273645Sian CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_16 | 1011273645Sian CGEM_DMA_CFG_DISC_WHEN_NO_AHB; 1012249997Swkoszek 1013249997Swkoszek /* Enable transmit checksum offloading? */ 1014249997Swkoszek if ((sc->ifp->if_capenable & IFCAP_TXCSUM) != 0) 1015249997Swkoszek dma_cfg |= CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN; 1016249997Swkoszek 1017249997Swkoszek WR4(sc, CGEM_DMA_CFG, dma_cfg); 1018249997Swkoszek 1019249997Swkoszek /* Write the rx and tx descriptor ring addresses to the QBAR regs. */ 1020249997Swkoszek WR4(sc, CGEM_RX_QBAR, (uint32_t) sc->rxring_physaddr); 1021249997Swkoszek WR4(sc, CGEM_TX_QBAR, (uint32_t) sc->txring_physaddr); 1022249997Swkoszek 1023249997Swkoszek /* Enable rx and tx. */ 1024249997Swkoszek sc->net_ctl_shadow |= (CGEM_NET_CTRL_TX_EN | CGEM_NET_CTRL_RX_EN); 1025249997Swkoszek WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow); 1026249997Swkoszek 1027273645Sian /* Set receive address in case it changed. */ 1028273645Sian WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) | 1029273645Sian (eaddr[2] << 16) | (eaddr[1] << 8) | eaddr[0]); 1030273645Sian WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]); 1031273645Sian 1032249997Swkoszek /* Set up interrupts. */ 1033249997Swkoszek WR4(sc, CGEM_INTR_EN, 1034273645Sian CGEM_INTR_RX_COMPLETE | CGEM_INTR_RX_OVERRUN | 1035273645Sian CGEM_INTR_TX_USED_READ | CGEM_INTR_RX_USED_READ | 1036273645Sian CGEM_INTR_HRESP_NOT_OK); 1037249997Swkoszek} 1038249997Swkoszek 1039249997Swkoszek/* Turn on interface and load up receive ring with buffers. */ 1040249997Swkoszekstatic void 1041249997Swkoszekcgem_init_locked(struct cgem_softc *sc) 1042249997Swkoszek{ 1043249997Swkoszek struct mii_data *mii; 1044249997Swkoszek 1045249997Swkoszek CGEM_ASSERT_LOCKED(sc); 1046249997Swkoszek 1047249997Swkoszek if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1048249997Swkoszek return; 1049249997Swkoszek 1050249997Swkoszek cgem_config(sc); 1051249997Swkoszek cgem_fill_rqueue(sc); 1052249997Swkoszek 1053249997Swkoszek sc->ifp->if_drv_flags |= IFF_DRV_RUNNING; 1054249997Swkoszek sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1055249997Swkoszek 1056249997Swkoszek mii = device_get_softc(sc->miibus); 1057273645Sian mii_mediachg(mii); 1058249997Swkoszek 1059249997Swkoszek callout_reset(&sc->tick_ch, hz, cgem_tick, sc); 1060249997Swkoszek} 1061249997Swkoszek 1062249997Swkoszekstatic void 1063249997Swkoszekcgem_init(void *arg) 1064249997Swkoszek{ 1065249997Swkoszek struct cgem_softc *sc = (struct cgem_softc *)arg; 1066249997Swkoszek 1067249997Swkoszek CGEM_LOCK(sc); 1068249997Swkoszek cgem_init_locked(sc); 1069249997Swkoszek CGEM_UNLOCK(sc); 1070249997Swkoszek} 1071249997Swkoszek 1072249997Swkoszek/* Turn off interface. Free up any buffers in transmit or receive queues. */ 1073249997Swkoszekstatic void 1074249997Swkoszekcgem_stop(struct cgem_softc *sc) 1075249997Swkoszek{ 1076249997Swkoszek int i; 1077249997Swkoszek 1078249997Swkoszek CGEM_ASSERT_LOCKED(sc); 1079249997Swkoszek 1080249997Swkoszek callout_stop(&sc->tick_ch); 1081249997Swkoszek 1082249997Swkoszek /* Shut down hardware. */ 1083249997Swkoszek cgem_reset(sc); 1084249997Swkoszek 1085249997Swkoszek /* Clear out transmit queue. */ 1086249997Swkoszek for (i = 0; i < CGEM_NUM_TX_DESCS; i++) { 1087249997Swkoszek sc->txring[i].ctl = CGEM_TXDESC_USED; 1088249997Swkoszek sc->txring[i].addr = 0; 1089249997Swkoszek if (sc->txring_m[i]) { 1090249997Swkoszek bus_dmamap_unload(sc->mbuf_dma_tag, 1091249997Swkoszek sc->txring_m_dmamap[i]); 1092249997Swkoszek m_freem(sc->txring_m[i]); 1093249997Swkoszek sc->txring_m[i] = NULL; 1094249997Swkoszek } 1095249997Swkoszek } 1096249997Swkoszek sc->txring[CGEM_NUM_TX_DESCS - 1].ctl |= CGEM_TXDESC_WRAP; 1097249997Swkoszek 1098249997Swkoszek sc->txring_hd_ptr = 0; 1099249997Swkoszek sc->txring_tl_ptr = 0; 1100249997Swkoszek sc->txring_queued = 0; 1101249997Swkoszek 1102249997Swkoszek /* Clear out receive queue. */ 1103249997Swkoszek for (i = 0; i < CGEM_NUM_RX_DESCS; i++) { 1104249997Swkoszek sc->rxring[i].addr = CGEM_RXDESC_OWN; 1105249997Swkoszek sc->rxring[i].ctl = 0; 1106249997Swkoszek if (sc->rxring_m[i]) { 1107249997Swkoszek /* Unload dmamap. */ 1108249997Swkoszek bus_dmamap_unload(sc->mbuf_dma_tag, 1109249997Swkoszek sc->rxring_m_dmamap[sc->rxring_tl_ptr]); 1110249997Swkoszek 1111249997Swkoszek m_freem(sc->rxring_m[i]); 1112249997Swkoszek sc->rxring_m[i] = NULL; 1113249997Swkoszek } 1114249997Swkoszek } 1115249997Swkoszek sc->rxring[CGEM_NUM_RX_DESCS - 1].addr |= CGEM_RXDESC_WRAP; 1116249997Swkoszek 1117249997Swkoszek sc->rxring_hd_ptr = 0; 1118249997Swkoszek sc->rxring_tl_ptr = 0; 1119249997Swkoszek sc->rxring_queued = 0; 1120273645Sian 1121273645Sian /* Force next statchg or linkchg to program net config register. */ 1122273645Sian sc->mii_media_active = 0; 1123249997Swkoszek} 1124249997Swkoszek 1125249997Swkoszek 1126249997Swkoszekstatic int 1127249997Swkoszekcgem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1128249997Swkoszek{ 1129249997Swkoszek struct cgem_softc *sc = ifp->if_softc; 1130249997Swkoszek struct ifreq *ifr = (struct ifreq *)data; 1131249997Swkoszek struct mii_data *mii; 1132249997Swkoszek int error = 0, mask; 1133249997Swkoszek 1134249997Swkoszek switch (cmd) { 1135249997Swkoszek case SIOCSIFFLAGS: 1136249997Swkoszek CGEM_LOCK(sc); 1137249997Swkoszek if ((ifp->if_flags & IFF_UP) != 0) { 1138249997Swkoszek if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1139249997Swkoszek if (((ifp->if_flags ^ sc->if_old_flags) & 1140249997Swkoszek (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1141249997Swkoszek cgem_rx_filter(sc); 1142249997Swkoszek } 1143249997Swkoszek } else { 1144249997Swkoszek cgem_init_locked(sc); 1145249997Swkoszek } 1146249997Swkoszek } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1147249997Swkoszek ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1148249997Swkoszek cgem_stop(sc); 1149249997Swkoszek } 1150249997Swkoszek sc->if_old_flags = ifp->if_flags; 1151249997Swkoszek CGEM_UNLOCK(sc); 1152249997Swkoszek break; 1153249997Swkoszek 1154249997Swkoszek case SIOCADDMULTI: 1155249997Swkoszek case SIOCDELMULTI: 1156249997Swkoszek /* Set up multi-cast filters. */ 1157249997Swkoszek if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1158249997Swkoszek CGEM_LOCK(sc); 1159249997Swkoszek cgem_rx_filter(sc); 1160249997Swkoszek CGEM_UNLOCK(sc); 1161249997Swkoszek } 1162249997Swkoszek break; 1163249997Swkoszek 1164249997Swkoszek case SIOCSIFMEDIA: 1165249997Swkoszek case SIOCGIFMEDIA: 1166249997Swkoszek mii = device_get_softc(sc->miibus); 1167249997Swkoszek error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1168249997Swkoszek break; 1169249997Swkoszek 1170249997Swkoszek case SIOCSIFCAP: 1171249997Swkoszek CGEM_LOCK(sc); 1172249997Swkoszek mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1173249997Swkoszek 1174249997Swkoszek if ((mask & IFCAP_TXCSUM) != 0) { 1175249997Swkoszek if ((ifr->ifr_reqcap & IFCAP_TXCSUM) != 0) { 1176249997Swkoszek /* Turn on TX checksumming. */ 1177249997Swkoszek ifp->if_capenable |= (IFCAP_TXCSUM | 1178249997Swkoszek IFCAP_TXCSUM_IPV6); 1179249997Swkoszek ifp->if_hwassist |= CGEM_CKSUM_ASSIST; 1180249997Swkoszek 1181249997Swkoszek WR4(sc, CGEM_DMA_CFG, 1182249997Swkoszek RD4(sc, CGEM_DMA_CFG) | 1183249997Swkoszek CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN); 1184249997Swkoszek } else { 1185249997Swkoszek /* Turn off TX checksumming. */ 1186249997Swkoszek ifp->if_capenable &= ~(IFCAP_TXCSUM | 1187249997Swkoszek IFCAP_TXCSUM_IPV6); 1188249997Swkoszek ifp->if_hwassist &= ~CGEM_CKSUM_ASSIST; 1189249997Swkoszek 1190249997Swkoszek WR4(sc, CGEM_DMA_CFG, 1191249997Swkoszek RD4(sc, CGEM_DMA_CFG) & 1192249997Swkoszek ~CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN); 1193249997Swkoszek } 1194249997Swkoszek } 1195249997Swkoszek if ((mask & IFCAP_RXCSUM) != 0) { 1196249997Swkoszek if ((ifr->ifr_reqcap & IFCAP_RXCSUM) != 0) { 1197249997Swkoszek /* Turn on RX checksumming. */ 1198249997Swkoszek ifp->if_capenable |= (IFCAP_RXCSUM | 1199249997Swkoszek IFCAP_RXCSUM_IPV6); 1200249997Swkoszek WR4(sc, CGEM_NET_CFG, 1201249997Swkoszek RD4(sc, CGEM_NET_CFG) | 1202249997Swkoszek CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN); 1203249997Swkoszek } else { 1204249997Swkoszek /* Turn off RX checksumming. */ 1205249997Swkoszek ifp->if_capenable &= ~(IFCAP_RXCSUM | 1206249997Swkoszek IFCAP_RXCSUM_IPV6); 1207249997Swkoszek WR4(sc, CGEM_NET_CFG, 1208249997Swkoszek RD4(sc, CGEM_NET_CFG) & 1209249997Swkoszek ~CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN); 1210249997Swkoszek } 1211249997Swkoszek } 1212273645Sian if ((ifp->if_capenable & (IFCAP_RXCSUM | IFCAP_TXCSUM)) == 1213273645Sian (IFCAP_RXCSUM | IFCAP_TXCSUM)) 1214273645Sian ifp->if_capenable |= IFCAP_VLAN_HWCSUM; 1215273645Sian else 1216273645Sian ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 1217249997Swkoszek 1218249997Swkoszek CGEM_UNLOCK(sc); 1219249997Swkoszek break; 1220249997Swkoszek default: 1221249997Swkoszek error = ether_ioctl(ifp, cmd, data); 1222249997Swkoszek break; 1223249997Swkoszek } 1224249997Swkoszek 1225249997Swkoszek return (error); 1226249997Swkoszek} 1227249997Swkoszek 1228249997Swkoszek/* MII bus support routines. 1229249997Swkoszek */ 1230249997Swkoszekstatic void 1231249997Swkoszekcgem_child_detached(device_t dev, device_t child) 1232249997Swkoszek{ 1233249997Swkoszek struct cgem_softc *sc = device_get_softc(dev); 1234273645Sian 1235249997Swkoszek if (child == sc->miibus) 1236249997Swkoszek sc->miibus = NULL; 1237249997Swkoszek} 1238249997Swkoszek 1239249997Swkoszekstatic int 1240249997Swkoszekcgem_ifmedia_upd(struct ifnet *ifp) 1241249997Swkoszek{ 1242249997Swkoszek struct cgem_softc *sc = (struct cgem_softc *) ifp->if_softc; 1243249997Swkoszek struct mii_data *mii; 1244273645Sian struct mii_softc *miisc; 1245273645Sian int error = 0; 1246249997Swkoszek 1247249997Swkoszek mii = device_get_softc(sc->miibus); 1248249997Swkoszek CGEM_LOCK(sc); 1249273645Sian if ((ifp->if_flags & IFF_UP) != 0) { 1250273645Sian LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1251273645Sian PHY_RESET(miisc); 1252273645Sian error = mii_mediachg(mii); 1253273645Sian } 1254249997Swkoszek CGEM_UNLOCK(sc); 1255273645Sian 1256273645Sian return (error); 1257249997Swkoszek} 1258249997Swkoszek 1259249997Swkoszekstatic void 1260249997Swkoszekcgem_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1261249997Swkoszek{ 1262249997Swkoszek struct cgem_softc *sc = (struct cgem_softc *) ifp->if_softc; 1263249997Swkoszek struct mii_data *mii; 1264249997Swkoszek 1265249997Swkoszek mii = device_get_softc(sc->miibus); 1266249997Swkoszek CGEM_LOCK(sc); 1267249997Swkoszek mii_pollstat(mii); 1268249997Swkoszek ifmr->ifm_active = mii->mii_media_active; 1269249997Swkoszek ifmr->ifm_status = mii->mii_media_status; 1270249997Swkoszek CGEM_UNLOCK(sc); 1271249997Swkoszek} 1272249997Swkoszek 1273249997Swkoszekstatic int 1274249997Swkoszekcgem_miibus_readreg(device_t dev, int phy, int reg) 1275249997Swkoszek{ 1276249997Swkoszek struct cgem_softc *sc = device_get_softc(dev); 1277249997Swkoszek int tries, val; 1278249997Swkoszek 1279249997Swkoszek WR4(sc, CGEM_PHY_MAINT, 1280249997Swkoszek CGEM_PHY_MAINT_CLAUSE_22 | CGEM_PHY_MAINT_MUST_10 | 1281249997Swkoszek CGEM_PHY_MAINT_OP_READ | 1282249997Swkoszek (phy << CGEM_PHY_MAINT_PHY_ADDR_SHIFT) | 1283249997Swkoszek (reg << CGEM_PHY_MAINT_REG_ADDR_SHIFT)); 1284249997Swkoszek 1285249997Swkoszek /* Wait for completion. */ 1286249997Swkoszek tries=0; 1287249997Swkoszek while ((RD4(sc, CGEM_NET_STAT) & CGEM_NET_STAT_PHY_MGMT_IDLE) == 0) { 1288249997Swkoszek DELAY(5); 1289249997Swkoszek if (++tries > 200) { 1290249997Swkoszek device_printf(dev, "phy read timeout: %d\n", reg); 1291249997Swkoszek return (-1); 1292249997Swkoszek } 1293249997Swkoszek } 1294249997Swkoszek 1295249997Swkoszek val = RD4(sc, CGEM_PHY_MAINT) & CGEM_PHY_MAINT_DATA_MASK; 1296249997Swkoszek 1297273645Sian if (reg == MII_EXTSR) 1298273645Sian /* 1299273645Sian * MAC does not support half-duplex at gig speeds. 1300273645Sian * Let mii(4) exclude the capability. 1301273645Sian */ 1302273645Sian val &= ~(EXTSR_1000XHDX | EXTSR_1000THDX); 1303273645Sian 1304249997Swkoszek return (val); 1305249997Swkoszek} 1306249997Swkoszek 1307249997Swkoszekstatic int 1308249997Swkoszekcgem_miibus_writereg(device_t dev, int phy, int reg, int data) 1309249997Swkoszek{ 1310249997Swkoszek struct cgem_softc *sc = device_get_softc(dev); 1311249997Swkoszek int tries; 1312249997Swkoszek 1313249997Swkoszek WR4(sc, CGEM_PHY_MAINT, 1314249997Swkoszek CGEM_PHY_MAINT_CLAUSE_22 | CGEM_PHY_MAINT_MUST_10 | 1315249997Swkoszek CGEM_PHY_MAINT_OP_WRITE | 1316249997Swkoszek (phy << CGEM_PHY_MAINT_PHY_ADDR_SHIFT) | 1317249997Swkoszek (reg << CGEM_PHY_MAINT_REG_ADDR_SHIFT) | 1318249997Swkoszek (data & CGEM_PHY_MAINT_DATA_MASK)); 1319249997Swkoszek 1320249997Swkoszek /* Wait for completion. */ 1321249997Swkoszek tries = 0; 1322249997Swkoszek while ((RD4(sc, CGEM_NET_STAT) & CGEM_NET_STAT_PHY_MGMT_IDLE) == 0) { 1323249997Swkoszek DELAY(5); 1324249997Swkoszek if (++tries > 200) { 1325249997Swkoszek device_printf(dev, "phy write timeout: %d\n", reg); 1326249997Swkoszek return (-1); 1327249997Swkoszek } 1328249997Swkoszek } 1329249997Swkoszek 1330249997Swkoszek return (0); 1331249997Swkoszek} 1332249997Swkoszek 1333273645Sianstatic void 1334273645Siancgem_miibus_statchg(device_t dev) 1335273645Sian{ 1336273645Sian struct cgem_softc *sc = device_get_softc(dev); 1337273645Sian struct mii_data *mii = device_get_softc(sc->miibus); 1338249997Swkoszek 1339273645Sian CGEM_ASSERT_LOCKED(sc); 1340273645Sian 1341273645Sian if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1342273645Sian (IFM_ACTIVE | IFM_AVALID) && 1343273645Sian sc->mii_media_active != mii->mii_media_active) 1344273645Sian cgem_mediachange(sc, mii); 1345273645Sian} 1346273645Sian 1347273645Sianstatic void 1348273645Siancgem_miibus_linkchg(device_t dev) 1349273645Sian{ 1350273645Sian struct cgem_softc *sc = device_get_softc(dev); 1351273645Sian struct mii_data *mii = device_get_softc(sc->miibus); 1352273645Sian 1353273645Sian CGEM_ASSERT_LOCKED(sc); 1354273645Sian 1355273645Sian if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1356273645Sian (IFM_ACTIVE | IFM_AVALID) && 1357273645Sian sc->mii_media_active != mii->mii_media_active) 1358273645Sian cgem_mediachange(sc, mii); 1359273645Sian} 1360273645Sian 1361273645Sian/* 1362273645Sian * Overridable weak symbol cgem_set_ref_clk(). This allows platforms to 1363273645Sian * provide a function to set the cgem's reference clock. 1364273645Sian */ 1365273645Sianstatic int __used 1366273645Siancgem_default_set_ref_clk(int unit, int frequency) 1367273645Sian{ 1368273645Sian 1369273645Sian return 0; 1370273645Sian} 1371273645Sian__weak_reference(cgem_default_set_ref_clk, cgem_set_ref_clk); 1372273645Sian 1373273645Sian/* Call to set reference clock and network config bits according to media. */ 1374273645Sianstatic void 1375273645Siancgem_mediachange(struct cgem_softc *sc, struct mii_data *mii) 1376273645Sian{ 1377273645Sian uint32_t net_cfg; 1378273645Sian int ref_clk_freq; 1379273645Sian 1380273645Sian CGEM_ASSERT_LOCKED(sc); 1381273645Sian 1382273645Sian /* Update hardware to reflect media. */ 1383273645Sian net_cfg = RD4(sc, CGEM_NET_CFG); 1384273645Sian net_cfg &= ~(CGEM_NET_CFG_SPEED100 | CGEM_NET_CFG_GIGE_EN | 1385273645Sian CGEM_NET_CFG_FULL_DUPLEX); 1386273645Sian 1387273645Sian switch (IFM_SUBTYPE(mii->mii_media_active)) { 1388273645Sian case IFM_1000_T: 1389273645Sian net_cfg |= (CGEM_NET_CFG_SPEED100 | 1390273645Sian CGEM_NET_CFG_GIGE_EN); 1391273645Sian ref_clk_freq = 125000000; 1392273645Sian break; 1393273645Sian case IFM_100_TX: 1394273645Sian net_cfg |= CGEM_NET_CFG_SPEED100; 1395273645Sian ref_clk_freq = 25000000; 1396273645Sian break; 1397273645Sian default: 1398273645Sian ref_clk_freq = 2500000; 1399273645Sian } 1400273645Sian 1401273645Sian if ((mii->mii_media_active & IFM_FDX) != 0) 1402273645Sian net_cfg |= CGEM_NET_CFG_FULL_DUPLEX; 1403273645Sian 1404273645Sian WR4(sc, CGEM_NET_CFG, net_cfg); 1405273645Sian 1406273645Sian /* Set the reference clock if necessary. */ 1407273645Sian if (cgem_set_ref_clk(sc->ref_clk_num, ref_clk_freq)) 1408273645Sian device_printf(sc->dev, "cgem_mediachange: " 1409273645Sian "could not set ref clk%d to %d.\n", 1410273645Sian sc->ref_clk_num, ref_clk_freq); 1411273645Sian 1412273645Sian sc->mii_media_active = mii->mii_media_active; 1413273645Sian} 1414273645Sian 1415273645Sianstatic void 1416273645Siancgem_add_sysctls(device_t dev) 1417273645Sian{ 1418273645Sian struct cgem_softc *sc = device_get_softc(dev); 1419273645Sian struct sysctl_ctx_list *ctx; 1420273645Sian struct sysctl_oid_list *child; 1421273645Sian struct sysctl_oid *tree; 1422273645Sian 1423273645Sian ctx = device_get_sysctl_ctx(dev); 1424273645Sian child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 1425273645Sian 1426273645Sian SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rxbufs", CTLFLAG_RW, 1427273645Sian &sc->rxbufs, 0, 1428273645Sian "Number receive buffers to provide"); 1429273645Sian 1430273645Sian SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rxhangwar", CTLFLAG_RW, 1431273645Sian &sc->rxhangwar, 0, 1432273645Sian "Enable receive hang work-around"); 1433273645Sian 1434273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxoverruns", CTLFLAG_RD, 1435273645Sian &sc->rxoverruns, 0, 1436273645Sian "Receive overrun events"); 1437273645Sian 1438273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxnobufs", CTLFLAG_RD, 1439273645Sian &sc->rxnobufs, 0, 1440273645Sian "Receive buf queue empty events"); 1441273645Sian 1442273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxdmamapfails", CTLFLAG_RD, 1443273645Sian &sc->rxdmamapfails, 0, 1444273645Sian "Receive DMA map failures"); 1445273645Sian 1446273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txfull", CTLFLAG_RD, 1447273645Sian &sc->txfull, 0, 1448273645Sian "Transmit ring full events"); 1449273645Sian 1450273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdmamapfails", CTLFLAG_RD, 1451273645Sian &sc->txdmamapfails, 0, 1452273645Sian "Transmit DMA map failures"); 1453273645Sian 1454273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdefrags", CTLFLAG_RD, 1455273645Sian &sc->txdefrags, 0, 1456273645Sian "Transmit m_defrag() calls"); 1457273645Sian 1458273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdefragfails", CTLFLAG_RD, 1459273645Sian &sc->txdefragfails, 0, 1460273645Sian "Transmit m_defrag() failures"); 1461273645Sian 1462273645Sian tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1463273645Sian NULL, "GEM statistics"); 1464273645Sian child = SYSCTL_CHILDREN(tree); 1465273645Sian 1466273645Sian SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, "tx_bytes", CTLFLAG_RD, 1467273645Sian &sc->stats.tx_bytes, "Total bytes transmitted"); 1468273645Sian 1469273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames", CTLFLAG_RD, 1470273645Sian &sc->stats.tx_frames, 0, "Total frames transmitted"); 1471273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_bcast", CTLFLAG_RD, 1472273645Sian &sc->stats.tx_frames_bcast, 0, 1473273645Sian "Number broadcast frames transmitted"); 1474273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_multi", CTLFLAG_RD, 1475273645Sian &sc->stats.tx_frames_multi, 0, 1476273645Sian "Number multicast frames transmitted"); 1477273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_pause", 1478273645Sian CTLFLAG_RD, &sc->stats.tx_frames_pause, 0, 1479273645Sian "Number pause frames transmitted"); 1480273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_64b", CTLFLAG_RD, 1481273645Sian &sc->stats.tx_frames_64b, 0, 1482273645Sian "Number frames transmitted of size 64 bytes or less"); 1483273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_65to127b", CTLFLAG_RD, 1484273645Sian &sc->stats.tx_frames_65to127b, 0, 1485273645Sian "Number frames transmitted of size 65-127 bytes"); 1486273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_128to255b", 1487273645Sian CTLFLAG_RD, &sc->stats.tx_frames_128to255b, 0, 1488273645Sian "Number frames transmitted of size 128-255 bytes"); 1489273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_256to511b", 1490273645Sian CTLFLAG_RD, &sc->stats.tx_frames_256to511b, 0, 1491273645Sian "Number frames transmitted of size 256-511 bytes"); 1492273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_512to1023b", 1493273645Sian CTLFLAG_RD, &sc->stats.tx_frames_512to1023b, 0, 1494273645Sian "Number frames transmitted of size 512-1023 bytes"); 1495273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_1024to1536b", 1496273645Sian CTLFLAG_RD, &sc->stats.tx_frames_1024to1536b, 0, 1497273645Sian "Number frames transmitted of size 1024-1536 bytes"); 1498273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_under_runs", 1499273645Sian CTLFLAG_RD, &sc->stats.tx_under_runs, 0, 1500273645Sian "Number transmit under-run events"); 1501273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_single_collisn", 1502273645Sian CTLFLAG_RD, &sc->stats.tx_single_collisn, 0, 1503273645Sian "Number single-collision transmit frames"); 1504273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_multi_collisn", 1505273645Sian CTLFLAG_RD, &sc->stats.tx_multi_collisn, 0, 1506273645Sian "Number multi-collision transmit frames"); 1507273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_excsv_collisn", 1508273645Sian CTLFLAG_RD, &sc->stats.tx_excsv_collisn, 0, 1509273645Sian "Number excessive collision transmit frames"); 1510273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_late_collisn", 1511273645Sian CTLFLAG_RD, &sc->stats.tx_late_collisn, 0, 1512273645Sian "Number late-collision transmit frames"); 1513273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_deferred_frames", 1514273645Sian CTLFLAG_RD, &sc->stats.tx_deferred_frames, 0, 1515273645Sian "Number deferred transmit frames"); 1516273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_carrier_sense_errs", 1517273645Sian CTLFLAG_RD, &sc->stats.tx_carrier_sense_errs, 0, 1518273645Sian "Number carrier sense errors on transmit"); 1519273645Sian 1520273645Sian SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, "rx_bytes", CTLFLAG_RD, 1521273645Sian &sc->stats.rx_bytes, "Total bytes received"); 1522273645Sian 1523273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames", CTLFLAG_RD, 1524273645Sian &sc->stats.rx_frames, 0, "Total frames received"); 1525273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_bcast", 1526273645Sian CTLFLAG_RD, &sc->stats.rx_frames_bcast, 0, 1527273645Sian "Number broadcast frames received"); 1528273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_multi", 1529273645Sian CTLFLAG_RD, &sc->stats.rx_frames_multi, 0, 1530273645Sian "Number multicast frames received"); 1531273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_pause", 1532273645Sian CTLFLAG_RD, &sc->stats.rx_frames_pause, 0, 1533273645Sian "Number pause frames received"); 1534273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_64b", 1535273645Sian CTLFLAG_RD, &sc->stats.rx_frames_64b, 0, 1536273645Sian "Number frames received of size 64 bytes or less"); 1537273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_65to127b", 1538273645Sian CTLFLAG_RD, &sc->stats.rx_frames_65to127b, 0, 1539273645Sian "Number frames received of size 65-127 bytes"); 1540273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_128to255b", 1541273645Sian CTLFLAG_RD, &sc->stats.rx_frames_128to255b, 0, 1542273645Sian "Number frames received of size 128-255 bytes"); 1543273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_256to511b", 1544273645Sian CTLFLAG_RD, &sc->stats.rx_frames_256to511b, 0, 1545273645Sian "Number frames received of size 256-511 bytes"); 1546273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_512to1023b", 1547273645Sian CTLFLAG_RD, &sc->stats.rx_frames_512to1023b, 0, 1548273645Sian "Number frames received of size 512-1023 bytes"); 1549273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_1024to1536b", 1550273645Sian CTLFLAG_RD, &sc->stats.rx_frames_1024to1536b, 0, 1551273645Sian "Number frames received of size 1024-1536 bytes"); 1552273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_undersize", 1553273645Sian CTLFLAG_RD, &sc->stats.rx_frames_undersize, 0, 1554273645Sian "Number undersize frames received"); 1555273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_oversize", 1556273645Sian CTLFLAG_RD, &sc->stats.rx_frames_oversize, 0, 1557273645Sian "Number oversize frames received"); 1558273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_jabber", 1559273645Sian CTLFLAG_RD, &sc->stats.rx_frames_jabber, 0, 1560273645Sian "Number jabber frames received"); 1561273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_fcs_errs", 1562273645Sian CTLFLAG_RD, &sc->stats.rx_frames_fcs_errs, 0, 1563273645Sian "Number frames received with FCS errors"); 1564273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_length_errs", 1565273645Sian CTLFLAG_RD, &sc->stats.rx_frames_length_errs, 0, 1566273645Sian "Number frames received with length errors"); 1567273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_symbol_errs", 1568273645Sian CTLFLAG_RD, &sc->stats.rx_symbol_errs, 0, 1569273645Sian "Number receive symbol errors"); 1570273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_align_errs", 1571273645Sian CTLFLAG_RD, &sc->stats.rx_align_errs, 0, 1572273645Sian "Number receive alignment errors"); 1573273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_resource_errs", 1574273645Sian CTLFLAG_RD, &sc->stats.rx_resource_errs, 0, 1575273645Sian "Number frames received when no rx buffer available"); 1576273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_overrun_errs", 1577273645Sian CTLFLAG_RD, &sc->stats.rx_overrun_errs, 0, 1578273645Sian "Number frames received but not copied due to " 1579273645Sian "receive overrun"); 1580273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_ip_hdr_csum_errs", 1581273645Sian CTLFLAG_RD, &sc->stats.rx_ip_hdr_csum_errs, 0, 1582273645Sian "Number frames received with IP header checksum " 1583273645Sian "errors"); 1584273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_tcp_csum_errs", 1585273645Sian CTLFLAG_RD, &sc->stats.rx_tcp_csum_errs, 0, 1586273645Sian "Number frames received with TCP checksum errors"); 1587273645Sian SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_udp_csum_errs", 1588273645Sian CTLFLAG_RD, &sc->stats.rx_udp_csum_errs, 0, 1589273645Sian "Number frames received with UDP checksum errors"); 1590273645Sian} 1591273645Sian 1592273645Sian 1593249997Swkoszekstatic int 1594249997Swkoszekcgem_probe(device_t dev) 1595249997Swkoszek{ 1596249997Swkoszek 1597249997Swkoszek if (!ofw_bus_is_compatible(dev, "cadence,gem")) 1598249997Swkoszek return (ENXIO); 1599249997Swkoszek 1600249997Swkoszek device_set_desc(dev, "Cadence CGEM Gigabit Ethernet Interface"); 1601249997Swkoszek return (0); 1602249997Swkoszek} 1603249997Swkoszek 1604249997Swkoszekstatic int 1605249997Swkoszekcgem_attach(device_t dev) 1606249997Swkoszek{ 1607249997Swkoszek struct cgem_softc *sc = device_get_softc(dev); 1608249997Swkoszek struct ifnet *ifp = NULL; 1609273645Sian phandle_t node; 1610273645Sian pcell_t cell; 1611249997Swkoszek int rid, err; 1612249997Swkoszek u_char eaddr[ETHER_ADDR_LEN]; 1613249997Swkoszek 1614249997Swkoszek sc->dev = dev; 1615249997Swkoszek CGEM_LOCK_INIT(sc); 1616249997Swkoszek 1617273645Sian /* Get reference clock number and base divider from fdt. */ 1618273645Sian node = ofw_bus_get_node(dev); 1619273645Sian sc->ref_clk_num = 0; 1620273645Sian if (OF_getprop(node, "ref-clock-num", &cell, sizeof(cell)) > 0) 1621273645Sian sc->ref_clk_num = fdt32_to_cpu(cell); 1622273645Sian 1623249997Swkoszek /* Get memory resource. */ 1624249997Swkoszek rid = 0; 1625249997Swkoszek sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1626249997Swkoszek RF_ACTIVE); 1627249997Swkoszek if (sc->mem_res == NULL) { 1628249997Swkoszek device_printf(dev, "could not allocate memory resources.\n"); 1629249997Swkoszek return (ENOMEM); 1630249997Swkoszek } 1631249997Swkoszek 1632249997Swkoszek /* Get IRQ resource. */ 1633249997Swkoszek rid = 0; 1634249997Swkoszek sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1635249997Swkoszek RF_ACTIVE); 1636249997Swkoszek if (sc->irq_res == NULL) { 1637249997Swkoszek device_printf(dev, "could not allocate interrupt resource.\n"); 1638249997Swkoszek cgem_detach(dev); 1639249997Swkoszek return (ENOMEM); 1640249997Swkoszek } 1641249997Swkoszek 1642273645Sian /* Set up ifnet structure. */ 1643249997Swkoszek ifp = sc->ifp = if_alloc(IFT_ETHER); 1644249997Swkoszek if (ifp == NULL) { 1645249997Swkoszek device_printf(dev, "could not allocate ifnet structure\n"); 1646249997Swkoszek cgem_detach(dev); 1647249997Swkoszek return (ENOMEM); 1648249997Swkoszek } 1649273645Sian ifp->if_softc = sc; 1650273645Sian if_initname(ifp, IF_CGEM_NAME, device_get_unit(dev)); 1651273645Sian ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1652273645Sian ifp->if_start = cgem_start; 1653273645Sian ifp->if_ioctl = cgem_ioctl; 1654273645Sian ifp->if_init = cgem_init; 1655273645Sian ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | 1656273645Sian IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM; 1657273645Sian /* Disable hardware checksumming by default. */ 1658273645Sian ifp->if_hwassist = 0; 1659273645Sian ifp->if_capenable = ifp->if_capabilities & 1660273645Sian ~(IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | IFCAP_VLAN_HWCSUM); 1661273645Sian ifp->if_snd.ifq_drv_maxlen = CGEM_NUM_TX_DESCS; 1662273645Sian IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1663273645Sian IFQ_SET_READY(&ifp->if_snd); 1664249997Swkoszek 1665273645Sian sc->if_old_flags = ifp->if_flags; 1666273645Sian sc->rxbufs = DEFAULT_NUM_RX_BUFS; 1667273645Sian sc->rxhangwar = 1; 1668249997Swkoszek 1669249997Swkoszek /* Reset hardware. */ 1670273645Sian CGEM_LOCK(sc); 1671249997Swkoszek cgem_reset(sc); 1672273645Sian CGEM_UNLOCK(sc); 1673249997Swkoszek 1674249997Swkoszek /* Attach phy to mii bus. */ 1675249997Swkoszek err = mii_attach(dev, &sc->miibus, ifp, 1676249997Swkoszek cgem_ifmedia_upd, cgem_ifmedia_sts, 1677249997Swkoszek BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 1678249997Swkoszek if (err) { 1679249997Swkoszek device_printf(dev, "attaching PHYs failed\n"); 1680249997Swkoszek cgem_detach(dev); 1681249997Swkoszek return (err); 1682249997Swkoszek } 1683249997Swkoszek 1684249997Swkoszek /* Set up TX and RX descriptor area. */ 1685249997Swkoszek err = cgem_setup_descs(sc); 1686249997Swkoszek if (err) { 1687249997Swkoszek device_printf(dev, "could not set up dma mem for descs.\n"); 1688249997Swkoszek cgem_detach(dev); 1689249997Swkoszek return (ENOMEM); 1690249997Swkoszek } 1691249997Swkoszek 1692249997Swkoszek /* Get a MAC address. */ 1693249997Swkoszek cgem_get_mac(sc, eaddr); 1694249997Swkoszek 1695249997Swkoszek /* Start ticks. */ 1696249997Swkoszek callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 1697249997Swkoszek 1698249997Swkoszek ether_ifattach(ifp, eaddr); 1699249997Swkoszek 1700249997Swkoszek err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE | 1701249997Swkoszek INTR_EXCL, NULL, cgem_intr, sc, &sc->intrhand); 1702249997Swkoszek if (err) { 1703249997Swkoszek device_printf(dev, "could not set interrupt handler.\n"); 1704249997Swkoszek ether_ifdetach(ifp); 1705249997Swkoszek cgem_detach(dev); 1706249997Swkoszek return (err); 1707249997Swkoszek } 1708249997Swkoszek 1709273645Sian cgem_add_sysctls(dev); 1710249997Swkoszek 1711249997Swkoszek return (0); 1712249997Swkoszek} 1713249997Swkoszek 1714249997Swkoszekstatic int 1715249997Swkoszekcgem_detach(device_t dev) 1716249997Swkoszek{ 1717249997Swkoszek struct cgem_softc *sc = device_get_softc(dev); 1718249997Swkoszek int i; 1719249997Swkoszek 1720249997Swkoszek if (sc == NULL) 1721249997Swkoszek return (ENODEV); 1722249997Swkoszek 1723249997Swkoszek if (device_is_attached(dev)) { 1724249997Swkoszek CGEM_LOCK(sc); 1725249997Swkoszek cgem_stop(sc); 1726249997Swkoszek CGEM_UNLOCK(sc); 1727249997Swkoszek callout_drain(&sc->tick_ch); 1728249997Swkoszek sc->ifp->if_flags &= ~IFF_UP; 1729249997Swkoszek ether_ifdetach(sc->ifp); 1730249997Swkoszek } 1731249997Swkoszek 1732249997Swkoszek if (sc->miibus != NULL) { 1733249997Swkoszek device_delete_child(dev, sc->miibus); 1734249997Swkoszek sc->miibus = NULL; 1735249997Swkoszek } 1736249997Swkoszek 1737273645Sian /* Release resources. */ 1738249997Swkoszek if (sc->mem_res != NULL) { 1739249997Swkoszek bus_release_resource(dev, SYS_RES_MEMORY, 1740249997Swkoszek rman_get_rid(sc->mem_res), sc->mem_res); 1741249997Swkoszek sc->mem_res = NULL; 1742249997Swkoszek } 1743249997Swkoszek if (sc->irq_res != NULL) { 1744249997Swkoszek if (sc->intrhand) 1745249997Swkoszek bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 1746249997Swkoszek bus_release_resource(dev, SYS_RES_IRQ, 1747249997Swkoszek rman_get_rid(sc->irq_res), sc->irq_res); 1748249997Swkoszek sc->irq_res = NULL; 1749249997Swkoszek } 1750249997Swkoszek 1751249997Swkoszek /* Release DMA resources. */ 1752249997Swkoszek if (sc->rxring_dma_map != NULL) { 1753249997Swkoszek bus_dmamem_free(sc->desc_dma_tag, sc->rxring, 1754249997Swkoszek sc->rxring_dma_map); 1755249997Swkoszek sc->rxring_dma_map = NULL; 1756249997Swkoszek for (i = 0; i < CGEM_NUM_RX_DESCS; i++) 1757249997Swkoszek if (sc->rxring_m_dmamap[i] != NULL) { 1758249997Swkoszek bus_dmamap_destroy(sc->mbuf_dma_tag, 1759249997Swkoszek sc->rxring_m_dmamap[i]); 1760249997Swkoszek sc->rxring_m_dmamap[i] = NULL; 1761249997Swkoszek } 1762249997Swkoszek } 1763249997Swkoszek if (sc->txring_dma_map != NULL) { 1764249997Swkoszek bus_dmamem_free(sc->desc_dma_tag, sc->txring, 1765249997Swkoszek sc->txring_dma_map); 1766249997Swkoszek sc->txring_dma_map = NULL; 1767249997Swkoszek for (i = 0; i < CGEM_NUM_TX_DESCS; i++) 1768249997Swkoszek if (sc->txring_m_dmamap[i] != NULL) { 1769249997Swkoszek bus_dmamap_destroy(sc->mbuf_dma_tag, 1770249997Swkoszek sc->txring_m_dmamap[i]); 1771249997Swkoszek sc->txring_m_dmamap[i] = NULL; 1772249997Swkoszek } 1773249997Swkoszek } 1774249997Swkoszek if (sc->desc_dma_tag != NULL) { 1775249997Swkoszek bus_dma_tag_destroy(sc->desc_dma_tag); 1776249997Swkoszek sc->desc_dma_tag = NULL; 1777249997Swkoszek } 1778249997Swkoszek if (sc->mbuf_dma_tag != NULL) { 1779249997Swkoszek bus_dma_tag_destroy(sc->mbuf_dma_tag); 1780249997Swkoszek sc->mbuf_dma_tag = NULL; 1781249997Swkoszek } 1782249997Swkoszek 1783249997Swkoszek bus_generic_detach(dev); 1784249997Swkoszek 1785249997Swkoszek CGEM_LOCK_DESTROY(sc); 1786249997Swkoszek 1787249997Swkoszek return (0); 1788249997Swkoszek} 1789249997Swkoszek 1790249997Swkoszekstatic device_method_t cgem_methods[] = { 1791249997Swkoszek /* Device interface */ 1792249997Swkoszek DEVMETHOD(device_probe, cgem_probe), 1793249997Swkoszek DEVMETHOD(device_attach, cgem_attach), 1794249997Swkoszek DEVMETHOD(device_detach, cgem_detach), 1795249997Swkoszek 1796249997Swkoszek /* Bus interface */ 1797249997Swkoszek DEVMETHOD(bus_child_detached, cgem_child_detached), 1798249997Swkoszek 1799249997Swkoszek /* MII interface */ 1800249997Swkoszek DEVMETHOD(miibus_readreg, cgem_miibus_readreg), 1801249997Swkoszek DEVMETHOD(miibus_writereg, cgem_miibus_writereg), 1802273645Sian DEVMETHOD(miibus_statchg, cgem_miibus_statchg), 1803273645Sian DEVMETHOD(miibus_linkchg, cgem_miibus_linkchg), 1804249997Swkoszek 1805249997Swkoszek DEVMETHOD_END 1806249997Swkoszek}; 1807249997Swkoszek 1808249997Swkoszekstatic driver_t cgem_driver = { 1809249997Swkoszek "cgem", 1810249997Swkoszek cgem_methods, 1811249997Swkoszek sizeof(struct cgem_softc), 1812249997Swkoszek}; 1813249997Swkoszek 1814249997SwkoszekDRIVER_MODULE(cgem, simplebus, cgem_driver, cgem_devclass, NULL, NULL); 1815249997SwkoszekDRIVER_MODULE(miibus, cgem, miibus_driver, miibus_devclass, NULL, NULL); 1816249997SwkoszekMODULE_DEPEND(cgem, miibus, 1, 1, 1); 1817249997SwkoszekMODULE_DEPEND(cgem, ether, 1, 1, 1); 1818