1256806Sian/*- 2256806Sian * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3256806Sian * All rights reserved. 4256806Sian * 5256806Sian * Redistribution and use in source and binary forms, with or without 6256806Sian * modification, are permitted provided that the following conditions 7256806Sian * are met: 8256806Sian * 1. Redistributions of source code must retain the above copyright 9256806Sian * notice, this list of conditions and the following disclaimer. 10256806Sian * 2. Redistributions in binary form must reproduce the above copyright 11256806Sian * notice, this list of conditions and the following disclaimer in the 12256806Sian * documentation and/or other materials provided with the distribution. 13256806Sian * 14256806Sian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15256806Sian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16256806Sian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17256806Sian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18256806Sian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19256806Sian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20256806Sian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21256806Sian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22256806Sian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23256806Sian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24256806Sian * SUCH DAMAGE. 25256806Sian * 26256806Sian */ 27256806Sian 28256806Sian#include <sys/cdefs.h> 29256806Sian__FBSDID("$FreeBSD$"); 30256806Sian 31256806Sian/* 32256806Sian * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among 33256806Sian * others. Also works for the ENET Gigibit controller found on imx6 and imx28, 34256806Sian * but the driver doesn't currently use any of the ENET advanced features other 35256806Sian * than enabling gigabit. 36256806Sian * 37256806Sian * The interface name 'fec' is already taken by netgraph's Fast Etherchannel 38256806Sian * (netgraph/ng_fec.c), so we use 'ffec'. 39256806Sian * 40256806Sian * Requires an FDT entry with at least these properties: 41256806Sian * fec: ethernet@02188000 { 42256806Sian * compatible = "fsl,imxNN-fec"; 43256806Sian * reg = <0x02188000 0x4000>; 44256806Sian * interrupts = <150 151>; 45256806Sian * phy-mode = "rgmii"; 46256806Sian * phy-disable-preamble; // optional 47256806Sian * }; 48256806Sian * The second interrupt number is for IEEE-1588, and is not currently used; it 49256806Sian * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii". 50256806Sian * There is also an optional property, phy-disable-preamble, which if present 51256806Sian * will disable the preamble bits, cutting the size of each mdio transaction 52256806Sian * (and thus the busy-wait time) in half. 53256806Sian */ 54256806Sian 55256806Sian#include <sys/param.h> 56256806Sian#include <sys/systm.h> 57256806Sian#include <sys/bus.h> 58256806Sian#include <sys/endian.h> 59256806Sian#include <sys/kernel.h> 60256806Sian#include <sys/lock.h> 61256806Sian#include <sys/malloc.h> 62256806Sian#include <sys/mbuf.h> 63256806Sian#include <sys/module.h> 64256806Sian#include <sys/mutex.h> 65256806Sian#include <sys/rman.h> 66256806Sian#include <sys/socket.h> 67256806Sian#include <sys/sockio.h> 68256806Sian#include <sys/sysctl.h> 69256806Sian 70256806Sian#include <machine/bus.h> 71256806Sian 72256806Sian#include <net/bpf.h> 73256806Sian#include <net/if.h> 74256806Sian#include <net/ethernet.h> 75256806Sian#include <net/if_dl.h> 76256806Sian#include <net/if_media.h> 77256806Sian#include <net/if_types.h> 78256806Sian#include <net/if_var.h> 79256806Sian#include <net/if_vlan_var.h> 80256806Sian 81256806Sian#include <dev/ffec/if_ffecreg.h> 82256806Sian#include <dev/ofw/ofw_bus.h> 83256806Sian#include <dev/ofw/ofw_bus_subr.h> 84256806Sian#include <dev/mii/mii.h> 85256806Sian#include <dev/mii/miivar.h> 86256806Sian#include "miibus_if.h" 87256806Sian 88256806Sian/* 89259317Sian * There are small differences in the hardware on various SoCs. Not every SoC 90259317Sian * we support has its own FECTYPE; most work as GENERIC and only the ones that 91259317Sian * need different handling get their own entry. In addition to the types in 92259317Sian * this list, there are some flags below that can be ORed into the upper bits. 93259317Sian */ 94259317Sianenum { 95259317Sian FECTYPE_NONE, 96259317Sian FECTYPE_GENERIC, 97259317Sian FECTYPE_IMX53, 98259317Sian FECTYPE_IMX6, 99259317Sian}; 100259317Sian 101259317Sian/* 102259317Sian * Flags that describe general differences between the FEC hardware in various 103259317Sian * SoCs. These are ORed into the FECTYPE enum values. 104259317Sian */ 105259317Sian#define FECTYPE_MASK 0x0000ffff 106259317Sian#define FECFLAG_GBE (0x0001 << 16) 107259317Sian 108259317Sian/* 109259317Sian * Table of supported FDT compat strings and their associated FECTYPE values. 110259317Sian */ 111259317Sianstatic struct ofw_compat_data compat_data[] = { 112259317Sian {"fsl,imx51-fec", FECTYPE_GENERIC}, 113259317Sian {"fsl,imx53-fec", FECTYPE_IMX53}, 114259317Sian {"fsl,imx6q-fec", FECTYPE_IMX6 | FECFLAG_GBE}, 115259317Sian {"fsl,mvf600-fec", FECTYPE_GENERIC}, 116259317Sian {"fsl,vf-fec", FECTYPE_GENERIC}, 117259317Sian {NULL, FECTYPE_NONE}, 118259317Sian}; 119259317Sian 120259317Sian/* 121256806Sian * Driver data and defines. 122256806Sian */ 123256806Sian#define RX_DESC_COUNT 64 124256806Sian#define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT) 125256806Sian#define TX_DESC_COUNT 64 126256806Sian#define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT) 127256806Sian 128256806Sian#define WATCHDOG_TIMEOUT_SECS 5 129256806Sian#define STATS_HARVEST_INTERVAL 3 130256806Sian 131256806Sianstruct ffec_bufmap { 132256806Sian struct mbuf *mbuf; 133256806Sian bus_dmamap_t map; 134256806Sian}; 135256806Sian 136256806Sianenum { 137256806Sian PHY_CONN_UNKNOWN, 138256806Sian PHY_CONN_MII, 139256806Sian PHY_CONN_RMII, 140256806Sian PHY_CONN_RGMII 141256806Sian}; 142256806Sian 143256806Sianstruct ffec_softc { 144256806Sian device_t dev; 145256806Sian device_t miibus; 146256806Sian struct mii_data * mii_softc; 147256806Sian struct ifnet *ifp; 148256806Sian int if_flags; 149256806Sian struct mtx mtx; 150256806Sian struct resource *irq_res; 151256806Sian struct resource *mem_res; 152256806Sian void * intr_cookie; 153256806Sian struct callout ffec_callout; 154256806Sian uint8_t phy_conn_type; 155256806Sian uint8_t fectype; 156256806Sian boolean_t link_is_up; 157256806Sian boolean_t is_attached; 158256806Sian boolean_t is_detaching; 159256806Sian int tx_watchdog_count; 160256806Sian int stats_harvest_count; 161256806Sian 162256806Sian bus_dma_tag_t rxdesc_tag; 163256806Sian bus_dmamap_t rxdesc_map; 164256806Sian struct ffec_hwdesc *rxdesc_ring; 165256806Sian bus_addr_t rxdesc_ring_paddr; 166256806Sian bus_dma_tag_t rxbuf_tag; 167256806Sian struct ffec_bufmap rxbuf_map[RX_DESC_COUNT]; 168256806Sian uint32_t rx_idx; 169256806Sian 170256806Sian bus_dma_tag_t txdesc_tag; 171256806Sian bus_dmamap_t txdesc_map; 172256806Sian struct ffec_hwdesc *txdesc_ring; 173256806Sian bus_addr_t txdesc_ring_paddr; 174256806Sian bus_dma_tag_t txbuf_tag; 175256806Sian struct ffec_bufmap txbuf_map[RX_DESC_COUNT]; 176256806Sian uint32_t tx_idx_head; 177256806Sian uint32_t tx_idx_tail; 178256806Sian int txcount; 179256806Sian}; 180256806Sian 181256806Sian#define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx) 182256806Sian#define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 183256806Sian#define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \ 184256806Sian device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF) 185256806Sian#define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx); 186256806Sian#define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); 187256806Sian#define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); 188256806Sian 189256806Sianstatic void ffec_init_locked(struct ffec_softc *sc); 190256806Sianstatic void ffec_stop_locked(struct ffec_softc *sc); 191256806Sianstatic void ffec_txstart_locked(struct ffec_softc *sc); 192256806Sianstatic void ffec_txfinish_locked(struct ffec_softc *sc); 193256806Sian 194256806Sianstatic inline uint16_t 195256806SianRD2(struct ffec_softc *sc, bus_size_t off) 196256806Sian{ 197256806Sian 198256806Sian return (bus_read_2(sc->mem_res, off)); 199256806Sian} 200256806Sian 201256806Sianstatic inline void 202256806SianWR2(struct ffec_softc *sc, bus_size_t off, uint16_t val) 203256806Sian{ 204256806Sian 205256806Sian bus_write_2(sc->mem_res, off, val); 206256806Sian} 207256806Sian 208256806Sianstatic inline uint32_t 209256806SianRD4(struct ffec_softc *sc, bus_size_t off) 210256806Sian{ 211256806Sian 212256806Sian return (bus_read_4(sc->mem_res, off)); 213256806Sian} 214256806Sian 215256806Sianstatic inline void 216256806SianWR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) 217256806Sian{ 218256806Sian 219256806Sian bus_write_4(sc->mem_res, off, val); 220256806Sian} 221256806Sian 222256806Sianstatic inline uint32_t 223256806Siannext_rxidx(struct ffec_softc *sc, uint32_t curidx) 224256806Sian{ 225256806Sian 226256806Sian return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1); 227256806Sian} 228256806Sian 229256806Sianstatic inline uint32_t 230256806Siannext_txidx(struct ffec_softc *sc, uint32_t curidx) 231256806Sian{ 232256806Sian 233256806Sian return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1); 234256806Sian} 235256806Sian 236256806Sianstatic void 237256806Sianffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 238256806Sian{ 239256806Sian 240256806Sian if (error != 0) 241256806Sian return; 242256806Sian *(bus_addr_t *)arg = segs[0].ds_addr; 243256806Sian} 244256806Sian 245256806Sianstatic void 246256806Sianffec_miigasket_setup(struct ffec_softc *sc) 247256806Sian{ 248256806Sian uint32_t ifmode; 249256806Sian 250256806Sian /* 251256806Sian * We only need the gasket for MII and RMII connections on certain SoCs. 252256806Sian */ 253256806Sian 254259317Sian switch (sc->fectype & FECTYPE_MASK) 255256806Sian { 256256806Sian case FECTYPE_IMX53: 257256806Sian break; 258256806Sian default: 259256806Sian return; 260256806Sian } 261256806Sian 262256806Sian switch (sc->phy_conn_type) 263256806Sian { 264256806Sian case PHY_CONN_MII: 265256806Sian ifmode = 0; 266256806Sian break; 267256806Sian case PHY_CONN_RMII: 268256806Sian ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII; 269256806Sian break; 270256806Sian default: 271256806Sian return; 272256806Sian } 273256806Sian 274256806Sian /* 275256806Sian * Disable the gasket, configure for either MII or RMII, then enable. 276256806Sian */ 277256806Sian 278256806Sian WR2(sc, FEC_MIIGSK_ENR, 0); 279256806Sian while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) 280256806Sian continue; 281256806Sian 282256806Sian WR2(sc, FEC_MIIGSK_CFGR, ifmode); 283256806Sian 284256806Sian WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN); 285256806Sian while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)) 286256806Sian continue; 287256806Sian} 288256806Sian 289256806Sianstatic boolean_t 290256806Sianffec_miibus_iowait(struct ffec_softc *sc) 291256806Sian{ 292256806Sian uint32_t timeout; 293256806Sian 294256806Sian for (timeout = 10000; timeout != 0; --timeout) 295256806Sian if (RD4(sc, FEC_IER_REG) & FEC_IER_MII) 296256806Sian return (true); 297256806Sian 298256806Sian return (false); 299256806Sian} 300256806Sian 301256806Sianstatic int 302256806Sianffec_miibus_readreg(device_t dev, int phy, int reg) 303256806Sian{ 304256806Sian struct ffec_softc *sc; 305256806Sian int val; 306256806Sian 307256806Sian sc = device_get_softc(dev); 308256806Sian 309256806Sian WR4(sc, FEC_IER_REG, FEC_IER_MII); 310256806Sian 311256806Sian WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | 312256806Sian FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 313256806Sian ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 314256806Sian ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK)); 315256806Sian 316256806Sian if (!ffec_miibus_iowait(sc)) { 317256806Sian device_printf(dev, "timeout waiting for mii read\n"); 318256806Sian return (-1); /* All-ones is a symptom of bad mdio. */ 319256806Sian } 320256806Sian 321256806Sian val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK; 322256806Sian 323256806Sian return (val); 324256806Sian} 325256806Sian 326256806Sianstatic int 327256806Sianffec_miibus_writereg(device_t dev, int phy, int reg, int val) 328256806Sian{ 329256806Sian struct ffec_softc *sc; 330256806Sian 331256806Sian sc = device_get_softc(dev); 332256806Sian 333256806Sian WR4(sc, FEC_IER_REG, FEC_IER_MII); 334256806Sian 335256806Sian WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | 336256806Sian FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 337256806Sian ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 338256806Sian ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) | 339256806Sian (val & FEC_MMFR_DATA_MASK)); 340256806Sian 341256806Sian if (!ffec_miibus_iowait(sc)) { 342256806Sian device_printf(dev, "timeout waiting for mii write\n"); 343256806Sian return (-1); 344256806Sian } 345256806Sian 346256806Sian return (0); 347256806Sian} 348256806Sian 349256806Sianstatic void 350256806Sianffec_miibus_statchg(device_t dev) 351256806Sian{ 352256806Sian struct ffec_softc *sc; 353256806Sian struct mii_data *mii; 354256806Sian uint32_t ecr, rcr, tcr; 355256806Sian 356256806Sian /* 357256806Sian * Called by the MII bus driver when the PHY establishes link to set the 358256806Sian * MAC interface registers. 359256806Sian */ 360256806Sian 361256806Sian sc = device_get_softc(dev); 362256806Sian 363256806Sian FFEC_ASSERT_LOCKED(sc); 364256806Sian 365256806Sian mii = sc->mii_softc; 366256806Sian 367256806Sian if (mii->mii_media_status & IFM_ACTIVE) 368256806Sian sc->link_is_up = true; 369256806Sian else 370256806Sian sc->link_is_up = false; 371256806Sian 372256806Sian ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED; 373256806Sian rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE | 374256806Sian FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE); 375256806Sian tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN; 376256806Sian 377256806Sian rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */ 378256806Sian switch (sc->phy_conn_type) { 379256806Sian case PHY_CONN_MII: 380256806Sian break; 381256806Sian case PHY_CONN_RMII: 382256806Sian rcr |= FEC_RCR_RMII_MODE; 383256806Sian break; 384256806Sian case PHY_CONN_RGMII: 385256806Sian rcr |= FEC_RCR_RGMII_EN; 386256806Sian break; 387256806Sian } 388256806Sian 389256806Sian switch (IFM_SUBTYPE(mii->mii_media_active)) { 390256806Sian case IFM_1000_T: 391256806Sian case IFM_1000_SX: 392256806Sian ecr |= FEC_ECR_SPEED; 393256806Sian break; 394256806Sian case IFM_100_TX: 395256806Sian /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */ 396256806Sian break; 397256806Sian case IFM_10_T: 398256806Sian rcr |= FEC_RCR_RMII_10T; 399256806Sian break; 400256806Sian case IFM_NONE: 401256806Sian sc->link_is_up = false; 402256806Sian return; 403256806Sian default: 404256806Sian sc->link_is_up = false; 405256806Sian device_printf(dev, "Unsupported media %u\n", 406256806Sian IFM_SUBTYPE(mii->mii_media_active)); 407256806Sian return; 408256806Sian } 409256806Sian 410256806Sian if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 411256806Sian tcr |= FEC_TCR_FDEN; 412256806Sian else 413256806Sian rcr |= FEC_RCR_DRT; 414256806Sian 415256806Sian if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0) 416256806Sian rcr |= FEC_RCR_FCE; 417256806Sian 418256806Sian WR4(sc, FEC_RCR_REG, rcr); 419256806Sian WR4(sc, FEC_TCR_REG, tcr); 420256806Sian WR4(sc, FEC_ECR_REG, ecr); 421256806Sian} 422256806Sian 423256806Sianstatic void 424256806Sianffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 425256806Sian{ 426256806Sian struct ffec_softc *sc; 427256806Sian struct mii_data *mii; 428256806Sian 429256806Sian 430256806Sian sc = ifp->if_softc; 431256806Sian mii = sc->mii_softc; 432256806Sian FFEC_LOCK(sc); 433256806Sian mii_pollstat(mii); 434256806Sian ifmr->ifm_active = mii->mii_media_active; 435256806Sian ifmr->ifm_status = mii->mii_media_status; 436256806Sian FFEC_UNLOCK(sc); 437256806Sian} 438256806Sian 439256806Sianstatic int 440256806Sianffec_media_change_locked(struct ffec_softc *sc) 441256806Sian{ 442256806Sian 443256806Sian return (mii_mediachg(sc->mii_softc)); 444256806Sian} 445256806Sian 446256806Sianstatic int 447256806Sianffec_media_change(struct ifnet * ifp) 448256806Sian{ 449256806Sian struct ffec_softc *sc; 450256806Sian int error; 451256806Sian 452256806Sian sc = ifp->if_softc; 453256806Sian 454256806Sian FFEC_LOCK(sc); 455256806Sian error = ffec_media_change_locked(sc); 456256806Sian FFEC_UNLOCK(sc); 457256806Sian return (error); 458256806Sian} 459256806Sian 460256806Sianstatic void ffec_clear_stats(struct ffec_softc *sc) 461256806Sian{ 462256806Sian 463256806Sian WR4(sc, FEC_RMON_R_PACKETS, 0); 464256806Sian WR4(sc, FEC_RMON_R_MC_PKT, 0); 465256806Sian WR4(sc, FEC_RMON_R_CRC_ALIGN, 0); 466256806Sian WR4(sc, FEC_RMON_R_UNDERSIZE, 0); 467256806Sian WR4(sc, FEC_RMON_R_OVERSIZE, 0); 468256806Sian WR4(sc, FEC_RMON_R_FRAG, 0); 469256806Sian WR4(sc, FEC_RMON_R_JAB, 0); 470256806Sian WR4(sc, FEC_RMON_T_PACKETS, 0); 471256806Sian WR4(sc, FEC_RMON_T_MC_PKT, 0); 472256806Sian WR4(sc, FEC_RMON_T_CRC_ALIGN, 0); 473256806Sian WR4(sc, FEC_RMON_T_UNDERSIZE, 0); 474256806Sian WR4(sc, FEC_RMON_T_OVERSIZE , 0); 475256806Sian WR4(sc, FEC_RMON_T_FRAG, 0); 476256806Sian WR4(sc, FEC_RMON_T_JAB, 0); 477256806Sian WR4(sc, FEC_RMON_T_COL, 0); 478256806Sian} 479256806Sian 480256806Sianstatic void 481256806Sianffec_harvest_stats(struct ffec_softc *sc) 482256806Sian{ 483256806Sian struct ifnet *ifp; 484256806Sian 485256806Sian /* We don't need to harvest too often. */ 486256806Sian if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) 487256806Sian return; 488256806Sian 489256806Sian /* 490256806Sian * Try to avoid harvesting unless the IDLE flag is on, but if it has 491256806Sian * been too long just go ahead and do it anyway, the worst that'll 492256806Sian * happen is we'll lose a packet count or two as we clear at the end. 493256806Sian */ 494256806Sian if (sc->stats_harvest_count < (2 * STATS_HARVEST_INTERVAL) && 495256806Sian ((RD4(sc, FEC_MIBC_REG) & FEC_MIBC_IDLE) == 0)) 496256806Sian return; 497256806Sian 498256806Sian sc->stats_harvest_count = 0; 499256806Sian ifp = sc->ifp; 500256806Sian 501256806Sian ifp->if_ipackets += RD4(sc, FEC_RMON_R_PACKETS); 502256806Sian ifp->if_imcasts += RD4(sc, FEC_RMON_R_MC_PKT); 503256806Sian ifp->if_ierrors += RD4(sc, FEC_RMON_R_CRC_ALIGN); 504256806Sian ifp->if_ierrors += RD4(sc, FEC_RMON_R_UNDERSIZE); 505256806Sian ifp->if_ierrors += RD4(sc, FEC_RMON_R_OVERSIZE); 506256806Sian ifp->if_ierrors += RD4(sc, FEC_RMON_R_FRAG); 507256806Sian ifp->if_ierrors += RD4(sc, FEC_RMON_R_JAB); 508256806Sian 509256806Sian ifp->if_opackets += RD4(sc, FEC_RMON_T_PACKETS); 510256806Sian ifp->if_omcasts += RD4(sc, FEC_RMON_T_MC_PKT); 511256806Sian ifp->if_oerrors += RD4(sc, FEC_RMON_T_CRC_ALIGN); 512256806Sian ifp->if_oerrors += RD4(sc, FEC_RMON_T_UNDERSIZE); 513256806Sian ifp->if_oerrors += RD4(sc, FEC_RMON_T_OVERSIZE ); 514256806Sian ifp->if_oerrors += RD4(sc, FEC_RMON_T_FRAG); 515256806Sian ifp->if_oerrors += RD4(sc, FEC_RMON_T_JAB); 516256806Sian 517256806Sian ifp->if_collisions += RD4(sc, FEC_RMON_T_COL); 518256806Sian 519256806Sian ffec_clear_stats(sc); 520256806Sian} 521256806Sian 522256806Sianstatic void 523256806Sianffec_tick(void *arg) 524256806Sian{ 525256806Sian struct ffec_softc *sc; 526256806Sian struct ifnet *ifp; 527256806Sian int link_was_up; 528256806Sian 529256806Sian sc = arg; 530256806Sian 531256806Sian FFEC_ASSERT_LOCKED(sc); 532256806Sian 533256806Sian ifp = sc->ifp; 534256806Sian 535256806Sian if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 536256806Sian return; 537256806Sian 538256806Sian /* 539256806Sian * Typical tx watchdog. If this fires it indicates that we enqueued 540256806Sian * packets for output and never got a txdone interrupt for them. Maybe 541256806Sian * it's a missed interrupt somehow, just pretend we got one. 542256806Sian */ 543256806Sian if (sc->tx_watchdog_count > 0) { 544256806Sian if (--sc->tx_watchdog_count == 0) { 545256806Sian ffec_txfinish_locked(sc); 546256806Sian } 547256806Sian } 548256806Sian 549256806Sian /* Gather stats from hardware counters. */ 550256806Sian ffec_harvest_stats(sc); 551256806Sian 552256806Sian /* Check the media status. */ 553256806Sian link_was_up = sc->link_is_up; 554256806Sian mii_tick(sc->mii_softc); 555256806Sian if (sc->link_is_up && !link_was_up) 556256806Sian ffec_txstart_locked(sc); 557256806Sian 558256806Sian /* Schedule another check one second from now. */ 559256806Sian callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 560256806Sian} 561256806Sian 562256806Sianinline static uint32_t 563256806Sianffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr, 564256806Sian uint32_t len) 565256806Sian{ 566256806Sian uint32_t nidx; 567256806Sian uint32_t flags; 568256806Sian 569256806Sian nidx = next_txidx(sc, idx); 570256806Sian 571256806Sian /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 572256806Sian if (paddr == 0 || len == 0) { 573256806Sian flags = 0; 574256806Sian --sc->txcount; 575256806Sian } else { 576256806Sian flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC; 577256806Sian ++sc->txcount; 578256806Sian } 579256806Sian if (nidx == 0) 580256806Sian flags |= FEC_TXDESC_WRAP; 581256806Sian 582256806Sian /* 583256806Sian * The hardware requires 32-bit physical addresses. We set up the dma 584256806Sian * tag to indicate that, so the cast to uint32_t should never lose 585256806Sian * significant bits. 586256806Sian */ 587256806Sian sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr; 588256806Sian sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */ 589256806Sian 590256806Sian return (nidx); 591256806Sian} 592256806Sian 593256806Sianstatic int 594256806Sianffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp) 595256806Sian{ 596256806Sian struct mbuf * m; 597256806Sian int error, nsegs; 598256806Sian struct bus_dma_segment seg; 599256806Sian 600256806Sian if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 601256806Sian return (ENOMEM); 602256806Sian *mp = m; 603256806Sian 604256806Sian error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 605256806Sian m, &seg, &nsegs, 0); 606256806Sian if (error != 0) { 607256806Sian return (ENOMEM); 608256806Sian } 609256806Sian bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 610256806Sian BUS_DMASYNC_PREWRITE); 611256806Sian 612256806Sian sc->txbuf_map[idx].mbuf = m; 613256806Sian ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 614256806Sian 615256806Sian return (0); 616256806Sian 617256806Sian} 618256806Sian 619256806Sianstatic void 620256806Sianffec_txstart_locked(struct ffec_softc *sc) 621256806Sian{ 622256806Sian struct ifnet *ifp; 623256806Sian struct mbuf *m; 624256806Sian int enqueued; 625256806Sian 626256806Sian FFEC_ASSERT_LOCKED(sc); 627256806Sian 628256806Sian if (!sc->link_is_up) 629256806Sian return; 630256806Sian 631256806Sian ifp = sc->ifp; 632256806Sian 633256806Sian if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 634256806Sian return; 635256806Sian 636256806Sian enqueued = 0; 637256806Sian 638256806Sian for (;;) { 639256806Sian if (sc->txcount == (TX_DESC_COUNT-1)) { 640256806Sian ifp->if_drv_flags |= IFF_DRV_OACTIVE; 641256806Sian break; 642256806Sian } 643256806Sian IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 644256806Sian if (m == NULL) 645256806Sian break; 646256806Sian if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 647256806Sian IFQ_DRV_PREPEND(&ifp->if_snd, m); 648256806Sian break; 649256806Sian } 650256806Sian BPF_MTAP(ifp, m); 651256806Sian sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 652256806Sian ++enqueued; 653256806Sian } 654256806Sian 655256806Sian if (enqueued != 0) { 656276285Sian bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE); 657256806Sian WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR); 658276285Sian bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE); 659256806Sian sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 660256806Sian } 661256806Sian} 662256806Sian 663256806Sianstatic void 664256806Sianffec_txstart(struct ifnet *ifp) 665256806Sian{ 666256806Sian struct ffec_softc *sc = ifp->if_softc; 667256806Sian 668256806Sian FFEC_LOCK(sc); 669256806Sian ffec_txstart_locked(sc); 670256806Sian FFEC_UNLOCK(sc); 671256806Sian} 672256806Sian 673256806Sianstatic void 674256806Sianffec_txfinish_locked(struct ffec_softc *sc) 675256806Sian{ 676256806Sian struct ifnet *ifp; 677256806Sian struct ffec_hwdesc *desc; 678256806Sian struct ffec_bufmap *bmap; 679256806Sian boolean_t retired_buffer; 680256806Sian 681256806Sian FFEC_ASSERT_LOCKED(sc); 682256806Sian 683276285Sian /* XXX Can't set PRE|POST right now, but we need both. */ 684276285Sian bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD); 685276285Sian bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD); 686256806Sian ifp = sc->ifp; 687256806Sian retired_buffer = false; 688256806Sian while (sc->tx_idx_tail != sc->tx_idx_head) { 689256806Sian desc = &sc->txdesc_ring[sc->tx_idx_tail]; 690256806Sian if (desc->flags_len & FEC_TXDESC_READY) 691256806Sian break; 692256806Sian retired_buffer = true; 693256806Sian bmap = &sc->txbuf_map[sc->tx_idx_tail]; 694256806Sian bus_dmamap_sync(sc->txbuf_tag, bmap->map, 695256806Sian BUS_DMASYNC_POSTWRITE); 696256806Sian bus_dmamap_unload(sc->txbuf_tag, bmap->map); 697256806Sian m_freem(bmap->mbuf); 698256806Sian bmap->mbuf = NULL; 699256806Sian ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 700256806Sian sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 701256806Sian } 702256806Sian 703256806Sian /* 704256806Sian * If we retired any buffers, there will be open tx slots available in 705256806Sian * the descriptor ring, go try to start some new output. 706256806Sian */ 707256806Sian if (retired_buffer) { 708256806Sian ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 709256806Sian ffec_txstart_locked(sc); 710256806Sian } 711256806Sian 712256806Sian /* If there are no buffers outstanding, muzzle the watchdog. */ 713256806Sian if (sc->tx_idx_tail == sc->tx_idx_head) { 714256806Sian sc->tx_watchdog_count = 0; 715256806Sian } 716256806Sian} 717256806Sian 718256806Sianinline static uint32_t 719256806Sianffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr) 720256806Sian{ 721256806Sian uint32_t nidx; 722256806Sian 723256806Sian /* 724256806Sian * The hardware requires 32-bit physical addresses. We set up the dma 725256806Sian * tag to indicate that, so the cast to uint32_t should never lose 726256806Sian * significant bits. 727256806Sian */ 728256806Sian nidx = next_rxidx(sc, idx); 729256806Sian sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr; 730256806Sian sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY | 731256806Sian ((nidx == 0) ? FEC_RXDESC_WRAP : 0); 732256806Sian 733256806Sian return (nidx); 734256806Sian} 735256806Sian 736256806Sianstatic int 737256806Sianffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m) 738256806Sian{ 739256806Sian int error, nsegs; 740256806Sian struct bus_dma_segment seg; 741256806Sian 742256806Sian /* 743256806Sian * We need to leave at least ETHER_ALIGN bytes free at the beginning of 744256806Sian * the buffer to allow the data to be re-aligned after receiving it (by 745256806Sian * copying it backwards ETHER_ALIGN bytes in the same buffer). We also 746256806Sian * have to ensure that the beginning of the buffer is aligned to the 747256806Sian * hardware's requirements. 748256806Sian */ 749256806Sian m_adj(m, roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN)); 750256806Sian 751256806Sian error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 752256806Sian m, &seg, &nsegs, 0); 753256806Sian if (error != 0) { 754256806Sian return (error); 755256806Sian } 756256806Sian 757256806Sian bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 758256806Sian BUS_DMASYNC_PREREAD); 759256806Sian 760256806Sian sc->rxbuf_map[idx].mbuf = m; 761256806Sian ffec_setup_rxdesc(sc, idx, seg.ds_addr); 762256806Sian 763256806Sian return (0); 764256806Sian} 765256806Sian 766256806Sianstatic struct mbuf * 767256806Sianffec_alloc_mbufcl(struct ffec_softc *sc) 768256806Sian{ 769256806Sian struct mbuf *m; 770256806Sian 771256806Sian m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 772256806Sian m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 773256806Sian 774256806Sian return (m); 775256806Sian} 776256806Sian 777256806Sianstatic void 778256806Sianffec_rxfinish_onebuf(struct ffec_softc *sc, int len) 779256806Sian{ 780256806Sian struct mbuf *m, *newmbuf; 781256806Sian struct ffec_bufmap *bmap; 782256806Sian uint8_t *dst, *src; 783256806Sian int error; 784256806Sian 785256806Sian /* 786256806Sian * First try to get a new mbuf to plug into this slot in the rx ring. 787256806Sian * If that fails, drop the current packet and recycle the current 788256806Sian * mbuf, which is still mapped and loaded. 789256806Sian */ 790256806Sian if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) { 791256806Sian ++sc->ifp->if_iqdrops; 792256806Sian ffec_setup_rxdesc(sc, sc->rx_idx, 793256806Sian sc->rxdesc_ring[sc->rx_idx].buf_paddr); 794256806Sian return; 795256806Sian } 796256806Sian 797256806Sian /* 798256806Sian * Unfortunately, the protocol headers need to be aligned on a 32-bit 799256806Sian * boundary for the upper layers. The hardware requires receive 800256806Sian * buffers to be 16-byte aligned. The ethernet header is 14 bytes, 801256806Sian * leaving the protocol header unaligned. We used m_adj() after 802256806Sian * allocating the buffer to leave empty space at the start of the 803256806Sian * buffer, now we'll use the alignment agnostic bcopy() routine to 804256806Sian * shuffle all the data backwards 2 bytes and adjust m_data. 805256806Sian * 806256806Sian * XXX imx6 hardware is able to do this 2-byte alignment by setting the 807256806Sian * SHIFT16 bit in the RACC register. Older hardware doesn't have that 808256806Sian * feature, but for them could we speed this up by copying just the 809256806Sian * protocol headers into their own small mbuf then chaining the cluster 810256806Sian * to it? That way we'd only need to copy like 64 bytes or whatever 811256806Sian * the biggest header is, instead of the whole 1530ish-byte frame. 812256806Sian */ 813256806Sian 814256806Sian FFEC_UNLOCK(sc); 815256806Sian 816256806Sian bmap = &sc->rxbuf_map[sc->rx_idx]; 817256806Sian len -= ETHER_CRC_LEN; 818256806Sian bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD); 819256806Sian bus_dmamap_unload(sc->rxbuf_tag, bmap->map); 820256806Sian m = bmap->mbuf; 821256806Sian bmap->mbuf = NULL; 822256806Sian m->m_len = len; 823256806Sian m->m_pkthdr.len = len; 824256806Sian m->m_pkthdr.rcvif = sc->ifp; 825256806Sian 826256806Sian src = mtod(m, uint8_t*); 827256806Sian dst = src - ETHER_ALIGN; 828256806Sian bcopy(src, dst, len); 829256806Sian m->m_data = dst; 830256806Sian sc->ifp->if_input(sc->ifp, m); 831256806Sian 832256806Sian FFEC_LOCK(sc); 833256806Sian 834256806Sian if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) { 835256806Sian device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error); 836256806Sian /* XXX Now what? We've got a hole in the rx ring. */ 837256806Sian } 838256806Sian 839256806Sian} 840256806Sian 841256806Sianstatic void 842256806Sianffec_rxfinish_locked(struct ffec_softc *sc) 843256806Sian{ 844256806Sian struct ffec_hwdesc *desc; 845256806Sian int len; 846256806Sian boolean_t produced_empty_buffer; 847256806Sian 848256806Sian FFEC_ASSERT_LOCKED(sc); 849256806Sian 850276285Sian /* XXX Can't set PRE|POST right now, but we need both. */ 851276285Sian bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREREAD); 852276285Sian bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTREAD); 853256806Sian produced_empty_buffer = false; 854256806Sian for (;;) { 855256806Sian desc = &sc->rxdesc_ring[sc->rx_idx]; 856256806Sian if (desc->flags_len & FEC_RXDESC_EMPTY) 857256806Sian break; 858256806Sian produced_empty_buffer = true; 859256806Sian len = (desc->flags_len & FEC_RXDESC_LEN_MASK); 860256806Sian if (len < 64) { 861256806Sian /* 862256806Sian * Just recycle the descriptor and continue. . 863256806Sian */ 864256806Sian ffec_setup_rxdesc(sc, sc->rx_idx, 865256806Sian sc->rxdesc_ring[sc->rx_idx].buf_paddr); 866256806Sian } else if ((desc->flags_len & FEC_RXDESC_L) == 0) { 867256806Sian /* 868256806Sian * The entire frame is not in this buffer. Impossible. 869256806Sian * Recycle the descriptor and continue. 870256806Sian * 871256806Sian * XXX what's the right way to handle this? Probably we 872256806Sian * should stop/init the hardware because this should 873256806Sian * just really never happen when we have buffers bigger 874256806Sian * than the maximum frame size. 875256806Sian */ 876256806Sian device_printf(sc->dev, 877256806Sian "fec_rxfinish: received frame without LAST bit set"); 878256806Sian ffec_setup_rxdesc(sc, sc->rx_idx, 879256806Sian sc->rxdesc_ring[sc->rx_idx].buf_paddr); 880256806Sian } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) { 881256806Sian /* 882256806Sian * Something went wrong with receiving the frame, we 883256806Sian * don't care what (the hardware has counted the error 884256806Sian * in the stats registers already), we just reuse the 885256806Sian * same mbuf, which is still dma-mapped, by resetting 886256806Sian * the rx descriptor. 887256806Sian */ 888256806Sian ffec_setup_rxdesc(sc, sc->rx_idx, 889256806Sian sc->rxdesc_ring[sc->rx_idx].buf_paddr); 890256806Sian } else { 891256806Sian /* 892256806Sian * Normal case: a good frame all in one buffer. 893256806Sian */ 894256806Sian ffec_rxfinish_onebuf(sc, len); 895256806Sian } 896256806Sian sc->rx_idx = next_rxidx(sc, sc->rx_idx); 897256806Sian } 898256806Sian 899256806Sian if (produced_empty_buffer) { 900276285Sian bus_dmamap_sync(sc->rxdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE); 901256806Sian WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 902276285Sian bus_dmamap_sync(sc->rxdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE); 903256806Sian } 904256806Sian} 905256806Sian 906256806Sianstatic void 907256806Sianffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr) 908256806Sian{ 909256806Sian uint32_t palr, paur, rnd; 910256806Sian 911256806Sian /* 912256806Sian * Try to recover a MAC address from the running hardware. If there's 913256806Sian * something non-zero there, assume the bootloader did the right thing 914256806Sian * and just use it. 915256806Sian * 916256806Sian * Otherwise, set the address to a convenient locally assigned address, 917256806Sian * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 918256806Sian * assigned bit set, and the broadcast/multicast bit clear. 919256806Sian */ 920256806Sian palr = RD4(sc, FEC_PALR_REG); 921259317Sian paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK; 922256806Sian if ((palr | paur) != 0) { 923256806Sian hwaddr[0] = palr >> 24; 924256806Sian hwaddr[1] = palr >> 16; 925256806Sian hwaddr[2] = palr >> 8; 926256806Sian hwaddr[3] = palr >> 0; 927256806Sian hwaddr[4] = paur >> 24; 928256806Sian hwaddr[5] = paur >> 16; 929256806Sian } else { 930256806Sian rnd = arc4random() & 0x00ffffff; 931256806Sian hwaddr[0] = 'b'; 932256806Sian hwaddr[1] = 's'; 933256806Sian hwaddr[2] = 'd'; 934256806Sian hwaddr[3] = rnd >> 16; 935256806Sian hwaddr[4] = rnd >> 8; 936256806Sian hwaddr[5] = rnd >> 0; 937256806Sian } 938256806Sian 939256806Sian if (bootverbose) { 940256806Sian device_printf(sc->dev, 941256806Sian "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n", 942256806Sian hwaddr[0], hwaddr[1], hwaddr[2], 943256806Sian hwaddr[3], hwaddr[4], hwaddr[5]); 944256806Sian } 945256806Sian} 946256806Sian 947256806Sianstatic void 948256806Sianffec_setup_rxfilter(struct ffec_softc *sc) 949256806Sian{ 950256806Sian struct ifnet *ifp; 951256806Sian struct ifmultiaddr *ifma; 952256806Sian uint8_t *eaddr; 953256806Sian uint32_t crc; 954256806Sian uint64_t ghash, ihash; 955256806Sian 956256806Sian FFEC_ASSERT_LOCKED(sc); 957256806Sian 958256806Sian ifp = sc->ifp; 959256806Sian 960256806Sian /* 961256806Sian * Set the multicast (group) filter hash. 962256806Sian */ 963256806Sian if ((ifp->if_flags & IFF_ALLMULTI)) 964256806Sian ghash = 0xffffffffffffffffLLU; 965256806Sian else { 966256806Sian ghash = 0; 967256806Sian if_maddr_rlock(ifp); 968256806Sian TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 969256806Sian if (ifma->ifma_addr->sa_family != AF_LINK) 970256806Sian continue; 971266277Sian /* 6 bits from MSB in LE CRC32 are used for hash. */ 972266277Sian crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 973256806Sian ifma->ifma_addr), ETHER_ADDR_LEN); 974266277Sian ghash |= 1LLU << (((uint8_t *)&crc)[3] >> 2); 975256806Sian } 976256806Sian if_maddr_runlock(ifp); 977256806Sian } 978256806Sian WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32)); 979256806Sian WR4(sc, FEC_GALR_REG, (uint32_t)ghash); 980256806Sian 981256806Sian /* 982256806Sian * Set the individual address filter hash. 983256806Sian * 984256806Sian * XXX Is 0 the right value when promiscuous is off? This hw feature 985256806Sian * seems to support the concept of MAC address aliases, does such a 986256806Sian * thing even exist? 987256806Sian */ 988256806Sian if ((ifp->if_flags & IFF_PROMISC)) 989256806Sian ihash = 0xffffffffffffffffLLU; 990256806Sian else { 991256806Sian ihash = 0; 992256806Sian } 993256806Sian WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32)); 994256806Sian WR4(sc, FEC_IALR_REG, (uint32_t)ihash); 995256806Sian 996256806Sian /* 997256806Sian * Set the primary address. 998256806Sian */ 999256806Sian eaddr = IF_LLADDR(ifp); 1000256806Sian WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) | 1001256806Sian (eaddr[2] << 8) | eaddr[3]); 1002256806Sian WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16)); 1003256806Sian} 1004256806Sian 1005256806Sianstatic void 1006256806Sianffec_stop_locked(struct ffec_softc *sc) 1007256806Sian{ 1008256806Sian struct ifnet *ifp; 1009256806Sian struct ffec_hwdesc *desc; 1010256806Sian struct ffec_bufmap *bmap; 1011256806Sian int idx; 1012256806Sian 1013256806Sian FFEC_ASSERT_LOCKED(sc); 1014256806Sian 1015256806Sian ifp = sc->ifp; 1016256806Sian ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1017256806Sian sc->tx_watchdog_count = 0; 1018256806Sian sc->stats_harvest_count = 0; 1019256806Sian 1020256806Sian /* 1021256806Sian * Stop the hardware, mask all interrupts, and clear all current 1022256806Sian * interrupt status bits. 1023256806Sian */ 1024256806Sian WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN); 1025256806Sian WR4(sc, FEC_IEM_REG, 0x00000000); 1026256806Sian WR4(sc, FEC_IER_REG, 0xffffffff); 1027256806Sian 1028256806Sian /* 1029256806Sian * Stop the media-check callout. Do not use callout_drain() because 1030256806Sian * we're holding a mutex the callout acquires, and if it's currently 1031256806Sian * waiting to acquire it, we'd deadlock. If it is waiting now, the 1032256806Sian * ffec_tick() routine will return without doing anything when it sees 1033256806Sian * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe. 1034256806Sian */ 1035256806Sian callout_stop(&sc->ffec_callout); 1036256806Sian 1037256806Sian /* 1038256806Sian * Discard all untransmitted buffers. Each buffer is simply freed; 1039256806Sian * it's as if the bits were transmitted and then lost on the wire. 1040256806Sian * 1041256806Sian * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them 1042256806Sian * back on the queue for when we get restarted later? 1043256806Sian */ 1044256806Sian idx = sc->tx_idx_tail; 1045256806Sian while (idx != sc->tx_idx_head) { 1046256806Sian desc = &sc->txdesc_ring[idx]; 1047256806Sian bmap = &sc->txbuf_map[idx]; 1048256806Sian if (desc->buf_paddr != 0) { 1049256806Sian bus_dmamap_unload(sc->txbuf_tag, bmap->map); 1050256806Sian m_freem(bmap->mbuf); 1051256806Sian bmap->mbuf = NULL; 1052256806Sian ffec_setup_txdesc(sc, idx, 0, 0); 1053256806Sian } 1054256806Sian idx = next_txidx(sc, idx); 1055256806Sian } 1056256806Sian 1057256806Sian /* 1058256806Sian * Discard all unprocessed receive buffers. This amounts to just 1059256806Sian * pretending that nothing ever got received into them. We reuse the 1060256806Sian * mbuf already mapped for each desc, simply turning the EMPTY flags 1061256806Sian * back on so they'll get reused when we start up again. 1062256806Sian */ 1063256806Sian for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1064256806Sian desc = &sc->rxdesc_ring[idx]; 1065256806Sian ffec_setup_rxdesc(sc, idx, desc->buf_paddr); 1066256806Sian } 1067256806Sian} 1068256806Sian 1069256806Sianstatic void 1070256806Sianffec_init_locked(struct ffec_softc *sc) 1071256806Sian{ 1072256806Sian struct ifnet *ifp = sc->ifp; 1073256806Sian uint32_t maxbuf, maxfl, regval; 1074256806Sian 1075256806Sian FFEC_ASSERT_LOCKED(sc); 1076256806Sian 1077256806Sian /* 1078256806Sian * The hardware has a limit of 0x7ff as the max frame length (see 1079256806Sian * comments for MRBR below), and we use mbuf clusters as receive 1080256806Sian * buffers, and we currently are designed to receive an entire frame 1081256806Sian * into a single buffer. 1082256806Sian * 1083256806Sian * We start with a MCLBYTES-sized cluster, but we have to offset into 1084256806Sian * the buffer by ETHER_ALIGN to make room for post-receive re-alignment, 1085256806Sian * and then that value has to be rounded up to the hardware's DMA 1086256806Sian * alignment requirements, so all in all our buffer is that much smaller 1087256806Sian * than MCLBYTES. 1088256806Sian * 1089256806Sian * The resulting value is used as the frame truncation length and the 1090256806Sian * max buffer receive buffer size for now. It'll become more complex 1091256806Sian * when we support jumbo frames and receiving fragments of them into 1092256806Sian * separate buffers. 1093256806Sian */ 1094256806Sian maxbuf = MCLBYTES - roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN); 1095256806Sian maxfl = min(maxbuf, 0x7ff); 1096256806Sian 1097256806Sian if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1098256806Sian return; 1099256806Sian 1100256806Sian /* Mask all interrupts and clear all current interrupt status bits. */ 1101256806Sian WR4(sc, FEC_IEM_REG, 0x00000000); 1102256806Sian WR4(sc, FEC_IER_REG, 0xffffffff); 1103256806Sian 1104256806Sian /* 1105256806Sian * Go set up palr/puar, galr/gaur, ialr/iaur. 1106256806Sian */ 1107256806Sian ffec_setup_rxfilter(sc); 1108256806Sian 1109256806Sian /* 1110256806Sian * TFWR - Transmit FIFO watermark register. 1111256806Sian * 1112256806Sian * Set the transmit fifo watermark register to "store and forward" mode 1113256806Sian * and also set a threshold of 128 bytes in the fifo before transmission 1114256806Sian * of a frame begins (to avoid dma underruns). Recent FEC hardware 1115256806Sian * supports STRFWD and when that bit is set, the watermark level in the 1116256806Sian * low bits is ignored. Older hardware doesn't have STRFWD, but writing 1117256806Sian * to that bit is innocuous, and the TWFR bits get used instead. 1118256806Sian */ 1119256806Sian WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE); 1120256806Sian 1121256806Sian /* RCR - Receive control register. 1122256806Sian * 1123256806Sian * Set max frame length + clean out anything left from u-boot. 1124256806Sian */ 1125256806Sian WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT)); 1126256806Sian 1127256806Sian /* 1128256806Sian * TCR - Transmit control register. 1129256806Sian * 1130256806Sian * Clean out anything left from u-boot. Any necessary values are set in 1131256806Sian * ffec_miibus_statchg() based on the media type. 1132256806Sian */ 1133256806Sian WR4(sc, FEC_TCR_REG, 0); 1134256806Sian 1135256806Sian /* 1136256806Sian * OPD - Opcode/pause duration. 1137256806Sian * 1138256806Sian * XXX These magic numbers come from u-boot. 1139256806Sian */ 1140256806Sian WR4(sc, FEC_OPD_REG, 0x00010020); 1141256806Sian 1142256806Sian /* 1143256806Sian * FRSR - Fifo receive start register. 1144256806Sian * 1145256806Sian * This register does not exist on imx6, it is present on earlier 1146256806Sian * hardware. The u-boot code sets this to a non-default value that's 32 1147256806Sian * bytes larger than the default, with no clue as to why. The default 1148256806Sian * value should work fine, so there's no code to init it here. 1149256806Sian */ 1150256806Sian 1151256806Sian /* 1152256806Sian * MRBR - Max RX buffer size. 1153256806Sian * 1154256806Sian * Note: For hardware prior to imx6 this value cannot exceed 0x07ff, 1155256806Sian * but the datasheet says no such thing for imx6. On the imx6, setting 1156256806Sian * this to 2K without setting EN1588 resulted in a crazy runaway 1157256806Sian * receive loop in the hardware, where every rx descriptor in the ring 1158256806Sian * had its EMPTY flag cleared, no completion or error flags set, and a 1159256806Sian * length of zero. I think maybe you can only exceed it when EN1588 is 1160256806Sian * set, like maybe that's what enables jumbo frames, because in general 1161256806Sian * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy- 1162256806Sian * compatible" flag. 1163256806Sian */ 1164256806Sian WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT); 1165256806Sian 1166256806Sian /* 1167256806Sian * FTRL - Frame truncation length. 1168256806Sian * 1169256806Sian * Must be greater than or equal to the value set in FEC_RCR_MAXFL. 1170256806Sian */ 1171256806Sian WR4(sc, FEC_FTRL_REG, maxfl); 1172256806Sian 1173256806Sian /* 1174256806Sian * RDSR / TDSR descriptor ring pointers. 1175256806Sian * 1176256806Sian * When we turn on ECR_ETHEREN at the end, the hardware zeroes its 1177256806Sian * internal current descriptor index values for both rings, so we zero 1178256806Sian * our index values as well. 1179256806Sian */ 1180256806Sian sc->rx_idx = 0; 1181256806Sian sc->tx_idx_head = sc->tx_idx_tail = 0; 1182256806Sian sc->txcount = 0; 1183256806Sian WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr); 1184256806Sian WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr); 1185256806Sian 1186256806Sian /* 1187256806Sian * EIM - interrupt mask register. 1188256806Sian * 1189256806Sian * We always enable the same set of interrupts while running; unlike 1190256806Sian * some drivers there's no need to change the mask on the fly depending 1191256806Sian * on what operations are in progress. 1192256806Sian */ 1193256806Sian WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR); 1194256806Sian 1195256806Sian /* 1196256806Sian * MIBC - MIB control (hardware stats). 1197256806Sian */ 1198256806Sian regval = RD4(sc, FEC_MIBC_REG); 1199256806Sian WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS); 1200256806Sian ffec_clear_stats(sc); 1201256806Sian WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS); 1202256806Sian 1203256806Sian /* 1204256806Sian * ECR - Ethernet control register. 1205256806Sian * 1206256806Sian * This must happen after all the other config registers are set. If 1207256806Sian * we're running on little-endian hardware, also set the flag for byte- 1208256806Sian * swapping descriptor ring entries. This flag doesn't exist on older 1209256806Sian * hardware, but it can be safely set -- the bit position it occupies 1210256806Sian * was unused. 1211256806Sian */ 1212256806Sian regval = RD4(sc, FEC_ECR_REG); 1213256806Sian#if _BYTE_ORDER == _LITTLE_ENDIAN 1214256806Sian regval |= FEC_ECR_DBSWP; 1215256806Sian#endif 1216256806Sian regval |= FEC_ECR_ETHEREN; 1217256806Sian WR4(sc, FEC_ECR_REG, regval); 1218256806Sian 1219256806Sian ifp->if_drv_flags |= IFF_DRV_RUNNING; 1220256806Sian 1221256806Sian /* 1222256806Sian * Call mii_mediachg() which will call back into ffec_miibus_statchg() to 1223256806Sian * set up the remaining config registers based on the current media. 1224256806Sian */ 1225256806Sian mii_mediachg(sc->mii_softc); 1226256806Sian callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 1227256806Sian 1228256806Sian /* 1229256806Sian * Tell the hardware that receive buffers are available. They were made 1230256806Sian * available in ffec_attach() or ffec_stop(). 1231256806Sian */ 1232256806Sian WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 1233256806Sian} 1234256806Sian 1235256806Sianstatic void 1236256806Sianffec_init(void *if_softc) 1237256806Sian{ 1238256806Sian struct ffec_softc *sc = if_softc; 1239256806Sian 1240256806Sian FFEC_LOCK(sc); 1241256806Sian ffec_init_locked(sc); 1242256806Sian FFEC_UNLOCK(sc); 1243256806Sian} 1244256806Sian 1245256806Sianstatic void 1246256806Sianffec_intr(void *arg) 1247256806Sian{ 1248256806Sian struct ffec_softc *sc; 1249256806Sian uint32_t ier; 1250256806Sian 1251256806Sian sc = arg; 1252256806Sian 1253256806Sian FFEC_LOCK(sc); 1254256806Sian 1255256806Sian ier = RD4(sc, FEC_IER_REG); 1256256806Sian 1257256806Sian if (ier & FEC_IER_TXF) { 1258256806Sian WR4(sc, FEC_IER_REG, FEC_IER_TXF); 1259256806Sian ffec_txfinish_locked(sc); 1260256806Sian } 1261256806Sian 1262256806Sian if (ier & FEC_IER_RXF) { 1263256806Sian WR4(sc, FEC_IER_REG, FEC_IER_RXF); 1264256806Sian ffec_rxfinish_locked(sc); 1265256806Sian } 1266256806Sian 1267256806Sian /* 1268256806Sian * We actually don't care about most errors, because the hardware copes 1269256806Sian * with them just fine, discarding the incoming bad frame, or forcing a 1270256806Sian * bad CRC onto an outgoing bad frame, and counting the errors in the 1271256806Sian * stats registers. The one that really matters is EBERR (DMA bus 1272256806Sian * error) because the hardware automatically clears ECR[ETHEREN] and we 1273256806Sian * have to restart it here. It should never happen. 1274256806Sian */ 1275256806Sian if (ier & FEC_IER_EBERR) { 1276256806Sian WR4(sc, FEC_IER_REG, FEC_IER_EBERR); 1277256806Sian device_printf(sc->dev, 1278256806Sian "Ethernet DMA error, restarting controller.\n"); 1279256806Sian ffec_stop_locked(sc); 1280256806Sian ffec_init_locked(sc); 1281256806Sian } 1282256806Sian 1283256806Sian FFEC_UNLOCK(sc); 1284256806Sian 1285256806Sian} 1286256806Sian 1287256806Sianstatic int 1288256806Sianffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1289256806Sian{ 1290256806Sian struct ffec_softc *sc; 1291256806Sian struct mii_data *mii; 1292256806Sian struct ifreq *ifr; 1293256806Sian int mask, error; 1294256806Sian 1295256806Sian sc = ifp->if_softc; 1296256806Sian ifr = (struct ifreq *)data; 1297256806Sian 1298256806Sian error = 0; 1299256806Sian switch (cmd) { 1300256806Sian case SIOCSIFFLAGS: 1301256806Sian FFEC_LOCK(sc); 1302256806Sian if (ifp->if_flags & IFF_UP) { 1303256806Sian if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1304256806Sian if ((ifp->if_flags ^ sc->if_flags) & 1305256806Sian (IFF_PROMISC | IFF_ALLMULTI)) 1306256806Sian ffec_setup_rxfilter(sc); 1307256806Sian } else { 1308256806Sian if (!sc->is_detaching) 1309256806Sian ffec_init_locked(sc); 1310256806Sian } 1311256806Sian } else { 1312256806Sian if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1313256806Sian ffec_stop_locked(sc); 1314256806Sian } 1315256806Sian sc->if_flags = ifp->if_flags; 1316256806Sian FFEC_UNLOCK(sc); 1317256806Sian break; 1318256806Sian 1319256806Sian case SIOCADDMULTI: 1320256806Sian case SIOCDELMULTI: 1321256806Sian if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1322256806Sian FFEC_LOCK(sc); 1323256806Sian ffec_setup_rxfilter(sc); 1324256806Sian FFEC_UNLOCK(sc); 1325256806Sian } 1326256806Sian break; 1327256806Sian 1328256806Sian case SIOCSIFMEDIA: 1329256806Sian case SIOCGIFMEDIA: 1330256806Sian mii = sc->mii_softc; 1331256806Sian error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1332256806Sian break; 1333256806Sian 1334256806Sian case SIOCSIFCAP: 1335256806Sian mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1336256806Sian if (mask & IFCAP_VLAN_MTU) { 1337256806Sian /* No work to do except acknowledge the change took. */ 1338256806Sian ifp->if_capenable ^= IFCAP_VLAN_MTU; 1339256806Sian } 1340256806Sian break; 1341256806Sian 1342256806Sian default: 1343256806Sian error = ether_ioctl(ifp, cmd, data); 1344256806Sian break; 1345256806Sian } 1346256806Sian 1347256806Sian return (error); 1348256806Sian} 1349256806Sian 1350256806Sianstatic int 1351256806Sianffec_detach(device_t dev) 1352256806Sian{ 1353256806Sian struct ffec_softc *sc; 1354256806Sian bus_dmamap_t map; 1355256806Sian int idx; 1356256806Sian 1357256806Sian /* 1358256806Sian * NB: This function can be called internally to unwind a failure to 1359256806Sian * attach. Make sure a resource got allocated/created before destroying. 1360256806Sian */ 1361256806Sian 1362256806Sian sc = device_get_softc(dev); 1363256806Sian 1364256806Sian if (sc->is_attached) { 1365256806Sian FFEC_LOCK(sc); 1366256806Sian sc->is_detaching = true; 1367256806Sian ffec_stop_locked(sc); 1368256806Sian FFEC_UNLOCK(sc); 1369256806Sian callout_drain(&sc->ffec_callout); 1370256806Sian ether_ifdetach(sc->ifp); 1371256806Sian } 1372256806Sian 1373256806Sian /* XXX no miibus detach? */ 1374256806Sian 1375256806Sian /* Clean up RX DMA resources and free mbufs. */ 1376256806Sian for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1377256806Sian if ((map = sc->rxbuf_map[idx].map) != NULL) { 1378256806Sian bus_dmamap_unload(sc->rxbuf_tag, map); 1379256806Sian bus_dmamap_destroy(sc->rxbuf_tag, map); 1380256806Sian m_freem(sc->rxbuf_map[idx].mbuf); 1381256806Sian } 1382256806Sian } 1383256806Sian if (sc->rxbuf_tag != NULL) 1384256806Sian bus_dma_tag_destroy(sc->rxbuf_tag); 1385256806Sian if (sc->rxdesc_map != NULL) { 1386256806Sian bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map); 1387256806Sian bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map); 1388256806Sian } 1389256806Sian if (sc->rxdesc_tag != NULL) 1390256806Sian bus_dma_tag_destroy(sc->rxdesc_tag); 1391256806Sian 1392256806Sian /* Clean up TX DMA resources. */ 1393256806Sian for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1394256806Sian if ((map = sc->txbuf_map[idx].map) != NULL) { 1395256806Sian /* TX maps are already unloaded. */ 1396256806Sian bus_dmamap_destroy(sc->txbuf_tag, map); 1397256806Sian } 1398256806Sian } 1399256806Sian if (sc->txbuf_tag != NULL) 1400256806Sian bus_dma_tag_destroy(sc->txbuf_tag); 1401256806Sian if (sc->txdesc_map != NULL) { 1402256806Sian bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map); 1403256806Sian bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map); 1404256806Sian } 1405256806Sian if (sc->txdesc_tag != NULL) 1406256806Sian bus_dma_tag_destroy(sc->txdesc_tag); 1407256806Sian 1408256806Sian /* Release bus resources. */ 1409256806Sian if (sc->intr_cookie) 1410256806Sian bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 1411256806Sian 1412256806Sian if (sc->irq_res != NULL) 1413256806Sian bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 1414256806Sian 1415256806Sian if (sc->mem_res != NULL) 1416256806Sian bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 1417256806Sian 1418256806Sian FFEC_LOCK_DESTROY(sc); 1419256806Sian return (0); 1420256806Sian} 1421256806Sian 1422256806Sianstatic int 1423256806Sianffec_attach(device_t dev) 1424256806Sian{ 1425256806Sian struct ffec_softc *sc; 1426256806Sian struct ifnet *ifp = NULL; 1427256806Sian struct mbuf *m; 1428256806Sian phandle_t ofw_node; 1429256806Sian int error, rid; 1430256806Sian uint8_t eaddr[ETHER_ADDR_LEN]; 1431256806Sian char phy_conn_name[32]; 1432256806Sian uint32_t idx, mscr; 1433256806Sian 1434256806Sian sc = device_get_softc(dev); 1435256806Sian sc->dev = dev; 1436256806Sian 1437256806Sian FFEC_LOCK_INIT(sc); 1438256806Sian 1439256806Sian /* 1440256806Sian * There are differences in the implementation and features of the FEC 1441256806Sian * hardware on different SoCs, so figure out what type we are. 1442256806Sian */ 1443259317Sian sc->fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1444256806Sian 1445256806Sian /* 1446256806Sian * We have to be told what kind of electrical connection exists between 1447256806Sian * the MAC and PHY or we can't operate correctly. 1448256806Sian */ 1449256806Sian if ((ofw_node = ofw_bus_get_node(dev)) == -1) { 1450256806Sian device_printf(dev, "Impossible: Can't find ofw bus node\n"); 1451256806Sian error = ENXIO; 1452256806Sian goto out; 1453256806Sian } 1454256806Sian if (OF_searchprop(ofw_node, "phy-mode", 1455256806Sian phy_conn_name, sizeof(phy_conn_name)) != -1) { 1456256806Sian if (strcasecmp(phy_conn_name, "mii") == 0) 1457256806Sian sc->phy_conn_type = PHY_CONN_MII; 1458256806Sian else if (strcasecmp(phy_conn_name, "rmii") == 0) 1459256806Sian sc->phy_conn_type = PHY_CONN_RMII; 1460256806Sian else if (strcasecmp(phy_conn_name, "rgmii") == 0) 1461256806Sian sc->phy_conn_type = PHY_CONN_RGMII; 1462256806Sian } 1463256806Sian if (sc->phy_conn_type == PHY_CONN_UNKNOWN) { 1464256806Sian device_printf(sc->dev, "No valid 'phy-mode' " 1465256806Sian "property found in FDT data for device.\n"); 1466256806Sian error = ENOATTR; 1467256806Sian goto out; 1468256806Sian } 1469256806Sian 1470256806Sian callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0); 1471256806Sian 1472256806Sian /* Allocate bus resources for accessing the hardware. */ 1473256806Sian rid = 0; 1474256806Sian sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1475256806Sian RF_ACTIVE); 1476256806Sian if (sc->mem_res == NULL) { 1477256806Sian device_printf(dev, "could not allocate memory resources.\n"); 1478256806Sian error = ENOMEM; 1479256806Sian goto out; 1480256806Sian } 1481256806Sian rid = 0; 1482256806Sian sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1483256806Sian RF_ACTIVE); 1484256806Sian if (sc->irq_res == NULL) { 1485256806Sian device_printf(dev, "could not allocate interrupt resources.\n"); 1486256806Sian error = ENOMEM; 1487256806Sian goto out; 1488256806Sian } 1489256806Sian 1490256806Sian /* 1491256806Sian * Set up TX descriptor ring, descriptors, and dma maps. 1492256806Sian */ 1493256806Sian error = bus_dma_tag_create( 1494256806Sian bus_get_dma_tag(dev), /* Parent tag. */ 1495256806Sian FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1496256806Sian BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1497256806Sian BUS_SPACE_MAXADDR, /* highaddr */ 1498256806Sian NULL, NULL, /* filter, filterarg */ 1499256806Sian TX_DESC_SIZE, 1, /* maxsize, nsegments */ 1500256806Sian TX_DESC_SIZE, /* maxsegsize */ 1501256806Sian 0, /* flags */ 1502256806Sian NULL, NULL, /* lockfunc, lockarg */ 1503256806Sian &sc->txdesc_tag); 1504256806Sian if (error != 0) { 1505256806Sian device_printf(sc->dev, 1506256806Sian "could not create TX ring DMA tag.\n"); 1507256806Sian goto out; 1508256806Sian } 1509256806Sian 1510256806Sian error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 1511256806Sian BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map); 1512256806Sian if (error != 0) { 1513256806Sian device_printf(sc->dev, 1514256806Sian "could not allocate TX descriptor ring.\n"); 1515256806Sian goto out; 1516256806Sian } 1517256806Sian 1518256806Sian error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring, 1519256806Sian TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0); 1520256806Sian if (error != 0) { 1521256806Sian device_printf(sc->dev, 1522256806Sian "could not load TX descriptor ring map.\n"); 1523256806Sian goto out; 1524256806Sian } 1525256806Sian 1526256806Sian error = bus_dma_tag_create( 1527256806Sian bus_get_dma_tag(dev), /* Parent tag. */ 1528256806Sian FEC_TXBUF_ALIGN, 0, /* alignment, boundary */ 1529256806Sian BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1530256806Sian BUS_SPACE_MAXADDR, /* highaddr */ 1531256806Sian NULL, NULL, /* filter, filterarg */ 1532256806Sian MCLBYTES, 1, /* maxsize, nsegments */ 1533256806Sian MCLBYTES, /* maxsegsize */ 1534256806Sian 0, /* flags */ 1535256806Sian NULL, NULL, /* lockfunc, lockarg */ 1536256806Sian &sc->txbuf_tag); 1537256806Sian if (error != 0) { 1538256806Sian device_printf(sc->dev, 1539256806Sian "could not create TX ring DMA tag.\n"); 1540256806Sian goto out; 1541256806Sian } 1542256806Sian 1543256806Sian for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1544256806Sian error = bus_dmamap_create(sc->txbuf_tag, 0, 1545256806Sian &sc->txbuf_map[idx].map); 1546256806Sian if (error != 0) { 1547256806Sian device_printf(sc->dev, 1548256806Sian "could not create TX buffer DMA map.\n"); 1549256806Sian goto out; 1550256806Sian } 1551256806Sian ffec_setup_txdesc(sc, idx, 0, 0); 1552256806Sian } 1553256806Sian 1554256806Sian /* 1555256806Sian * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 1556256806Sian */ 1557256806Sian error = bus_dma_tag_create( 1558256806Sian bus_get_dma_tag(dev), /* Parent tag. */ 1559256806Sian FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1560256806Sian BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1561256806Sian BUS_SPACE_MAXADDR, /* highaddr */ 1562256806Sian NULL, NULL, /* filter, filterarg */ 1563256806Sian RX_DESC_SIZE, 1, /* maxsize, nsegments */ 1564256806Sian RX_DESC_SIZE, /* maxsegsize */ 1565256806Sian 0, /* flags */ 1566256806Sian NULL, NULL, /* lockfunc, lockarg */ 1567256806Sian &sc->rxdesc_tag); 1568256806Sian if (error != 0) { 1569256806Sian device_printf(sc->dev, 1570256806Sian "could not create RX ring DMA tag.\n"); 1571256806Sian goto out; 1572256806Sian } 1573256806Sian 1574256806Sian error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 1575256806Sian BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map); 1576256806Sian if (error != 0) { 1577256806Sian device_printf(sc->dev, 1578256806Sian "could not allocate RX descriptor ring.\n"); 1579256806Sian goto out; 1580256806Sian } 1581256806Sian 1582256806Sian error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring, 1583256806Sian RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0); 1584256806Sian if (error != 0) { 1585256806Sian device_printf(sc->dev, 1586256806Sian "could not load RX descriptor ring map.\n"); 1587256806Sian goto out; 1588256806Sian } 1589256806Sian 1590256806Sian error = bus_dma_tag_create( 1591256806Sian bus_get_dma_tag(dev), /* Parent tag. */ 1592256806Sian 1, 0, /* alignment, boundary */ 1593256806Sian BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1594256806Sian BUS_SPACE_MAXADDR, /* highaddr */ 1595256806Sian NULL, NULL, /* filter, filterarg */ 1596256806Sian MCLBYTES, 1, /* maxsize, nsegments */ 1597256806Sian MCLBYTES, /* maxsegsize */ 1598256806Sian 0, /* flags */ 1599256806Sian NULL, NULL, /* lockfunc, lockarg */ 1600256806Sian &sc->rxbuf_tag); 1601256806Sian if (error != 0) { 1602256806Sian device_printf(sc->dev, 1603256806Sian "could not create RX buf DMA tag.\n"); 1604256806Sian goto out; 1605256806Sian } 1606256806Sian 1607256806Sian for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1608256806Sian error = bus_dmamap_create(sc->rxbuf_tag, 0, 1609256806Sian &sc->rxbuf_map[idx].map); 1610256806Sian if (error != 0) { 1611256806Sian device_printf(sc->dev, 1612256806Sian "could not create RX buffer DMA map.\n"); 1613256806Sian goto out; 1614256806Sian } 1615256806Sian if ((m = ffec_alloc_mbufcl(sc)) == NULL) { 1616256806Sian device_printf(dev, "Could not alloc mbuf\n"); 1617256806Sian error = ENOMEM; 1618256806Sian goto out; 1619256806Sian } 1620256806Sian if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) { 1621256806Sian device_printf(sc->dev, 1622256806Sian "could not create new RX buffer.\n"); 1623256806Sian goto out; 1624256806Sian } 1625256806Sian } 1626256806Sian 1627256806Sian /* Try to get the MAC address from the hardware before resetting it. */ 1628256806Sian ffec_get_hwaddr(sc, eaddr); 1629256806Sian 1630256806Sian /* Reset the hardware. Disables all interrupts. */ 1631256806Sian WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); 1632256806Sian 1633256806Sian /* Setup interrupt handler. */ 1634256806Sian error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 1635256806Sian NULL, ffec_intr, sc, &sc->intr_cookie); 1636256806Sian if (error != 0) { 1637256806Sian device_printf(dev, "could not setup interrupt handler.\n"); 1638256806Sian goto out; 1639256806Sian } 1640256806Sian 1641256806Sian /* 1642256806Sian * Set up the PHY control register. 1643256806Sian * 1644256806Sian * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2). 1645256806Sian * Speed formula for FEC is md_clock = mac_clock / (N * 2) 1646256806Sian * 1647256806Sian * XXX - Revisit this... 1648256806Sian * 1649256806Sian * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot 1650256806Sian * code uses 10. Both values seem to work, but I suspect many modern 1651256806Sian * PHY parts can do mdio at speeds far above the standard 2.5 MHz. 1652256806Sian * 1653256806Sian * Different imx manuals use confusingly different terminology (things 1654256806Sian * like "system clock" and "internal module clock") with examples that 1655256806Sian * use frequencies that have nothing to do with ethernet, giving the 1656256806Sian * vague impression that maybe the clock in question is the periphclock 1657256806Sian * or something. In fact, on an imx53 development board (FEC), 1658256806Sian * measuring the mdio clock at the pin on the PHY and playing with 1659256806Sian * various divisors showed that the root speed was 66 MHz (clk_ipg_root 1660256806Sian * aka periphclock) and 13 was the right divisor. 1661256806Sian * 1662256806Sian * All in all, it seems likely that 13 is a safe divisor for now, 1663256806Sian * because if we really do need to base it on the peripheral clock 1664256806Sian * speed, then we need a platform-independant get-clock-freq API. 1665256806Sian */ 1666256806Sian mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT; 1667256806Sian if (OF_hasprop(ofw_node, "phy-disable-preamble")) { 1668256806Sian mscr |= FEC_MSCR_DIS_PRE; 1669256806Sian if (bootverbose) 1670256806Sian device_printf(dev, "PHY preamble disabled\n"); 1671256806Sian } 1672256806Sian WR4(sc, FEC_MSCR_REG, mscr); 1673256806Sian 1674256806Sian /* Set up the ethernet interface. */ 1675256806Sian sc->ifp = ifp = if_alloc(IFT_ETHER); 1676256806Sian 1677256806Sian ifp->if_softc = sc; 1678256806Sian if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1679256806Sian ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1680256806Sian ifp->if_capabilities = IFCAP_VLAN_MTU; 1681256806Sian ifp->if_capenable = ifp->if_capabilities; 1682256806Sian ifp->if_start = ffec_txstart; 1683256806Sian ifp->if_ioctl = ffec_ioctl; 1684256806Sian ifp->if_init = ffec_init; 1685256806Sian IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1686256806Sian ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1687256806Sian IFQ_SET_READY(&ifp->if_snd); 1688256806Sian ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1689256806Sian 1690256806Sian#if 0 /* XXX The hardware keeps stats we could use for these. */ 1691256806Sian ifp->if_linkmib = &sc->mibdata; 1692256806Sian ifp->if_linkmiblen = sizeof(sc->mibdata); 1693256806Sian#endif 1694256806Sian 1695256806Sian /* Set up the miigasket hardware (if any). */ 1696256806Sian ffec_miigasket_setup(sc); 1697256806Sian 1698256806Sian /* Attach the mii driver. */ 1699256806Sian error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change, 1700256806Sian ffec_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 1701256806Sian if (error != 0) { 1702256806Sian device_printf(dev, "PHY attach failed\n"); 1703256806Sian goto out; 1704256806Sian } 1705256806Sian sc->mii_softc = device_get_softc(sc->miibus); 1706256806Sian 1707256806Sian /* All ready to run, attach the ethernet interface. */ 1708256806Sian ether_ifattach(ifp, eaddr); 1709256806Sian sc->is_attached = true; 1710256806Sian 1711256806Sian error = 0; 1712256806Sianout: 1713256806Sian 1714256806Sian if (error != 0) 1715256806Sian ffec_detach(dev); 1716256806Sian 1717256806Sian return (error); 1718256806Sian} 1719256806Sian 1720256806Sianstatic int 1721256806Sianffec_probe(device_t dev) 1722256806Sian{ 1723259317Sian uintptr_t fectype; 1724256806Sian 1725266152Sian if (!ofw_bus_status_okay(dev)) 1726266152Sian return (ENXIO); 1727266152Sian 1728259317Sian fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1729259317Sian if (fectype == FECTYPE_NONE) 1730256806Sian return (ENXIO); 1731259317Sian 1732259317Sian device_set_desc(dev, (fectype & FECFLAG_GBE) ? 1733259317Sian "Freescale Gigabit Ethernet Controller" : 1734259317Sian "Freescale Fast Ethernet Controller"); 1735259317Sian 1736256806Sian return (BUS_PROBE_DEFAULT); 1737256806Sian} 1738256806Sian 1739256806Sian 1740256806Sianstatic device_method_t ffec_methods[] = { 1741256806Sian /* Device interface. */ 1742256806Sian DEVMETHOD(device_probe, ffec_probe), 1743256806Sian DEVMETHOD(device_attach, ffec_attach), 1744256806Sian DEVMETHOD(device_detach, ffec_detach), 1745256806Sian 1746256806Sian/* 1747256806Sian DEVMETHOD(device_shutdown, ffec_shutdown), 1748256806Sian DEVMETHOD(device_suspend, ffec_suspend), 1749256806Sian DEVMETHOD(device_resume, ffec_resume), 1750256806Sian*/ 1751256806Sian 1752256806Sian /* MII interface. */ 1753256806Sian DEVMETHOD(miibus_readreg, ffec_miibus_readreg), 1754256806Sian DEVMETHOD(miibus_writereg, ffec_miibus_writereg), 1755256806Sian DEVMETHOD(miibus_statchg, ffec_miibus_statchg), 1756256806Sian 1757256806Sian DEVMETHOD_END 1758256806Sian}; 1759256806Sian 1760256806Sianstatic driver_t ffec_driver = { 1761256806Sian "ffec", 1762256806Sian ffec_methods, 1763256806Sian sizeof(struct ffec_softc) 1764256806Sian}; 1765256806Sian 1766256806Sianstatic devclass_t ffec_devclass; 1767256806Sian 1768256806SianDRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0); 1769256806SianDRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0); 1770256806Sian 1771256806SianMODULE_DEPEND(ffec, ether, 1, 1, 1); 1772256806SianMODULE_DEPEND(ffec, miibus, 1, 1, 1); 1773