/freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/ |
H A D | CalcSpillWeights.h | 51 LiveIntervals &LIS; member in class:llvm::VirtRegAuxInfo 62 : MF(mf), LIS(lis), Loops(loops), MBFI(mbfi), normalize(norm) {} 70 void calculateSpillWeightsAndHints(LiveIntervals &LIS, MachineFunction &MF,
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H A D | ScheduleDAGInstrs.h | 83 LiveIntervals *LIS; member in class:llvm::ScheduleDAGInstrs 153 LiveIntervals *LIS = 0); 158 LiveIntervals *getLIS() const { return LIS; }
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H A D | LiveRegMatrix.h | 43 LiveIntervals *LIS; member in class:llvm::LiveRegMatrix
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H A D | LiveRangeEdit.h | 63 LiveIntervals &LIS; member in class:llvm::LiveRangeEdit 121 MRI(MF.getRegInfo()), LIS(lis), VRM(vrm), 210 /// to erase it from LIS.
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H A D | RegisterPressure.h | 255 const LiveIntervals *LIS; 264 /// or RegisterPressure. If requireIntervals is false, LIS are ignored. 288 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(true), 292 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(false),
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/freebsd-10-stable/contrib/llvm/lib/CodeGen/ |
H A D | CalcSpillWeights.cpp | 25 void llvm::calculateSpillWeightsAndHints(LiveIntervals &LIS, argument 34 VirtRegAuxInfo VRAI(MF, LIS, MLI, MBFI, norm); 39 VRAI.calculateSpillWeightAndHint(LIS.getInterval(Reg)); 76 const LiveIntervals &LIS, 86 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); 89 if (!TII.isTriviallyReMaterializable(MI, LIS.getAliasAnalysis())) 138 if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb)) 174 if (li.isZeroLength(LIS.getSlotIndexes())) { 183 if (isRematerializable(li, LIS, *MF.getTarget().getInstrInfo())) 75 isRematerializable(const LiveInterval &LI, const LiveIntervals &LIS, const TargetInstrInfo &TII) argument
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H A D | RegAllocBase.h | 65 LiveIntervals *LIS; member in class:llvm::RegAllocBase 69 RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0), Matrix(0) {}
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H A D | PHIElimination.cpp | 52 LiveIntervals *LIS; member in class:__anon2299::PHIElimination 129 LIS = getAnalysisIfAvailable<LiveIntervals>(); 138 if (!DisableEdgeSplitting && (LV || LIS)) { 157 if (LIS) 158 LIS->RemoveMachineInstrFromMaps(DefMI); 166 if (LIS) 167 LIS->RemoveMachineInstrFromMaps(I->first); 308 if (LIS) { 310 SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(NewInstr); 312 SlotIndex MBBStartIndex = LIS [all...] |
H A D | LiveDebugVariables.cpp | 130 LiveIntervals &LIS, const TargetInstrInfo &TII); 135 LiveIntervals &LIS); 226 /// @param LIS Live intervals analysis. 231 LiveIntervals &LIS, MachineDominatorTree &MDT, 245 LiveIntervals &LIS); 250 LiveIntervals &LIS, MachineDominatorTree &MDT, 256 LiveIntervals &LIS); 264 LiveIntervals &LIS, const TargetInstrInfo &TRI); 284 LiveIntervals *LIS; member in class:__anon2270::LDVImpl 482 LIS 497 extendDef(SlotIndex Idx, unsigned LocNo, LiveRange *LR, const VNInfo *VNI, SmallVectorImpl<SlotIndex> *Kills, LiveIntervals &LIS, MachineDominatorTree &MDT, UserValueScopes &UVS) argument 559 addDefsFromCopies(LiveInterval *LI, unsigned LocNo, const SmallVectorImpl<SlotIndex> &Kills, SmallVectorImpl<std::pair<SlotIndex, unsigned> > &NewDefs, MachineRegisterInfo &MRI, LiveIntervals &LIS) argument 632 computeIntervals(MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, LiveIntervals &LIS, MachineDominatorTree &MDT, UserValueScopes &UVS) argument 735 splitLocation(unsigned OldLocNo, ArrayRef<unsigned> NewRegs, LiveIntervals& LIS) argument 834 splitRegister(unsigned OldReg, ArrayRef<unsigned> NewRegs, LiveIntervals &LIS) argument 864 splitRegister(unsigned OldReg, ArrayRef<unsigned> NewRegs, LiveIntervals &LIS) argument 900 findInsertLocation(MachineBasicBlock *MBB, SlotIndex Idx, LiveIntervals &LIS) argument 926 insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx, unsigned LocNo, LiveIntervals &LIS, const TargetInstrInfo &TII) argument 942 emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS, const TargetInstrInfo &TII) argument [all...] |
H A D | LiveRangeEdit.cpp | 38 LiveInterval &LI = LIS.createEmptyInterval(VReg); 67 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def); 100 LiveInterval &li = LIS.getInterval(MO.getReg()); 129 DefIdx = LIS.getInstructionIndex(RM.OrigMI); 132 RM.OrigMI = LIS.getInstructionFromIndex(DefIdx); 156 return LIS.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late) 162 LIS.removeInterval(Reg); 195 LIS.getInstructionIndex(DefMI), 196 LIS.getInstructionIndex(UseMI))) 216 LIS [all...] |
H A D | RegAllocBase.cpp | 62 LIS = &lis; 77 enqueue(&LIS->getInterval(Reg)); 93 LIS->removeInterval(VirtReg->reg); 133 LiveInterval *SplitVirtReg = &LIS->getInterval(*I); 137 LIS->removeInterval(SplitVirtReg->reg);
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H A D | InlineSpiller.cpp | 59 LiveIntervals &LIS; member in class:__anon2266::InlineSpiller 144 LIS(pass.getAnalysis<LiveIntervals>()), 235 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI)) 285 LiveInterval &SnipLI = LIS.getInterval(SnipReg); 371 SV.SpillMBB = LIS.getMBBFromIndex(SV.SpillVNI->def); 389 DepSV.SpillMBB = LIS.getMBBFromIndex(DepSV.SpillVNI->def); 528 LiveInterval &LI = LIS.getInterval(Reg); 529 LiveInterval &OrigLI = LIS.getInterval(Original); 574 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); 580 LiveInterval &SrcLI = LIS 1009 dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B, MachineBasicBlock::iterator E, LiveIntervals const &LIS, const char *const header, unsigned VReg =0) argument 1180 DEBUG(dumpMachineInstrRangeWithSlotIndex(llvm::next(MI), MIS.end(), LIS, local [all...] |
H A D | RegisterCoalescer.cpp | 84 LiveIntervals *LIS; member in class:__anon2311::RegisterCoalescer 402 LiveRangeEdit(0, NewRegs, *MF, *LIS, 0, this).eliminateDeadDefs(DeadDefs); 432 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg()); 434 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg()); 435 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(); 457 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def); 471 LIS->getInstructionFromIndex(ValS->end.getPrevSlot()); 510 LIS->shrinkToUses(&IntA); 524 if (LIS->hasPHIKill(IntA, AValNo)) 573 SlotIndex CopyIdx = LIS 1289 LiveIntervals *LIS; member in class:__anon2312::JoinVals 2067 isLocalCopy(MachineInstr *Copy, const LiveIntervals *LIS) argument [all...] |
H A D | LiveDebugVariables.h | 52 LiveIntervals &LIS);
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H A D | TwoAddressInstructionPass.cpp | 76 LiveIntervals *LIS; member in class:__anon2346::TwoAddressInstructionPass 172 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS); 215 if (LIS) { 216 LiveInterval &LI = LIS->getInterval(SavedReg); 220 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot(); 226 KillMI = LIS->getInstructionFromIndex(I->end); 276 if (MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))) { 289 if (!LIS) { 303 if (LIS) 360 isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS) argument 402 isKilled(MachineInstr &MI, unsigned Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives) argument [all...] |
H A D | SplitKit.cpp | 47 LIS(lis), 65 SlotIndex MBBEnd = LIS.getMBBEndIdx(MBB); 74 LSP.first = LIS.getInstructionIndex(FirstTerm); 85 LSP.second = LIS.getInstructionIndex(I); 93 if (!LPad || !LSP.second || !LIS.isLiveInToMBB(*CurLI, LPad)) 116 if (LSP == LIS.getMBBEndIdx(MBB)) 118 return LIS.getInstructionFromIndex(LSP); 138 UseSlots.push_back(LIS.getInstructionIndex(&*I).getRegSlot()); 155 const_cast<LiveIntervals&>(LIS) 186 MachineFunction::iterator MFI = LIS [all...] |
H A D | InterferenceCache.h | 57 /// LIS - Used for accessing register mask interference maps. 58 LiveIntervals *LIS; member in class:llvm::InterferenceCache::Entry 96 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0), LIS(0) {} 103 LIS = lis;
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H A D | LiveRegMatrix.cpp | 52 LIS = &getAnalysis<LiveIntervals>(); 108 LIS->checkRegMaskInterference(VirtReg, RegMaskUsable); 123 const LiveRange &UnitRange = LIS->getRegUnit(*Units); 124 if (VirtReg.overlaps(UnitRange, CP, *LIS->getSlotIndexes()))
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H A D | VirtRegMap.cpp | 161 LiveIntervals *LIS; member in class:__anon2349::VirtRegRewriter 209 LIS = &getAnalysis<LiveIntervals>(); 217 LIS->addKillFlags(VRM); 243 LiveInterval &LI = LIS->getInterval(VirtReg); 244 if (LI.empty() || LIS->intervalIsInOneMBB(LI))
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H A D | RegAllocGreedy.cpp | 361 Matrix->unassign(LIS->getInterval(VirtReg)); 374 LiveInterval &LI = LIS->getInterval(VirtReg); 418 LIS->intervalIsInOneMBB(*LI)) { 445 LiveInterval *LI = &LIS->getInterval(~Queue.top().second); 564 bool IsLocal = LIS->intervalIsInOneMBB(VirtReg); 624 if (!MaxCost.isMax() && IsLocal && LIS->intervalIsInOneMBB(*Intf) && 1128 DebugVars->splitRegister(Reg, LREdit.regs(), *LIS); 1139 LiveInterval &Reg = LIS->getInterval(LREdit.get(i)); 1264 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this); 1312 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VR [all...] |
H A D | RegAllocBasic.cpp | 204 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM); 263 LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM); 281 calculateSpillWeightsAndHints(*LIS, *MF,
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H A D | RegisterPressure.cpp | 152 return &LIS->getInterval(Reg); 153 return LIS->getCachedRegUnit(Reg); 158 LIS = 0; 195 LIS = lis; 231 return LIS->getMBBEndIdx(MBB); 232 return LIS->getInstructionIndex(IdxPos).getRegSlot(); 481 SlotIdx = LIS->getInstructionIndex(CurrPos).getRegSlot(); 719 SlotIndex SlotIdx = LIS->getInstructionIndex(MI); 878 const LiveIntervals *LIS) { 885 SlotIndex InstSlot = LIS 875 findUseBetween(unsigned Reg, SlotIndex PriorUseIdx, SlotIndex NextUseIdx, const MachineRegisterInfo *MRI, const LiveIntervals *LIS) argument [all...] |
H A D | LiveIntervalAnalysis.cpp | 709 LiveIntervals& LIS; member in class:LiveIntervals::HMEditor 718 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI, argument 721 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx), 730 return &LIS.getRegUnit(Unit); 731 return LIS.getCachedRegUnit(Unit); 753 LiveInterval &LI = LIS.getInterval(Reg); 827 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end)) 961 std::lower_bound(LIS.RegMaskSlots.begin(), LIS [all...] |
H A D | InterferenceCache.cpp | 90 RegUnits.back().Fixed = &LIS->getRegUnit(*Units); 163 RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum); 164 RegMaskBits = LIS->getRegMaskBitsInBlock(MBBNum);
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H A D | MachineScheduler.cpp | 84 MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) { 254 LIS = &getAnalysis<LiveIntervals>(); 258 DEBUG(LIS->dump()); 341 DEBUG(LIS->dump()); 468 LIS->handleMove(MI, /*UpdateFlags=*/true); 511 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin); 512 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd); 610 const LiveInterval &LI = LIS->getInterval(Reg); 615 VNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB)); 617 LiveQueryResult LRQ = LI.Query(LIS 1181 LiveIntervals *LIS = DAG->getLIS(); local [all...] |