/freebsd-10-stable/contrib/llvm/lib/CodeGen/ |
H A D | ScoreboardHazardRecognizer.cpp | 35 ScheduleHazardRecognizer(), ItinData(II), DAG(SchedDAG), IssueWidth(0), 46 if (ItinData && !ItinData->isEmpty()) { 48 if (ItinData->isEndMarker(idx)) 51 const InstrStage *IS = ItinData->beginStage(idx); 52 const InstrStage *E = ItinData->endStage(idx); 80 IssueWidth = ItinData->SchedModel->IssueWidth; 119 if (!ItinData || ItinData->isEmpty()) 134 for (const InstrStage *IS = ItinData [all...] |
H A D | TargetInstrInfo.cpp | 616 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, argument 619 if (!ItinData || ItinData->isEmpty()) 627 return ItinData->getOperandCycle(DefClass, DefIdx); 629 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 632 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, argument 634 if (!ItinData || ItinData->isEmpty()) 640 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); 648 TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, argument 680 getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost) const argument 691 hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const argument 705 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 715 computeDefOperandLatency( const InstrItineraryData *ItinData, const MachineInstr *DefMI) const argument 742 computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument [all...] |
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.h | 35 ARMHazardRecognizer(const InstrItineraryData *ItinData, argument 37 : ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"),
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H A D | ARMBaseInstrInfo.h | 218 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 222 int getOperandLatency(const InstrItineraryData *ItinData, 226 int getOperandLatency(const InstrItineraryData *ItinData, 245 int getVLDMDefCycle(const InstrItineraryData *ItinData, 249 int getLDMDefCycle(const InstrItineraryData *ItinData, 253 int getVSTMUseCycle(const InstrItineraryData *ItinData, 257 int getSTMUseCycle(const InstrItineraryData *ItinData, 261 int getOperandLatency(const InstrItineraryData *ItinData, 269 unsigned getInstrLatency(const InstrItineraryData *ItinData, 273 int getInstrLatency(const InstrItineraryData *ItinData, [all...] |
H A D | ARMBaseInstrInfo.cpp | 2578 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, argument 2583 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); 2833 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, argument 2835 if (!ItinData || ItinData->isEmpty()) 2840 int ItinUOps = ItinData->getNumMicroOps(Class); 2843 return getNumMicroOpsSwiftLdSt(ItinData, MI); 2977 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, argument 2984 return ItinData->getOperandCycle(DefClass, DefIdx); 3018 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, argument 3053 getVSTMUseCycle(const InstrItineraryData *ItinData, const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const argument 3093 getSTMUseCycle(const InstrItineraryData *ItinData, const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const argument 3122 getOperandLatency(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const argument 3470 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 3561 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const argument 3794 getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost) const argument 3844 getInstrLatency(const InstrItineraryData *ItinData, SDNode *Node) const argument 3863 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 3885 hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const argument [all...] |
/freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/ |
H A D | ScoreboardHazardRecognizer.h | 93 const InstrItineraryData *ItinData; member in class:llvm::ScoreboardHazardRecognizer 107 ScoreboardHazardRecognizer(const InstrItineraryData *ItinData,
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/freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.h | 29 PPCScoreboardHazardRecognizer(const InstrItineraryData *ItinData, argument 31 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_) {}
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/freebsd-10-stable/contrib/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 801 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 812 virtual int getOperandLatency(const InstrItineraryData *ItinData, 824 virtual int getOperandLatency(const InstrItineraryData *ItinData, 831 unsigned computeOperandLatency(const InstrItineraryData *ItinData, 839 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, 845 virtual int getInstrLatency(const InstrItineraryData *ItinData, 852 int computeDefOperandLatency(const InstrItineraryData *ItinData, 865 bool hasHighOperandLatency(const InstrItineraryData *ItinData, argument 875 bool hasLowDefLatency(const InstrItineraryData *ItinData,
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/freebsd-10-stable/contrib/llvm/utils/TableGen/ |
H A D | DFAPacketizerEmitter.cpp | 51 Record *ItinData, 354 Record *ItinData, 377 ItinData->getValueAsListOfDefs("Stages"); 439 Record *ItinData = ItinDataList[j]; local 441 collectAllInsnClasses(Name, ItinData, NStages, OS); 353 collectAllInsnClasses(const std::string &Name, Record *ItinData, unsigned &NStages, raw_ostream &OS) argument
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H A D | SubtargetEmitter.cpp | 69 Record *ItinData, std::string &ItinString, 71 void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString, 74 Record *ItinData, 293 Record *ItinData, 298 ItinData->getValueAsListOfDefs("Stages"); 337 void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData, argument 341 ItinData->getValueAsListOfInts("OperandCycles"); 355 Record *ItinData, 359 ItinData->getValueAsListOfDefs("Bypasses"); 462 Record *ItinData local 292 FormItineraryStageString(const std::string &Name, Record *ItinData, std::string &ItinString, unsigned &NStages) argument 354 FormItineraryBypassString(const std::string &Name, Record *ItinData, std::string &ItinString, unsigned NOperandCycles) argument [all...] |
H A D | CodeGenSchedule.cpp | 801 Record *ItinData = ItinRecords[i]; 802 Record *ItinDef = ItinData->getValueAsDef("TheClass"); 808 ProcModel.ItinDefList[SCI->Index] = ItinData;
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/freebsd-10-stable/contrib/llvm/lib/Target/R600/ |
H A D | R600InstrInfo.h | 193 unsigned int getInstrLatency(const InstrItineraryData *ItinData, 197 virtual int getInstrLatency(const InstrItineraryData *ItinData, argument
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H A D | R600InstrInfo.cpp | 1059 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
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/freebsd-10-stable/contrib/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 387 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
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H A D | X86InstrInfo.cpp | 5304 hasHighOperandLatency(const InstrItineraryData *ItinData, argument
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