Lines Matching refs:ItinData
616 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
619 if (!ItinData || ItinData->isEmpty())
627 return ItinData->getOperandCycle(DefClass, DefIdx);
629 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
632 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
634 if (!ItinData || ItinData->isEmpty())
640 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
648 TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
650 if (!ItinData || ItinData->isEmpty())
654 int UOps = ItinData->Itineraries[Class].NumMicroOps;
680 getInstrLatency(const InstrItineraryData *ItinData,
685 if (!ItinData)
688 return ItinData->getStageLatency(MI->getDesc().getSchedClass());
691 bool TargetInstrInfo::hasLowDefLatency(const InstrItineraryData *ItinData,
694 if (!ItinData || ItinData->isEmpty())
698 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
705 getOperandLatency(const InstrItineraryData *ItinData,
710 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
716 const InstrItineraryData *ItinData,
720 if (!ItinData)
721 return getInstrLatency(ItinData, DefMI);
723 if(ItinData->isEmpty())
724 return defaultDefLatency(ItinData->SchedModel, DefMI);
742 computeOperandLatency(const InstrItineraryData *ItinData,
746 int DefLatency = computeDefOperandLatency(ItinData, DefMI);
750 assert(ItinData && !ItinData->isEmpty() && "computeDefOperandLatency fail");
754 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
757 OperLatency = ItinData->getOperandCycle(DefClass, DefIdx);
763 unsigned InstrLatency = getInstrLatency(ItinData, DefMI);
767 defaultDefLatency(ItinData->SchedModel, DefMI));