Lines Matching refs:ItinData
2578 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2583 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2833 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2835 if (!ItinData || ItinData->isEmpty())
2840 int ItinUOps = ItinData->getNumMicroOps(Class);
2843 return getNumMicroOpsSwiftLdSt(ItinData, MI);
2977 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2984 return ItinData->getOperandCycle(DefClass, DefIdx);
3018 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3025 return ItinData->getOperandCycle(DefClass, DefIdx);
3053 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3059 return ItinData->getOperandCycle(UseClass, UseIdx);
3093 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3099 return ItinData->getOperandCycle(UseClass, UseIdx);
3122 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3131 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3140 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3149 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3170 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3181 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3190 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3208 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3221 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3224 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3470 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3475 if (!ItinData || ItinData->isEmpty())
3517 unsigned Latency = getInstrLatency(ItinData, DefMI);
3542 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3561 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3572 if (!ItinData || ItinData->isEmpty())
3576 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3590 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3794 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3809 Latency += getInstrLatency(ItinData, I, PredCost);
3822 if (!ItinData)
3828 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3829 return getNumMicroOps(ItinData, MI);
3832 unsigned Latency = ItinData->getStageLatency(Class);
3844 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3849 if (!ItinData || ItinData->isEmpty())
3855 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3863 hasHighOperandLatency(const InstrItineraryData *ItinData,
3875 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
3877 Latency = getInstrLatency(ItinData, DefMI);
3885 hasLowDefLatency(const InstrItineraryData *ItinData,
3887 if (!ItinData || ItinData->isEmpty())
3893 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);