/freebsd-10-stable/contrib/llvm/lib/CodeGen/ |
H A D | RegisterCoalescer.h | 31 /// DstReg - The register that will be left after coalescing. It can be a 33 unsigned DstReg; member in class:llvm::CoalescerPair 38 /// DstIdx - The sub-register index of the old DstReg in the new coalesced 52 /// Flipped - True when DstReg and SrcReg are reversed from the original 56 /// NewRC - The register class of the coalesced register, or NULL if DstReg 58 /// SrcReg and DstReg. 63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), 70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), 77 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossible 78 /// because DstReg i [all...] |
H A D | OptimizePHIs.cpp | 87 unsigned DstReg = MI->getOperand(0).getReg(); local 100 if (SrcReg == DstReg) 130 unsigned DstReg = MI->getOperand(0).getReg(); local 131 assert(TargetRegisterInfo::isVirtualRegister(DstReg) && 142 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DstReg),
|
H A D | TwoAddressInstructionPass.cpp | 131 void scanUses(unsigned DstReg); 340 unsigned &SrcReg, unsigned &DstReg, 343 DstReg = 0; 345 DstReg = MI.getOperand(0).getReg(); 348 DstReg = MI.getOperand(0).getReg(); 354 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 424 unsigned SrcReg, DstReg; local 427 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 435 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { argument 442 DstReg 339 isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, unsigned &SrcReg, unsigned &DstReg, bool &IsSrcPhys, bool &IsDstPhys) argument 452 findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, unsigned &DstReg, bool &IsDstPhys) argument 662 scanUses(unsigned DstReg) argument 723 unsigned SrcReg, DstReg; local 785 unsigned DstReg; local 974 unsigned DstReg; local 1312 unsigned DstReg = DstMO.getReg(); local 1548 unsigned DstReg = mi->getOperand(DstIdx).getReg(); local 1608 unsigned DstReg = MI->getOperand(0).getReg(); local [all...] |
H A D | ExpandPostRAPseudos.cpp | 85 unsigned DstReg = MI->getOperand(0).getReg(); local 91 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); 93 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) && 111 if (DstReg != InsReg) { 123 // Implicitly define DstReg for subsequent uses. 126 CopyMI->addRegisterDefined(DstReg);
|
H A D | RegisterCoalescer.cpp | 131 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, 175 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and 176 /// update the subregister number if it is not zero. If DstReg is a 180 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx); 253 SrcReg = DstReg = 0; 306 // SrcReg will be merged with a sub-register of DstReg. 310 // DstReg will be merged with a sub-register of SrcReg. 322 // Prefer SrcReg to be a sub-register of DstReg. 337 DstReg = Dst; 342 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) 738 unsigned DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg(); local 940 updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx) argument 2075 unsigned DstReg = Copy->getOperand(0).getReg(); local [all...] |
H A D | PeepholeOptimizer.cpp | 160 unsigned SrcReg, DstReg, SubIdx; local 161 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) 164 if (TargetRegisterInfo::isPhysicalRegister(DstReg) || 172 // Ensure DstReg can get a register class that actually supports 174 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); 191 UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end(); 274 UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end(); 287 // About to add uses of DstReg, clear DstReg's kill flags. 289 MRI->clearKillFlags(DstReg); [all...] |
H A D | EarlyIfConversion.cpp | 112 // Latencies from Cond+Branch, TReg, and FReg to DstReg. 462 unsigned DstReg = PI.PHI->getOperand(0).getReg(); local 463 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); 483 unsigned DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst)); local 484 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); 487 // Rewrite PHI operands TPred -> (DstReg, Head), remove FPred. 492 PI.PHI->getOperand(i-2).setReg(DstReg);
|
/freebsd-10-stable/contrib/llvm/lib/Target/R600/ |
H A D | R600ExpandSpecialInstrs.cpp | 116 unsigned DstReg; local 119 DstReg = MI.getOperand(Chan).getReg(); 121 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W; 124 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); 145 unsigned DstReg; local 148 DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y; 150 DstReg = MI.getOperand(Chan-2).getReg(); 153 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); 173 unsigned DstReg = MI.getOperand(0).getReg(); local 177 TRI.getSubReg(DstReg, TR 192 unsigned DstReg = MI.getOperand(0).getReg(); local 262 unsigned DstReg = MI.getOperand( local [all...] |
H A D | R600InstrInfo.h | 231 unsigned DstReg, 238 unsigned DstReg) const; 242 unsigned DstReg, 247 unsigned DstReg, unsigned SrcReg) const;
|
H A D | SIInstrInfo.h | 54 unsigned DstReg, unsigned SrcReg) const;
|
H A D | AMDGPUInstrInfo.h | 55 unsigned &DstReg, unsigned &SubIdx) const; 195 unsigned DstReg, unsigned SrcReg) const = 0;
|
H A D | SIFixSGPRCopies.cpp | 180 unsigned DstReg = Copy.getOperand(0).getReg(); local 183 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
|
H A D | SIInstrInfo.cpp | 230 unsigned DstReg, 233 DstReg) .addReg(SrcReg); 545 unsigned DstReg = MRI.createVirtualRegister(RC); local 547 get(AMDGPU::COPY), DstReg) 549 MI->getOperand(i).setReg(DstReg); 617 unsigned DstReg = Inst->getOperand(0).getReg(); local 619 MRI.replaceRegWith(DstReg, NewDstReg); 228 buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const argument
|
H A D | R600OptimizeVectorRegisters.cpp | 189 unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass); local 195 DstReg) 209 SrcVec = DstReg;
|
/freebsd-10-stable/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.h | 30 unsigned DstReg, int64_t Value, DebugLoc dl) const; 38 unsigned DstReg, int Offset, DebugLoc dl) const;
|
H A D | XCoreRegisterInfo.cpp | 246 unsigned DstReg, int64_t Value, DebugLoc dl) const { 254 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value); 245 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DstReg, int64_t Value, DebugLoc dl) const argument
|
/freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 141 unsigned DstReg = Dst.getReg(); local 144 if (TargetRegisterInfo::isVirtualRegister(DstReg) && 149 PeepholeMap[DstReg] = SrcReg; 163 unsigned DstReg = Dst.getReg(); local 165 PeepholeMap[DstReg] = SrcReg; 180 unsigned DstReg = Dst.getReg(); local 182 PeepholeDoubleRegsMap[DstReg] = 192 unsigned DstReg = Dst.getReg(); local 195 if (TargetRegisterInfo::isVirtualRegister(DstReg) && 200 PeepholeMap[DstReg] 215 unsigned DstReg = Dst.getReg(); local [all...] |
H A D | HexagonExpandPredSpillCode.cpp | 131 // DstReg = LDriw_pred [R30], ofst. 132 int DstReg = MI->getOperand(0).getReg(); local 133 assert(Hexagon::PredRegsRegClass.contains(DstReg) && 154 DstReg).addReg(HEXAGON_RESERVED_REG_2); 163 DstReg).addReg(HEXAGON_RESERVED_REG_2); 169 DstReg).addReg(HEXAGON_RESERVED_REG_2);
|
/freebsd-10-stable/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430RegisterInfo.cpp | 143 unsigned DstReg = MI.getOperand(0).getReg(); local 145 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg) 146 .addReg(DstReg).addImm(-Offset); 148 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg) 149 .addReg(DstReg).addImm(Offset);
|
/freebsd-10-stable/contrib/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 465 unsigned DstReg = I->getOperand(0).getReg(); local 466 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 467 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); 479 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; local 487 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 490 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 493 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); 499 unsigned DstReg local [all...] |
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 390 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); local 392 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 430 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 518 unsigned DstReg = 0; 522 DstReg = MI.getOperand(OpIdx++).getReg(); 523 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 572 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 619 unsigned DstReg = MI.getOperand(0).getReg(); local 628 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); 630 .addReg(DstReg, RegStat 886 unsigned DstReg = MI.getOperand(0).getReg(); local 910 unsigned DstReg = MI.getOperand(0).getReg(); local 982 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); local [all...] |
H A D | Thumb2ITBlockPass.cpp | 118 unsigned DstReg = MI->getOperand(0).getReg(); local 122 if (Uses.count(DstReg) || Defs.count(SrcReg))
|
/freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.h | 99 unsigned &SrcReg, unsigned &DstReg, 131 unsigned DstReg,
|
H A D | PPCFrameLowering.cpp | 137 unsigned DstReg = MI->getOperand(0).getReg(); local 140 if (DstReg != SrcReg) 141 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 149 if (DstReg != SrcReg) 150 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 158 if (DstReg != SrcReg) 159 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 163 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) [all...] |
/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.h | 97 unsigned DstReg, unsigned SrcReg, unsigned ScratchReg,
|