Searched refs:XEON_PHI_SBOX_BASE (Results 1 - 7 of 7) sorted by relevance

/barrelfish-master/kernel/include/arch/k1om/
H A Dxeon_phi.h32 #define XEON_PHI_SBOX_BASE 0x08007D0000ULL /* PCIE Box Registers */ macro
/barrelfish-master/kernel/arch/k1om/
H A Dinit.c297 paging_x86_64_map_table(&boot_pml4[X86_64_PML4_BASE(local_phys_to_mem(XEON_PHI_SBOX_BASE))],
299 paging_x86_64_map_table(&boot_pdpt_hi[X86_64_PDPT_BASE(local_phys_to_mem(XEON_PHI_SBOX_BASE))],
302 paging_x86_64_map_large(&boot_pdir_mmio[X86_64_PDIR_BASE(local_phys_to_mem(XEON_PHI_SBOX_BASE))],
303 XEON_PHI_SBOX_BASE,
444 kernel_sbox_base_address = local_phys_to_mem(XEON_PHI_SBOX_BASE);
H A Dstartup_arch.c389 err = caps_create_new(ObjType_DevFrame, XEON_PHI_SBOX_BASE,
/barrelfish-master/tools/weever/
H A Delf64.c35 #define XEON_PHI_SBOX_BASE 0x08007D0000ULL /* PCIE Box Registers */ macro
47 volatile uint32_t *p = (volatile uint32_t *) ((XEON_PHI_SBOX_BASE) + 0x0000AB40);
48 volatile uint32_t *p2 = (volatile uint32_t *) ((XEON_PHI_SBOX_BASE) + 0x0000AB5C);
/barrelfish-master/include/xeon_phi/
H A Dxeon_phi.h30 #define XEON_PHI_SBOX_BASE 0x08007D0000ULL /* PCIE Box Registers */ macro
/barrelfish-master/kernel/arch/x86_64/
H A Dpaging.c182 if (paging_x86_64_map_memory(XEON_PHI_SBOX_BASE, XEON_PHI_SBOX_SIZE) != 0) {
/barrelfish-master/kernel/arch/x86/
H A Dtiming.c105 freq = (uint32_t*)local_phys_to_mem(XEON_PHI_SBOX_BASE + 0x4100);

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