1/**
2 * \file
3 * \brief Header for Xeon Phi Specific Addresses
4 */
5
6/*
7 * Copyright (c) 2007, 2008, ETH Zurich.
8 * All rights reserved.
9 *
10 * This file is distributed under the terms in the attached LICENSE file.
11 * If you do not find this file, copies can be found by writing to:
12 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
13 */
14
15#ifndef XEON_PHI_H
16#define XEON_PHI_H
17
18#define XEON_PHI_CBOX_BASE           0x0ULL              /* P54C Core */
19#define XEON_PHI_TXS0_BASE           0x0800780000ULL     /* Texture Sampler */
20#define XEON_PHI_TXS1_BASE           0x0800770000ULL     /* Texture Sampler */
21#define XEON_PHI_TXS2_BASE           0x0800760000ULL     /* Texture Sampler */
22#define XEON_PHI_TXS3_BASE           0x0800750000ULL     /* Texture Sampler */
23#define XEON_PHI_TXS4_BASE           0x0800740000ULL     /* Texture Sampler */
24#define XEON_PHI_TXS5_BASE           0x0800730000ULL     /* Texture Sampler */
25#define XEON_PHI_TXS6_BASE           0x0800720000ULL     /* Texture Sampler */
26#define XEON_PHI_TXS7_BASE           0x0800710000ULL     /* Texture Sampler */
27#define XEON_PHI_DBOX0_BASE          0x08007C0000ULL     /* Display Box Registers */
28#define XEON_PHI_DBOX1_BASE          0x0800620000ULL     /* Display Box Registers */
29#define XEON_PHI_TD0_BASE            0x08007C0000ULL     /* Dbox Tag Directory TD */
30#define XEON_PHI_TD1_BASE            0x0800620000ULL     /* Dbox Tag Directory TD */
31#define XEON_PHI_VBOX_BASE           0x08007B0000ULL     /* Video Box Registers */
32#define XEON_PHI_SBOX_BASE           0x08007D0000ULL     /* PCIE Box Registers */
33#define XEON_PHI_GBOX0_BASE          0x08007A0000ULL     /* Gbox Front Box Registers */
34#define XEON_PHI_GBOX1_BASE          0x0800790000ULL     /* Gbox Front Box Registers */
35#define XEON_PHI_GBOX2_BASE          0x0800700000ULL     /* Gbox Front Box Registers */
36#define XEON_PHI_GBOX3_BASE          0x08006F0000ULL     /* Gbox Front Box Registers */
37#define XEON_PHI_GBOX4_BASE          0x08006D0000ULL     /* Gbox Front Box Registers */
38#define XEON_PHI_GBOX5_BASE          0x08006C0000ULL     /* Gbox Front Box Registers */
39#define XEON_PHI_GBOX6_BASE          0x08006B0000ULL     /* Gbox Front Box Registers */
40#define XEON_PHI_GBOX7_BASE          0x08006A0000ULL     /* Gbox Front Box Registers */
41#define XEON_PHI_REUT0_BASE          0x08007A0000ULL     /* Gbox REUT interface Registers */
42#define XEON_PHI_REUT1_BASE          0x0800790000ULL     /* Gbox REUT interface Registers */
43#define XEON_PHI_REUT2_BASE          0x0800700000ULL     /* Gbox REUT interface Registers */
44#define XEON_PHI_REUT3_BASE          0x08006F0000ULL     /* Gbox REUT interface Registers */
45#define XEON_PHI_REUT4_BASE          0x08006D0000ULL     /* Gbox REUT interface Registers */
46#define XEON_PHI_REUT5_BASE          0x08006C0000ULL     /* Gbox REUT interface Registers */
47#define XEON_PHI_REUT6_BASE          0x08006B0000ULL     /* Gbox REUT interface Registers */
48#define XEON_PHI_REUT7_BASE          0x08006A0000ULL     /* Gbox REUT interface Registers */
49
50#define XEON_PHI_GBOX_CHANNEL0_BASE  0x0
51#define XEON_PHI_GBOX_CHANNEL1_BASE  0x800
52#define XEON_PHI_GBOX_CHANNEL2_BASE  0x800
53#define XEON_PHI_GBOX_CHANNEL3_BASE  0x1000
54
55
56#define XEON_PHI_SBOX_SIZE (64*1024)
57#define XEON_PHI_SBOX_SIZE_BITS (16)
58
59// TODO: Verify these...
60#define XEON_PHI_GBOX_SIZE (64*1024)
61#define XEON_PHI_DBOX_SIZE (64*1024)
62#define XEON_PHI_CBOX_SIZE (64*1024)
63
64#define XEON_PHI_SYSMEM_BASE 0x8000000000UL
65#define XEON_PHI_SYSMEM_SIZE_BITS 39
66#define XEON_PHI_SYSMEM_SIZE (1ULL << XEON_PHI_SYSMEM_SIZE_BITS)
67
68
69
70void xeon_phi_init_early(void);
71
72#endif /* XEON_PHI_H*/
73