Searched refs:regChainOffset (Results 1 - 6 of 6) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/net/wireless/ath/ath9k/
H A Deeprom_def.c315 u8 txRxAttenLocal, int regChainOffset, int i)
321 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
324 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
327 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
330 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
334 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
335 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
339 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
340 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
349 AR_PHY_RXGAIN + regChainOffset,
312 ath9k_hw_def_set_gain(struct ath_hw *ah, struct modal_eep_header *pModal, struct ar5416_eeprom_def *eep, u8 txRxAttenLocal, int regChainOffset, int i) argument
373 int i, regChainOffset; local
842 u32 reg32, regOffset, regChainOffset; local
[all...]
H A Deeprom_9287.c466 u32 reg32, regOffset, regChainOffset, regval; local
513 regChainOffset = i * 0x1000;
556 AR_PHY_TPCRG5 + regChainOffset,
578 (672 << 2) + regChainOffset;
998 u32 regChainOffset, regval; local
1030 regChainOffset = i * 0x1000;
1032 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1035 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1036 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset)
1046 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
[all...]
H A Deeprom_4k.c402 u32 reg32, regOffset, regChainOffset; local
442 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
444 regChainOffset = i * 0x1000;
458 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
471 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
481 i, regChainOffset, regOffset,
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/wireless/ath/ath9k/
H A Deeprom_def.c315 u8 txRxAttenLocal, int regChainOffset, int i)
321 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
324 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
327 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
330 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
334 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
335 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
339 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
340 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
349 AR_PHY_RXGAIN + regChainOffset,
312 ath9k_hw_def_set_gain(struct ath_hw *ah, struct modal_eep_header *pModal, struct ar5416_eeprom_def *eep, u8 txRxAttenLocal, int regChainOffset, int i) argument
373 int i, regChainOffset; local
842 u32 reg32, regOffset, regChainOffset; local
[all...]
H A Deeprom_9287.c466 u32 reg32, regOffset, regChainOffset, regval; local
513 regChainOffset = i * 0x1000;
556 AR_PHY_TPCRG5 + regChainOffset,
578 (672 << 2) + regChainOffset;
998 u32 regChainOffset, regval; local
1030 regChainOffset = i * 0x1000;
1032 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1035 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1036 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset)
1046 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
[all...]
H A Deeprom_4k.c402 u32 reg32, regOffset, regChainOffset; local
442 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
444 regChainOffset = i * 0x1000;
458 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
471 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
481 i, regChainOffset, regOffset,

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