1/* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "hw.h" 18#include "ar9002_phy.h" 19 20static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah) 21{ 22 return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF); 23} 24 25static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah) 26{ 27 return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF); 28} 29 30static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) 31{ 32#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 33 struct ath_common *common = ath9k_hw_common(ah); 34 u16 *eep_data = (u16 *)&ah->eeprom.map4k; 35 int addr, eep_start_loc = 0; 36 37 eep_start_loc = 64; 38 39 if (!ath9k_hw_use_flash(ah)) { 40 ath_print(common, ATH_DBG_EEPROM, 41 "Reading from EEPROM, not flash\n"); 42 } 43 44 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { 45 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) { 46 ath_print(common, ATH_DBG_EEPROM, 47 "Unable to read eeprom region\n"); 48 return false; 49 } 50 eep_data++; 51 } 52 53 return true; 54#undef SIZE_EEPROM_4K 55} 56 57static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) 58{ 59#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 60 struct ath_common *common = ath9k_hw_common(ah); 61 struct ar5416_eeprom_4k *eep = 62 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k; 63 u16 *eepdata, temp, magic, magic2; 64 u32 sum = 0, el; 65 bool need_swap = false; 66 int i, addr; 67 68 69 if (!ath9k_hw_use_flash(ah)) { 70 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, 71 &magic)) { 72 ath_print(common, ATH_DBG_FATAL, 73 "Reading Magic # failed\n"); 74 return false; 75 } 76 77 ath_print(common, ATH_DBG_EEPROM, 78 "Read Magic = 0x%04X\n", magic); 79 80 if (magic != AR5416_EEPROM_MAGIC) { 81 magic2 = swab16(magic); 82 83 if (magic2 == AR5416_EEPROM_MAGIC) { 84 need_swap = true; 85 eepdata = (u16 *) (&ah->eeprom); 86 87 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) { 88 temp = swab16(*eepdata); 89 *eepdata = temp; 90 eepdata++; 91 } 92 } else { 93 ath_print(common, ATH_DBG_FATAL, 94 "Invalid EEPROM Magic. " 95 "endianness mismatch.\n"); 96 return -EINVAL; 97 } 98 } 99 } 100 101 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n", 102 need_swap ? "True" : "False"); 103 104 if (need_swap) 105 el = swab16(ah->eeprom.map4k.baseEepHeader.length); 106 else 107 el = ah->eeprom.map4k.baseEepHeader.length; 108 109 if (el > sizeof(struct ar5416_eeprom_4k)) 110 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16); 111 else 112 el = el / sizeof(u16); 113 114 eepdata = (u16 *)(&ah->eeprom); 115 116 for (i = 0; i < el; i++) 117 sum ^= *eepdata++; 118 119 if (need_swap) { 120 u32 integer; 121 u16 word; 122 123 ath_print(common, ATH_DBG_EEPROM, 124 "EEPROM Endianness is not native.. Changing\n"); 125 126 word = swab16(eep->baseEepHeader.length); 127 eep->baseEepHeader.length = word; 128 129 word = swab16(eep->baseEepHeader.checksum); 130 eep->baseEepHeader.checksum = word; 131 132 word = swab16(eep->baseEepHeader.version); 133 eep->baseEepHeader.version = word; 134 135 word = swab16(eep->baseEepHeader.regDmn[0]); 136 eep->baseEepHeader.regDmn[0] = word; 137 138 word = swab16(eep->baseEepHeader.regDmn[1]); 139 eep->baseEepHeader.regDmn[1] = word; 140 141 word = swab16(eep->baseEepHeader.rfSilent); 142 eep->baseEepHeader.rfSilent = word; 143 144 word = swab16(eep->baseEepHeader.blueToothOptions); 145 eep->baseEepHeader.blueToothOptions = word; 146 147 word = swab16(eep->baseEepHeader.deviceCap); 148 eep->baseEepHeader.deviceCap = word; 149 150 integer = swab32(eep->modalHeader.antCtrlCommon); 151 eep->modalHeader.antCtrlCommon = integer; 152 153 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) { 154 integer = swab32(eep->modalHeader.antCtrlChain[i]); 155 eep->modalHeader.antCtrlChain[i] = integer; 156 } 157 158 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 159 word = swab16(eep->modalHeader.spurChans[i].spurChan); 160 eep->modalHeader.spurChans[i].spurChan = word; 161 } 162 } 163 164 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || 165 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 166 ath_print(common, ATH_DBG_FATAL, 167 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 168 sum, ah->eep_ops->get_eeprom_ver(ah)); 169 return -EINVAL; 170 } 171 172 return 0; 173#undef EEPROM_4K_SIZE 174} 175 176static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah, 177 enum eeprom_param param) 178{ 179 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; 180 struct modal_eep_4k_header *pModal = &eep->modalHeader; 181 struct base_eep_header_4k *pBase = &eep->baseEepHeader; 182 183 switch (param) { 184 case EEP_NFTHRESH_2: 185 return pModal->noiseFloorThreshCh[0]; 186 case EEP_MAC_LSW: 187 return pBase->macAddr[0] << 8 | pBase->macAddr[1]; 188 case EEP_MAC_MID: 189 return pBase->macAddr[2] << 8 | pBase->macAddr[3]; 190 case EEP_MAC_MSW: 191 return pBase->macAddr[4] << 8 | pBase->macAddr[5]; 192 case EEP_REG_0: 193 return pBase->regDmn[0]; 194 case EEP_REG_1: 195 return pBase->regDmn[1]; 196 case EEP_OP_CAP: 197 return pBase->deviceCap; 198 case EEP_OP_MODE: 199 return pBase->opCapFlags; 200 case EEP_RF_SILENT: 201 return pBase->rfSilent; 202 case EEP_OB_2: 203 return pModal->ob_0; 204 case EEP_DB_2: 205 return pModal->db1_1; 206 case EEP_MINOR_REV: 207 return pBase->version & AR5416_EEP_VER_MINOR_MASK; 208 case EEP_TX_MASK: 209 return pBase->txMask; 210 case EEP_RX_MASK: 211 return pBase->rxMask; 212 case EEP_FRAC_N_5G: 213 return 0; 214 case EEP_PWR_TABLE_OFFSET: 215 return AR5416_PWR_TABLE_OFFSET_DB; 216 default: 217 return 0; 218 } 219} 220 221static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah, 222 struct ath9k_channel *chan, 223 struct cal_data_per_freq_4k *pRawDataSet, 224 u8 *bChans, u16 availPiers, 225 u16 tPdGainOverlap, 226 u16 *pPdGainBoundaries, u8 *pPDADCValues, 227 u16 numXpdGains) 228{ 229#define TMP_VAL_VPD_TABLE \ 230 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep)); 231 int i, j, k; 232 int16_t ss; 233 u16 idxL = 0, idxR = 0, numPiers; 234 static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS] 235 [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 236 static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS] 237 [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 238 static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS] 239 [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 240 241 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR; 242 u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS]; 243 u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS]; 244 int16_t vpdStep; 245 int16_t tmpVal; 246 u16 sizeCurrVpdTable, maxIndex, tgtIndex; 247 bool match; 248 int16_t minDelta = 0; 249 struct chan_centers centers; 250#define PD_GAIN_BOUNDARY_DEFAULT 58; 251 252 memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS); 253 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 254 255 for (numPiers = 0; numPiers < availPiers; numPiers++) { 256 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) 257 break; 258 } 259 260 match = ath9k_hw_get_lower_upper_index( 261 (u8)FREQ2FBIN(centers.synth_center, 262 IS_CHAN_2GHZ(chan)), bChans, numPiers, 263 &idxL, &idxR); 264 265 if (match) { 266 for (i = 0; i < numXpdGains; i++) { 267 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; 268 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; 269 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], 270 pRawDataSet[idxL].pwrPdg[i], 271 pRawDataSet[idxL].vpdPdg[i], 272 AR5416_EEP4K_PD_GAIN_ICEPTS, 273 vpdTableI[i]); 274 } 275 } else { 276 for (i = 0; i < numXpdGains; i++) { 277 pVpdL = pRawDataSet[idxL].vpdPdg[i]; 278 pPwrL = pRawDataSet[idxL].pwrPdg[i]; 279 pVpdR = pRawDataSet[idxR].vpdPdg[i]; 280 pPwrR = pRawDataSet[idxR].pwrPdg[i]; 281 282 minPwrT4[i] = max(pPwrL[0], pPwrR[0]); 283 284 maxPwrT4[i] = 285 min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1], 286 pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]); 287 288 289 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], 290 pPwrL, pVpdL, 291 AR5416_EEP4K_PD_GAIN_ICEPTS, 292 vpdTableL[i]); 293 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], 294 pPwrR, pVpdR, 295 AR5416_EEP4K_PD_GAIN_ICEPTS, 296 vpdTableR[i]); 297 298 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { 299 vpdTableI[i][j] = 300 (u8)(ath9k_hw_interpolate((u16) 301 FREQ2FBIN(centers. 302 synth_center, 303 IS_CHAN_2GHZ 304 (chan)), 305 bChans[idxL], bChans[idxR], 306 vpdTableL[i][j], vpdTableR[i][j])); 307 } 308 } 309 } 310 311 k = 0; 312 313 for (i = 0; i < numXpdGains; i++) { 314 if (i == (numXpdGains - 1)) 315 pPdGainBoundaries[i] = 316 (u16)(maxPwrT4[i] / 2); 317 else 318 pPdGainBoundaries[i] = 319 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4); 320 321 pPdGainBoundaries[i] = 322 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 323 324 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) { 325 minDelta = pPdGainBoundaries[0] - 23; 326 pPdGainBoundaries[0] = 23; 327 } else { 328 minDelta = 0; 329 } 330 331 if (i == 0) { 332 if (AR_SREV_9280_10_OR_LATER(ah)) 333 ss = (int16_t)(0 - (minPwrT4[i] / 2)); 334 else 335 ss = 0; 336 } else { 337 ss = (int16_t)((pPdGainBoundaries[i - 1] - 338 (minPwrT4[i] / 2)) - 339 tPdGainOverlap + 1 + minDelta); 340 } 341 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); 342 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 343 344 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 345 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); 346 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal); 347 ss++; 348 } 349 350 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1); 351 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap - 352 (minPwrT4[i] / 2)); 353 maxIndex = (tgtIndex < sizeCurrVpdTable) ? 354 tgtIndex : sizeCurrVpdTable; 355 356 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) 357 pPDADCValues[k++] = vpdTableI[i][ss++]; 358 359 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - 360 vpdTableI[i][sizeCurrVpdTable - 2]); 361 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 362 363 if (tgtIndex >= maxIndex) { 364 while ((ss <= tgtIndex) && 365 (k < (AR5416_NUM_PDADC_VALUES - 1))) { 366 tmpVal = (int16_t) TMP_VAL_VPD_TABLE; 367 pPDADCValues[k++] = (u8)((tmpVal > 255) ? 368 255 : tmpVal); 369 ss++; 370 } 371 } 372 } 373 374 while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) { 375 pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT; 376 i++; 377 } 378 379 while (k < AR5416_NUM_PDADC_VALUES) { 380 pPDADCValues[k] = pPDADCValues[k - 1]; 381 k++; 382 } 383 384 return; 385#undef TMP_VAL_VPD_TABLE 386} 387 388static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, 389 struct ath9k_channel *chan, 390 int16_t *pTxPowerIndexOffset) 391{ 392 struct ath_common *common = ath9k_hw_common(ah); 393 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; 394 struct cal_data_per_freq_4k *pRawDataset; 395 u8 *pCalBChans = NULL; 396 u16 pdGainOverlap_t2; 397 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; 398 u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK]; 399 u16 numPiers, i, j; 400 u16 numXpdGain, xpdMask; 401 u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 }; 402 u32 reg32, regOffset, regChainOffset; 403 404 xpdMask = pEepData->modalHeader.xpdGain; 405 406 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 407 AR5416_EEP_MINOR_VER_2) { 408 pdGainOverlap_t2 = 409 pEepData->modalHeader.pdGainOverlap; 410 } else { 411 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), 412 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 413 } 414 415 pCalBChans = pEepData->calFreqPier2G; 416 numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS; 417 418 numXpdGain = 0; 419 420 for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) { 421 if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) { 422 if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS) 423 break; 424 xpdGainValues[numXpdGain] = 425 (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i); 426 numXpdGain++; 427 } 428 } 429 430 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, 431 (numXpdGain - 1) & 0x3); 432 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, 433 xpdGainValues[0]); 434 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, 435 xpdGainValues[1]); 436 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0); 437 438 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) { 439 if (AR_SREV_5416_20_OR_LATER(ah) && 440 (ah->rxchainmask == 5 || ah->txchainmask == 5) && 441 (i != 0)) { 442 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 443 } else 444 regChainOffset = i * 0x1000; 445 446 if (pEepData->baseEepHeader.txMask & (1 << i)) { 447 pRawDataset = pEepData->calPierData2G[i]; 448 449 ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan, 450 pRawDataset, pCalBChans, 451 numPiers, pdGainOverlap_t2, 452 gainBoundaries, 453 pdadcValues, numXpdGain); 454 455 ENABLE_REGWRITE_BUFFER(ah); 456 457 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) { 458 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, 459 SM(pdGainOverlap_t2, 460 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) 461 | SM(gainBoundaries[0], 462 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) 463 | SM(gainBoundaries[1], 464 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) 465 | SM(gainBoundaries[2], 466 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) 467 | SM(gainBoundaries[3], 468 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); 469 } 470 471 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; 472 for (j = 0; j < 32; j++) { 473 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | 474 ((pdadcValues[4 * j + 1] & 0xFF) << 8) | 475 ((pdadcValues[4 * j + 2] & 0xFF) << 16)| 476 ((pdadcValues[4 * j + 3] & 0xFF) << 24); 477 REG_WRITE(ah, regOffset, reg32); 478 479 ath_print(common, ATH_DBG_EEPROM, 480 "PDADC (%d,%4x): %4.4x %8.8x\n", 481 i, regChainOffset, regOffset, 482 reg32); 483 ath_print(common, ATH_DBG_EEPROM, 484 "PDADC: Chain %d | " 485 "PDADC %3d Value %3d | " 486 "PDADC %3d Value %3d | " 487 "PDADC %3d Value %3d | " 488 "PDADC %3d Value %3d |\n", 489 i, 4 * j, pdadcValues[4 * j], 490 4 * j + 1, pdadcValues[4 * j + 1], 491 4 * j + 2, pdadcValues[4 * j + 2], 492 4 * j + 3, 493 pdadcValues[4 * j + 3]); 494 495 regOffset += 4; 496 } 497 498 REGWRITE_BUFFER_FLUSH(ah); 499 DISABLE_REGWRITE_BUFFER(ah); 500 } 501 } 502 503 *pTxPowerIndexOffset = 0; 504} 505 506static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, 507 struct ath9k_channel *chan, 508 int16_t *ratesArray, 509 u16 cfgCtl, 510 u16 AntennaReduction, 511 u16 twiceMaxRegulatoryPower, 512 u16 powerLimit) 513{ 514#define CMP_TEST_GRP \ 515 (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) == \ 516 pEepData->ctlIndex[i]) \ 517 || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \ 518 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL)) 519 520 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 521 int i; 522 int16_t twiceLargestAntenna; 523 u16 twiceMinEdgePower; 524 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 525 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; 526 u16 numCtlModes, *pCtlMode, ctlMode, freq; 527 struct chan_centers centers; 528 struct cal_ctl_data_4k *rep; 529 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; 530 static const u16 tpScaleReductionTable[5] = 531 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; 532 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { 533 0, { 0, 0, 0, 0} 534 }; 535 struct cal_target_power_leg targetPowerOfdmExt = { 536 0, { 0, 0, 0, 0} }, targetPowerCckExt = { 537 0, { 0, 0, 0, 0 } 538 }; 539 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { 540 0, {0, 0, 0, 0} 541 }; 542 u16 ctlModesFor11g[] = 543 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, 544 CTL_2GHT40 545 }; 546 547 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 548 549 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; 550 twiceLargestAntenna = (int16_t)min(AntennaReduction - 551 twiceLargestAntenna, 0); 552 553 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; 554 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) { 555 maxRegAllowedPower -= 556 (tpScaleReductionTable[(regulatory->tp_scale)] * 2); 557 } 558 559 scaledPower = min(powerLimit, maxRegAllowedPower); 560 scaledPower = max((u16)0, scaledPower); 561 562 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; 563 pCtlMode = ctlModesFor11g; 564 565 ath9k_hw_get_legacy_target_powers(ah, chan, 566 pEepData->calTargetPowerCck, 567 AR5416_NUM_2G_CCK_TARGET_POWERS, 568 &targetPowerCck, 4, false); 569 ath9k_hw_get_legacy_target_powers(ah, chan, 570 pEepData->calTargetPower2G, 571 AR5416_NUM_2G_20_TARGET_POWERS, 572 &targetPowerOfdm, 4, false); 573 ath9k_hw_get_target_powers(ah, chan, 574 pEepData->calTargetPower2GHT20, 575 AR5416_NUM_2G_20_TARGET_POWERS, 576 &targetPowerHt20, 8, false); 577 578 if (IS_CHAN_HT40(chan)) { 579 numCtlModes = ARRAY_SIZE(ctlModesFor11g); 580 ath9k_hw_get_target_powers(ah, chan, 581 pEepData->calTargetPower2GHT40, 582 AR5416_NUM_2G_40_TARGET_POWERS, 583 &targetPowerHt40, 8, true); 584 ath9k_hw_get_legacy_target_powers(ah, chan, 585 pEepData->calTargetPowerCck, 586 AR5416_NUM_2G_CCK_TARGET_POWERS, 587 &targetPowerCckExt, 4, true); 588 ath9k_hw_get_legacy_target_powers(ah, chan, 589 pEepData->calTargetPower2G, 590 AR5416_NUM_2G_20_TARGET_POWERS, 591 &targetPowerOfdmExt, 4, true); 592 } 593 594 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 595 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 596 (pCtlMode[ctlMode] == CTL_2GHT40); 597 598 if (isHt40CtlMode) 599 freq = centers.synth_center; 600 else if (pCtlMode[ctlMode] & EXT_ADDITIVE) 601 freq = centers.ext_center; 602 else 603 freq = centers.ctl_center; 604 605 if (ah->eep_ops->get_eeprom_ver(ah) == 14 && 606 ah->eep_ops->get_eeprom_rev(ah) <= 2) 607 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 608 609 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) && 610 pEepData->ctlIndex[i]; i++) { 611 612 if (CMP_TEST_GRP) { 613 rep = &(pEepData->ctlData[i]); 614 615 twiceMinEdgePower = ath9k_hw_get_max_edge_power( 616 freq, 617 rep->ctlEdges[ 618 ar5416_get_ntxchains(ah->txchainmask) - 1], 619 IS_CHAN_2GHZ(chan), 620 AR5416_EEP4K_NUM_BAND_EDGES); 621 622 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 623 twiceMaxEdgePower = 624 min(twiceMaxEdgePower, 625 twiceMinEdgePower); 626 } else { 627 twiceMaxEdgePower = twiceMinEdgePower; 628 break; 629 } 630 } 631 } 632 633 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); 634 635 switch (pCtlMode[ctlMode]) { 636 case CTL_11B: 637 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { 638 targetPowerCck.tPow2x[i] = 639 min((u16)targetPowerCck.tPow2x[i], 640 minCtlPower); 641 } 642 break; 643 case CTL_11G: 644 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) { 645 targetPowerOfdm.tPow2x[i] = 646 min((u16)targetPowerOfdm.tPow2x[i], 647 minCtlPower); 648 } 649 break; 650 case CTL_2GHT20: 651 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) { 652 targetPowerHt20.tPow2x[i] = 653 min((u16)targetPowerHt20.tPow2x[i], 654 minCtlPower); 655 } 656 break; 657 case CTL_11B_EXT: 658 targetPowerCckExt.tPow2x[0] = 659 min((u16)targetPowerCckExt.tPow2x[0], 660 minCtlPower); 661 break; 662 case CTL_11G_EXT: 663 targetPowerOfdmExt.tPow2x[0] = 664 min((u16)targetPowerOfdmExt.tPow2x[0], 665 minCtlPower); 666 break; 667 case CTL_2GHT40: 668 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { 669 targetPowerHt40.tPow2x[i] = 670 min((u16)targetPowerHt40.tPow2x[i], 671 minCtlPower); 672 } 673 break; 674 default: 675 break; 676 } 677 } 678 679 ratesArray[rate6mb] = 680 ratesArray[rate9mb] = 681 ratesArray[rate12mb] = 682 ratesArray[rate18mb] = 683 ratesArray[rate24mb] = 684 targetPowerOfdm.tPow2x[0]; 685 686 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; 687 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; 688 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; 689 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; 690 691 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) 692 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; 693 694 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; 695 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; 696 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; 697 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; 698 699 if (IS_CHAN_HT40(chan)) { 700 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { 701 ratesArray[rateHt40_0 + i] = 702 targetPowerHt40.tPow2x[i]; 703 } 704 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; 705 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; 706 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 707 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; 708 } 709 710#undef CMP_TEST_GRP 711} 712 713static void ath9k_hw_4k_set_txpower(struct ath_hw *ah, 714 struct ath9k_channel *chan, 715 u16 cfgCtl, 716 u8 twiceAntennaReduction, 717 u8 twiceMaxRegulatoryPower, 718 u8 powerLimit) 719{ 720 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 721 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; 722 struct modal_eep_4k_header *pModal = &pEepData->modalHeader; 723 int16_t ratesArray[Ar5416RateSize]; 724 int16_t txPowerIndexOffset = 0; 725 u8 ht40PowerIncForPdadc = 2; 726 int i; 727 728 memset(ratesArray, 0, sizeof(ratesArray)); 729 730 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 731 AR5416_EEP_MINOR_VER_2) { 732 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 733 } 734 735 ath9k_hw_set_4k_power_per_rate_table(ah, chan, 736 &ratesArray[0], cfgCtl, 737 twiceAntennaReduction, 738 twiceMaxRegulatoryPower, 739 powerLimit); 740 741 ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset); 742 743 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { 744 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 745 if (ratesArray[i] > AR5416_MAX_RATE_POWER) 746 ratesArray[i] = AR5416_MAX_RATE_POWER; 747 } 748 749 750 /* Update regulatory */ 751 752 i = rate6mb; 753 if (IS_CHAN_HT40(chan)) 754 i = rateHt40_0; 755 else if (IS_CHAN_HT20(chan)) 756 i = rateHt20_0; 757 758 regulatory->max_power_level = ratesArray[i]; 759 760 if (AR_SREV_9280_10_OR_LATER(ah)) { 761 for (i = 0; i < Ar5416RateSize; i++) 762 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; 763 } 764 765 ENABLE_REGWRITE_BUFFER(ah); 766 767 /* OFDM power per rate */ 768 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 769 ATH9K_POW_SM(ratesArray[rate18mb], 24) 770 | ATH9K_POW_SM(ratesArray[rate12mb], 16) 771 | ATH9K_POW_SM(ratesArray[rate9mb], 8) 772 | ATH9K_POW_SM(ratesArray[rate6mb], 0)); 773 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 774 ATH9K_POW_SM(ratesArray[rate54mb], 24) 775 | ATH9K_POW_SM(ratesArray[rate48mb], 16) 776 | ATH9K_POW_SM(ratesArray[rate36mb], 8) 777 | ATH9K_POW_SM(ratesArray[rate24mb], 0)); 778 779 /* CCK power per rate */ 780 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 781 ATH9K_POW_SM(ratesArray[rate2s], 24) 782 | ATH9K_POW_SM(ratesArray[rate2l], 16) 783 | ATH9K_POW_SM(ratesArray[rateXr], 8) 784 | ATH9K_POW_SM(ratesArray[rate1l], 0)); 785 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 786 ATH9K_POW_SM(ratesArray[rate11s], 24) 787 | ATH9K_POW_SM(ratesArray[rate11l], 16) 788 | ATH9K_POW_SM(ratesArray[rate5_5s], 8) 789 | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); 790 791 /* HT20 power per rate */ 792 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 793 ATH9K_POW_SM(ratesArray[rateHt20_3], 24) 794 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) 795 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) 796 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); 797 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, 798 ATH9K_POW_SM(ratesArray[rateHt20_7], 24) 799 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) 800 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) 801 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); 802 803 /* HT40 power per rate */ 804 if (IS_CHAN_HT40(chan)) { 805 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 806 ATH9K_POW_SM(ratesArray[rateHt40_3] + 807 ht40PowerIncForPdadc, 24) 808 | ATH9K_POW_SM(ratesArray[rateHt40_2] + 809 ht40PowerIncForPdadc, 16) 810 | ATH9K_POW_SM(ratesArray[rateHt40_1] + 811 ht40PowerIncForPdadc, 8) 812 | ATH9K_POW_SM(ratesArray[rateHt40_0] + 813 ht40PowerIncForPdadc, 0)); 814 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 815 ATH9K_POW_SM(ratesArray[rateHt40_7] + 816 ht40PowerIncForPdadc, 24) 817 | ATH9K_POW_SM(ratesArray[rateHt40_6] + 818 ht40PowerIncForPdadc, 16) 819 | ATH9K_POW_SM(ratesArray[rateHt40_5] + 820 ht40PowerIncForPdadc, 8) 821 | ATH9K_POW_SM(ratesArray[rateHt40_4] + 822 ht40PowerIncForPdadc, 0)); 823 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 824 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) 825 | ATH9K_POW_SM(ratesArray[rateExtCck], 16) 826 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) 827 | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); 828 } 829 830 REGWRITE_BUFFER_FLUSH(ah); 831 DISABLE_REGWRITE_BUFFER(ah); 832} 833 834static void ath9k_hw_4k_set_addac(struct ath_hw *ah, 835 struct ath9k_channel *chan) 836{ 837 struct modal_eep_4k_header *pModal; 838 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; 839 u8 biaslevel; 840 841 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) 842 return; 843 844 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7) 845 return; 846 847 pModal = &eep->modalHeader; 848 849 if (pModal->xpaBiasLvl != 0xff) { 850 biaslevel = pModal->xpaBiasLvl; 851 INI_RA(&ah->iniAddac, 7, 1) = 852 (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; 853 } 854} 855 856static void ath9k_hw_4k_set_gain(struct ath_hw *ah, 857 struct modal_eep_4k_header *pModal, 858 struct ar5416_eeprom_4k *eep, 859 u8 txRxAttenLocal) 860{ 861 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, 862 pModal->antCtrlChain[0]); 863 864 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), 865 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & 866 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 867 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 868 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 869 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 870 871 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 872 AR5416_EEP_MINOR_VER_3) { 873 txRxAttenLocal = pModal->txRxAttenCh[0]; 874 875 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 876 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); 877 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 878 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 879 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 880 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 881 pModal->xatten2Margin[0]); 882 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 883 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 884 885 /* Set the block 1 value to block 0 value */ 886 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 887 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 888 pModal->bswMargin[0]); 889 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 890 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 891 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 892 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 893 pModal->xatten2Margin[0]); 894 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 895 AR_PHY_GAIN_2GHZ_XATTEN2_DB, 896 pModal->xatten2Db[0]); 897 } 898 899 REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 900 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 901 REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 902 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 903 904 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 905 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 906 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 907 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 908 909 if (AR_SREV_9285_11(ah)) 910 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); 911} 912 913/* 914 * Read EEPROM header info and program the device for correct operation 915 * given the channel value. 916 */ 917static void ath9k_hw_4k_set_board_values(struct ath_hw *ah, 918 struct ath9k_channel *chan) 919{ 920 struct modal_eep_4k_header *pModal; 921 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; 922 u8 txRxAttenLocal; 923 u8 ob[5], db1[5], db2[5]; 924 u8 ant_div_control1, ant_div_control2; 925 u32 regVal; 926 927 pModal = &eep->modalHeader; 928 txRxAttenLocal = 23; 929 930 REG_WRITE(ah, AR_PHY_SWITCH_COM, 931 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan)); 932 933 /* Single chain for 4K EEPROM*/ 934 ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal); 935 936 /* Initialize Ant Diversity settings from EEPROM */ 937 if (pModal->version >= 3) { 938 ant_div_control1 = pModal->antdiv_ctl1; 939 ant_div_control2 = pModal->antdiv_ctl2; 940 941 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 942 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); 943 944 regVal |= SM(ant_div_control1, 945 AR_PHY_9285_ANT_DIV_CTL); 946 regVal |= SM(ant_div_control2, 947 AR_PHY_9285_ANT_DIV_ALT_LNACONF); 948 regVal |= SM((ant_div_control2 >> 2), 949 AR_PHY_9285_ANT_DIV_MAIN_LNACONF); 950 regVal |= SM((ant_div_control1 >> 1), 951 AR_PHY_9285_ANT_DIV_ALT_GAINTB); 952 regVal |= SM((ant_div_control1 >> 2), 953 AR_PHY_9285_ANT_DIV_MAIN_GAINTB); 954 955 956 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); 957 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 958 regVal = REG_READ(ah, AR_PHY_CCK_DETECT); 959 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 960 regVal |= SM((ant_div_control1 >> 3), 961 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 962 963 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal); 964 regVal = REG_READ(ah, AR_PHY_CCK_DETECT); 965 } 966 967 if (pModal->version >= 2) { 968 ob[0] = pModal->ob_0; 969 ob[1] = pModal->ob_1; 970 ob[2] = pModal->ob_2; 971 ob[3] = pModal->ob_3; 972 ob[4] = pModal->ob_4; 973 974 db1[0] = pModal->db1_0; 975 db1[1] = pModal->db1_1; 976 db1[2] = pModal->db1_2; 977 db1[3] = pModal->db1_3; 978 db1[4] = pModal->db1_4; 979 980 db2[0] = pModal->db2_0; 981 db2[1] = pModal->db2_1; 982 db2[2] = pModal->db2_2; 983 db2[3] = pModal->db2_3; 984 db2[4] = pModal->db2_4; 985 } else if (pModal->version == 1) { 986 ob[0] = pModal->ob_0; 987 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1; 988 db1[0] = pModal->db1_0; 989 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1; 990 db2[0] = pModal->db2_0; 991 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1; 992 } else { 993 int i; 994 995 for (i = 0; i < 5; i++) { 996 ob[i] = pModal->ob_0; 997 db1[i] = pModal->db1_0; 998 db2[i] = pModal->db1_0; 999 } 1000 } 1001 1002 if (AR_SREV_9271(ah)) { 1003 ath9k_hw_analog_shift_rmw(ah, 1004 AR9285_AN_RF2G3, 1005 AR9271_AN_RF2G3_OB_cck, 1006 AR9271_AN_RF2G3_OB_cck_S, 1007 ob[0]); 1008 ath9k_hw_analog_shift_rmw(ah, 1009 AR9285_AN_RF2G3, 1010 AR9271_AN_RF2G3_OB_psk, 1011 AR9271_AN_RF2G3_OB_psk_S, 1012 ob[1]); 1013 ath9k_hw_analog_shift_rmw(ah, 1014 AR9285_AN_RF2G3, 1015 AR9271_AN_RF2G3_OB_qam, 1016 AR9271_AN_RF2G3_OB_qam_S, 1017 ob[2]); 1018 ath9k_hw_analog_shift_rmw(ah, 1019 AR9285_AN_RF2G3, 1020 AR9271_AN_RF2G3_DB_1, 1021 AR9271_AN_RF2G3_DB_1_S, 1022 db1[0]); 1023 ath9k_hw_analog_shift_rmw(ah, 1024 AR9285_AN_RF2G4, 1025 AR9271_AN_RF2G4_DB_2, 1026 AR9271_AN_RF2G4_DB_2_S, 1027 db2[0]); 1028 } else { 1029 ath9k_hw_analog_shift_rmw(ah, 1030 AR9285_AN_RF2G3, 1031 AR9285_AN_RF2G3_OB_0, 1032 AR9285_AN_RF2G3_OB_0_S, 1033 ob[0]); 1034 ath9k_hw_analog_shift_rmw(ah, 1035 AR9285_AN_RF2G3, 1036 AR9285_AN_RF2G3_OB_1, 1037 AR9285_AN_RF2G3_OB_1_S, 1038 ob[1]); 1039 ath9k_hw_analog_shift_rmw(ah, 1040 AR9285_AN_RF2G3, 1041 AR9285_AN_RF2G3_OB_2, 1042 AR9285_AN_RF2G3_OB_2_S, 1043 ob[2]); 1044 ath9k_hw_analog_shift_rmw(ah, 1045 AR9285_AN_RF2G3, 1046 AR9285_AN_RF2G3_OB_3, 1047 AR9285_AN_RF2G3_OB_3_S, 1048 ob[3]); 1049 ath9k_hw_analog_shift_rmw(ah, 1050 AR9285_AN_RF2G3, 1051 AR9285_AN_RF2G3_OB_4, 1052 AR9285_AN_RF2G3_OB_4_S, 1053 ob[4]); 1054 1055 ath9k_hw_analog_shift_rmw(ah, 1056 AR9285_AN_RF2G3, 1057 AR9285_AN_RF2G3_DB1_0, 1058 AR9285_AN_RF2G3_DB1_0_S, 1059 db1[0]); 1060 ath9k_hw_analog_shift_rmw(ah, 1061 AR9285_AN_RF2G3, 1062 AR9285_AN_RF2G3_DB1_1, 1063 AR9285_AN_RF2G3_DB1_1_S, 1064 db1[1]); 1065 ath9k_hw_analog_shift_rmw(ah, 1066 AR9285_AN_RF2G3, 1067 AR9285_AN_RF2G3_DB1_2, 1068 AR9285_AN_RF2G3_DB1_2_S, 1069 db1[2]); 1070 ath9k_hw_analog_shift_rmw(ah, 1071 AR9285_AN_RF2G4, 1072 AR9285_AN_RF2G4_DB1_3, 1073 AR9285_AN_RF2G4_DB1_3_S, 1074 db1[3]); 1075 ath9k_hw_analog_shift_rmw(ah, 1076 AR9285_AN_RF2G4, 1077 AR9285_AN_RF2G4_DB1_4, 1078 AR9285_AN_RF2G4_DB1_4_S, db1[4]); 1079 1080 ath9k_hw_analog_shift_rmw(ah, 1081 AR9285_AN_RF2G4, 1082 AR9285_AN_RF2G4_DB2_0, 1083 AR9285_AN_RF2G4_DB2_0_S, 1084 db2[0]); 1085 ath9k_hw_analog_shift_rmw(ah, 1086 AR9285_AN_RF2G4, 1087 AR9285_AN_RF2G4_DB2_1, 1088 AR9285_AN_RF2G4_DB2_1_S, 1089 db2[1]); 1090 ath9k_hw_analog_shift_rmw(ah, 1091 AR9285_AN_RF2G4, 1092 AR9285_AN_RF2G4_DB2_2, 1093 AR9285_AN_RF2G4_DB2_2_S, 1094 db2[2]); 1095 ath9k_hw_analog_shift_rmw(ah, 1096 AR9285_AN_RF2G4, 1097 AR9285_AN_RF2G4_DB2_3, 1098 AR9285_AN_RF2G4_DB2_3_S, 1099 db2[3]); 1100 ath9k_hw_analog_shift_rmw(ah, 1101 AR9285_AN_RF2G4, 1102 AR9285_AN_RF2G4_DB2_4, 1103 AR9285_AN_RF2G4_DB2_4_S, 1104 db2[4]); 1105 } 1106 1107 1108 if (AR_SREV_9285_11(ah)) 1109 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT); 1110 1111 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 1112 pModal->switchSettling); 1113 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, 1114 pModal->adcDesiredSize); 1115 1116 REG_WRITE(ah, AR_PHY_RF_CTL4, 1117 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | 1118 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | 1119 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | 1120 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 1121 1122 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 1123 pModal->txEndToRxOn); 1124 1125 if (AR_SREV_9271_10(ah)) 1126 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 1127 pModal->txEndToRxOn); 1128 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 1129 pModal->thresh62); 1130 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 1131 pModal->thresh62); 1132 1133 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 1134 AR5416_EEP_MINOR_VER_2) { 1135 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START, 1136 pModal->txFrameToDataStart); 1137 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, 1138 pModal->txFrameToPaOn); 1139 } 1140 1141 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 1142 AR5416_EEP_MINOR_VER_3) { 1143 if (IS_CHAN_HT40(chan)) 1144 REG_RMW_FIELD(ah, AR_PHY_SETTLING, 1145 AR_PHY_SETTLING_SWITCH, 1146 pModal->swSettleHt40); 1147 } 1148} 1149 1150static u32 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah, 1151 struct ath9k_channel *chan) 1152{ 1153 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; 1154 struct modal_eep_4k_header *pModal = &eep->modalHeader; 1155 1156 return pModal->antCtrlCommon; 1157} 1158 1159static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah, 1160 enum ieee80211_band freq_band) 1161{ 1162 return 1; 1163} 1164 1165static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) 1166{ 1167#define EEP_MAP4K_SPURCHAN \ 1168 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan) 1169 struct ath_common *common = ath9k_hw_common(ah); 1170 1171 u16 spur_val = AR_NO_SPUR; 1172 1173 ath_print(common, ATH_DBG_ANI, 1174 "Getting spur idx %d is2Ghz. %d val %x\n", 1175 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1176 1177 switch (ah->config.spurmode) { 1178 case SPUR_DISABLE: 1179 break; 1180 case SPUR_ENABLE_IOCTL: 1181 spur_val = ah->config.spurchans[i][is2GHz]; 1182 ath_print(common, ATH_DBG_ANI, 1183 "Getting spur val from new loc. %d\n", spur_val); 1184 break; 1185 case SPUR_ENABLE_EEPROM: 1186 spur_val = EEP_MAP4K_SPURCHAN; 1187 break; 1188 } 1189 1190 return spur_val; 1191 1192#undef EEP_MAP4K_SPURCHAN 1193} 1194 1195const struct eeprom_ops eep_4k_ops = { 1196 .check_eeprom = ath9k_hw_4k_check_eeprom, 1197 .get_eeprom = ath9k_hw_4k_get_eeprom, 1198 .fill_eeprom = ath9k_hw_4k_fill_eeprom, 1199 .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver, 1200 .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev, 1201 .get_num_ant_config = ath9k_hw_4k_get_num_ant_config, 1202 .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg, 1203 .set_board_values = ath9k_hw_4k_set_board_values, 1204 .set_addac = ath9k_hw_4k_set_addac, 1205 .set_txpower = ath9k_hw_4k_set_txpower, 1206 .get_spur_channel = ath9k_hw_4k_get_spur_channel 1207}; 1208