Searched refs:h_gr (Results 1 - 25 of 60) sorted by relevance

123

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/sh64/
H A D	cpu.h	49 DI h_gr[64]; member in struct:__anon4285::__anon4286 50 #define GET_H_GR(index) ((((index) == (63))) ? (0) : (CPU (h_gr[index]))) 54 CPU (h_gr[(index)]) = (x);\ 125 #define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff)) 128 CPU (h_gr[(index)]) = EXTSIDI ((x));\ 213 #define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1) 216 CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\ 218 #define GET_H_VBR() SUBWORDDISI (CPU (h_gr[((UINT) 20)]), 1) 221 CPU (h_gr[((UINT) 20)]) = EXTSIDI ((x));\ 223 #define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UIN [all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/sh64/
H A D	cpu.h	49 DI h_gr[64]; member in struct:__anon3380::__anon3381 50 #define GET_H_GR(index) ((((index) == (63))) ? (0) : (CPU (h_gr[index]))) 54 CPU (h_gr[(index)]) = (x);\ 125 #define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff)) 128 CPU (h_gr[(index)]) = EXTSIDI ((x));\ 213 #define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1) 216 CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\ 218 #define GET_H_VBR() SUBWORDDISI (CPU (h_gr[((UINT) 20)]), 1) 221 CPU (h_gr[((UINT) 20)]) = EXTSIDI ((x));\ 223 #define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UIN [all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/sh64/
H A D	cpu.h	49 DI h_gr[64]; member in struct:__anon38310::__anon38311 50 #define GET_H_GR(index) ((((index) == (63))) ? (0) : (CPU (h_gr[index]))) 54 CPU (h_gr[(index)]) = (x);\ 125 #define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff)) 128 CPU (h_gr[(index)]) = EXTSIDI ((x));\ 213 #define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1) 216 CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\ 218 #define GET_H_VBR() SUBWORDDISI (CPU (h_gr[((UINT) 20)]), 1) 221 CPU (h_gr[((UINT) 20)]) = EXTSIDI ((x));\ 223 #define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UIN [all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/m32r/
H A D	m32r2.c	62 return CPU (h_gr[H_GR_SP]); 67 return CPU (h_gr[H_GR_SP]); 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); 101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); 106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); 120 CPU (h_gr[H_GR_SP]) = newval; 126 CPU (h_gr[H_GR_SP]) = newval; 235 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; 238 && (h_gr 233 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; local [all...]
H A D	m32rx.c	62 return CPU (h_gr[H_GR_SP]); 67 return CPU (h_gr[H_GR_SP]); 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); 101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); 106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); 120 CPU (h_gr[H_GR_SP]) = newval; 126 CPU (h_gr[H_GR_SP]) = newval; 235 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; 238 && (h_gr 233 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; local [all...]
H A D	decode2.c	638 FLD (i_dr) = & CPU (h_gr)[f_r1]; 639 FLD (i_sr) = & CPU (h_gr)[f_r2]; 672 FLD (i_sr) = & CPU (h_gr)[f_r2]; 673 FLD (i_dr) = & CPU (h_gr)[f_r1]; 705 FLD (i_sr) = & CPU (h_gr)[f_r2]; 706 FLD (i_dr) = & CPU (h_gr)[f_r1]; 738 FLD (i_sr) = & CPU (h_gr)[f_r2]; 739 FLD (i_dr) = & CPU (h_gr)[f_r1]; 768 FLD (i_dr) = & CPU (h_gr)[f_r1]; 797 FLD (i_dr) = & CPU (h_gr)[f_r [all...]
H A D	decodex.c	600 FLD (i_dr) = & CPU (h_gr)[f_r1]; 601 FLD (i_sr) = & CPU (h_gr)[f_r2]; 634 FLD (i_sr) = & CPU (h_gr)[f_r2]; 635 FLD (i_dr) = & CPU (h_gr)[f_r1]; 667 FLD (i_sr) = & CPU (h_gr)[f_r2]; 668 FLD (i_dr) = & CPU (h_gr)[f_r1]; 700 FLD (i_sr) = & CPU (h_gr)[f_r2]; 701 FLD (i_dr) = & CPU (h_gr)[f_r1]; 730 FLD (i_dr) = & CPU (h_gr)[f_r1]; 759 FLD (i_dr) = & CPU (h_gr)[f_r [all...]
H A D	m32r.c	143 return CPU (h_gr[H_GR_SP]); 148 return CPU (h_gr[H_GR_SP]); 181 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); 182 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); 187 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); 188 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); 201 CPU (h_gr[H_GR_SP]) = newval; 207 CPU (h_gr[H_GR_SP]) = newval; 328 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; 331 && (h_gr 326 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; local [all...]
H A D	decode.c	500 FLD (i_dr) = & CPU (h_gr)[f_r1]; 501 FLD (i_sr) = & CPU (h_gr)[f_r2]; 534 FLD (i_sr) = & CPU (h_gr)[f_r2]; 535 FLD (i_dr) = & CPU (h_gr)[f_r1]; 567 FLD (i_sr) = & CPU (h_gr)[f_r2]; 568 FLD (i_dr) = & CPU (h_gr)[f_r1]; 600 FLD (i_sr) = & CPU (h_gr)[f_r2]; 601 FLD (i_dr) = & CPU (h_gr)[f_r1]; 630 FLD (i_dr) = & CPU (h_gr)[f_r1]; 659 FLD (i_dr) = & CPU (h_gr)[f_r [all...]
H A D	cpu.c	51 return CPU (h_gr[regno]); 59 CPU (h_gr[regno]) = newval;
H A D	cpu2.c	51 return CPU (h_gr[regno]); 59 CPU (h_gr[regno]) = newval;
H A D	cpux.c	51 return CPU (h_gr[regno]); 59 CPU (h_gr[regno]) = newval;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/m32r/
H A D	m32r2.c	62 return CPU (h_gr[H_GR_SP]); 67 return CPU (h_gr[H_GR_SP]); 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); 101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); 106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); 120 CPU (h_gr[H_GR_SP]) = newval; 126 CPU (h_gr[H_GR_SP]) = newval; 235 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; 238 && (h_gr 233 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; local [all...]
H A D	m32rx.c	62 return CPU (h_gr[H_GR_SP]); 67 return CPU (h_gr[H_GR_SP]); 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); 101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); 106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); 120 CPU (h_gr[H_GR_SP]) = newval; 126 CPU (h_gr[H_GR_SP]) = newval; 235 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; 238 && (h_gr 233 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; local [all...]
H A D	decode2.c	638 FLD (i_dr) = & CPU (h_gr)[f_r1]; 639 FLD (i_sr) = & CPU (h_gr)[f_r2]; 672 FLD (i_sr) = & CPU (h_gr)[f_r2]; 673 FLD (i_dr) = & CPU (h_gr)[f_r1]; 705 FLD (i_sr) = & CPU (h_gr)[f_r2]; 706 FLD (i_dr) = & CPU (h_gr)[f_r1]; 738 FLD (i_sr) = & CPU (h_gr)[f_r2]; 739 FLD (i_dr) = & CPU (h_gr)[f_r1]; 768 FLD (i_dr) = & CPU (h_gr)[f_r1]; 797 FLD (i_dr) = & CPU (h_gr)[f_r [all...]
H A D	decodex.c	600 FLD (i_dr) = & CPU (h_gr)[f_r1]; 601 FLD (i_sr) = & CPU (h_gr)[f_r2]; 634 FLD (i_sr) = & CPU (h_gr)[f_r2]; 635 FLD (i_dr) = & CPU (h_gr)[f_r1]; 667 FLD (i_sr) = & CPU (h_gr)[f_r2]; 668 FLD (i_dr) = & CPU (h_gr)[f_r1]; 700 FLD (i_sr) = & CPU (h_gr)[f_r2]; 701 FLD (i_dr) = & CPU (h_gr)[f_r1]; 730 FLD (i_dr) = & CPU (h_gr)[f_r1]; 759 FLD (i_dr) = & CPU (h_gr)[f_r [all...]
H A D	m32r.c	143 return CPU (h_gr[H_GR_SP]); 148 return CPU (h_gr[H_GR_SP]); 181 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); 182 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); 187 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); 188 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); 201 CPU (h_gr[H_GR_SP]) = newval; 207 CPU (h_gr[H_GR_SP]) = newval; 328 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; 331 && (h_gr 326 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; local [all...]
H A D	decode.c	500 FLD (i_dr) = & CPU (h_gr)[f_r1]; 501 FLD (i_sr) = & CPU (h_gr)[f_r2]; 534 FLD (i_sr) = & CPU (h_gr)[f_r2]; 535 FLD (i_dr) = & CPU (h_gr)[f_r1]; 567 FLD (i_sr) = & CPU (h_gr)[f_r2]; 568 FLD (i_dr) = & CPU (h_gr)[f_r1]; 600 FLD (i_sr) = & CPU (h_gr)[f_r2]; 601 FLD (i_dr) = & CPU (h_gr)[f_r1]; 630 FLD (i_dr) = & CPU (h_gr)[f_r1]; 659 FLD (i_dr) = & CPU (h_gr)[f_r [all...]
H A D	cpu.c	51 return CPU (h_gr[regno]); 59 CPU (h_gr[regno]) = newval;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/m32r/
H A D	m32r2.c	62 return CPU (h_gr[H_GR_SP]); 67 return CPU (h_gr[H_GR_SP]); 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); 101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); 106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); 120 CPU (h_gr[H_GR_SP]) = newval; 126 CPU (h_gr[H_GR_SP]) = newval; 235 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; 238 && (h_gr 233 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; local [all...]
H A D	m32rx.c	62 return CPU (h_gr[H_GR_SP]); 67 return CPU (h_gr[H_GR_SP]); 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); 101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); 106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); 120 CPU (h_gr[H_GR_SP]) = newval; 126 CPU (h_gr[H_GR_SP]) = newval; 235 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; 238 && (h_gr 233 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; local [all...]
H A D	decode2.c	638 FLD (i_dr) = & CPU (h_gr)[f_r1]; 639 FLD (i_sr) = & CPU (h_gr)[f_r2]; 672 FLD (i_sr) = & CPU (h_gr)[f_r2]; 673 FLD (i_dr) = & CPU (h_gr)[f_r1]; 705 FLD (i_sr) = & CPU (h_gr)[f_r2]; 706 FLD (i_dr) = & CPU (h_gr)[f_r1]; 738 FLD (i_sr) = & CPU (h_gr)[f_r2]; 739 FLD (i_dr) = & CPU (h_gr)[f_r1]; 768 FLD (i_dr) = & CPU (h_gr)[f_r1]; 797 FLD (i_dr) = & CPU (h_gr)[f_r [all...]
H A D	decodex.c	600 FLD (i_dr) = & CPU (h_gr)[f_r1]; 601 FLD (i_sr) = & CPU (h_gr)[f_r2]; 634 FLD (i_sr) = & CPU (h_gr)[f_r2]; 635 FLD (i_dr) = & CPU (h_gr)[f_r1]; 667 FLD (i_sr) = & CPU (h_gr)[f_r2]; 668 FLD (i_dr) = & CPU (h_gr)[f_r1]; 700 FLD (i_sr) = & CPU (h_gr)[f_r2]; 701 FLD (i_dr) = & CPU (h_gr)[f_r1]; 730 FLD (i_dr) = & CPU (h_gr)[f_r1]; 759 FLD (i_dr) = & CPU (h_gr)[f_r [all...]
H A D	m32r.c	143 return CPU (h_gr[H_GR_SP]); 148 return CPU (h_gr[H_GR_SP]); 181 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); 182 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); 187 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); 188 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); 201 CPU (h_gr[H_GR_SP]) = newval; 207 CPU (h_gr[H_GR_SP]) = newval; 328 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; 331 && (h_gr 326 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; local [all...]
H A D	decode.c	500 FLD (i_dr) = & CPU (h_gr)[f_r1]; 501 FLD (i_sr) = & CPU (h_gr)[f_r2]; 534 FLD (i_sr) = & CPU (h_gr)[f_r2]; 535 FLD (i_dr) = & CPU (h_gr)[f_r1]; 567 FLD (i_sr) = & CPU (h_gr)[f_r2]; 568 FLD (i_dr) = & CPU (h_gr)[f_r1]; 600 FLD (i_sr) = & CPU (h_gr)[f_r2]; 601 FLD (i_dr) = & CPU (h_gr)[f_r1]; 630 FLD (i_dr) = & CPU (h_gr)[f_r1]; 659 FLD (i_dr) = & CPU (h_gr)[f_r [all...]

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Indexes created Sun Jun 30 11:05:36 MDT 2024