1/* Simulator instruction decoder for m32r2f. 2 3THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. 6 7This file is part of the GNU simulators. 8 9This program is free software; you can redistribute it and/or modify 10it under the terms of the GNU General Public License as published by 11the Free Software Foundation; either version 3 of the License, or 12(at your option) any later version. 13 14This program is distributed in the hope that it will be useful, 15but WITHOUT ANY WARRANTY; without even the implied warranty of 16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17GNU General Public License for more details. 18 19You should have received a copy of the GNU General Public License 20along with this program. If not, see <http://www.gnu.org/licenses/>. 21 22*/ 23 24#define WANT_CPU m32r2f 25#define WANT_CPU_M32R2F 26 27#include "sim-main.h" 28#include "sim-assert.h" 29 30/* Insn can't be executed in parallel. 31 Or is that "do NOt Pass to Air defense Radar"? :-) */ 32#define NOPAR (-1) 33 34/* The instruction descriptor array. 35 This is computed at runtime. Space for it is not malloc'd to save a 36 teensy bit of cpu in the decoder. Moving it to malloc space is trivial 37 but won't be done until necessary (we don't currently support the runtime 38 addition of instructions nor an SMP machine with different cpus). */ 39static IDESC m32r2f_insn_data[M32R2F_INSN__MAX]; 40 41/* Commas between elements are contained in the macros. 42 Some of these are conditionally compiled out. */ 43 44static const struct insn_sem m32r2f_insn_sem[] = 45{ 46 { VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, 47 { VIRTUAL_INSN_X_AFTER, M32R2F_INSN_X_AFTER, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, 48 { VIRTUAL_INSN_X_BEFORE, M32R2F_INSN_X_BEFORE, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, 49 { VIRTUAL_INSN_X_CTI_CHAIN, M32R2F_INSN_X_CTI_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, 50 { VIRTUAL_INSN_X_CHAIN, M32R2F_INSN_X_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, 51 { VIRTUAL_INSN_X_BEGIN, M32R2F_INSN_X_BEGIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, 52 { M32R_INSN_ADD, M32R2F_INSN_ADD, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_ADD, M32R2F_INSN_WRITE_ADD }, 53 { M32R_INSN_ADD3, M32R2F_INSN_ADD3, M32R2F_SFMT_ADD3, NOPAR, NOPAR }, 54 { M32R_INSN_AND, M32R2F_INSN_AND, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND }, 55 { M32R_INSN_AND3, M32R2F_INSN_AND3, M32R2F_SFMT_AND3, NOPAR, NOPAR }, 56 { M32R_INSN_OR, M32R2F_INSN_OR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_OR, M32R2F_INSN_WRITE_OR }, 57 { M32R_INSN_OR3, M32R2F_INSN_OR3, M32R2F_SFMT_OR3, NOPAR, NOPAR }, 58 { M32R_INSN_XOR, M32R2F_INSN_XOR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_XOR, M32R2F_INSN_WRITE_XOR }, 59 { M32R_INSN_XOR3, M32R2F_INSN_XOR3, M32R2F_SFMT_AND3, NOPAR, NOPAR }, 60 { M32R_INSN_ADDI, M32R2F_INSN_ADDI, M32R2F_SFMT_ADDI, M32R2F_INSN_PAR_ADDI, M32R2F_INSN_WRITE_ADDI }, 61 { M32R_INSN_ADDV, M32R2F_INSN_ADDV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_ADDV, M32R2F_INSN_WRITE_ADDV }, 62 { M32R_INSN_ADDV3, M32R2F_INSN_ADDV3, M32R2F_SFMT_ADDV3, NOPAR, NOPAR }, 63 { M32R_INSN_ADDX, M32R2F_INSN_ADDX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_ADDX, M32R2F_INSN_WRITE_ADDX }, 64 { M32R_INSN_BC8, M32R2F_INSN_BC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BC8, M32R2F_INSN_WRITE_BC8 }, 65 { M32R_INSN_BC24, M32R2F_INSN_BC24, M32R2F_SFMT_BC24, NOPAR, NOPAR }, 66 { M32R_INSN_BEQ, M32R2F_INSN_BEQ, M32R2F_SFMT_BEQ, NOPAR, NOPAR }, 67 { M32R_INSN_BEQZ, M32R2F_INSN_BEQZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, 68 { M32R_INSN_BGEZ, M32R2F_INSN_BGEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, 69 { M32R_INSN_BGTZ, M32R2F_INSN_BGTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, 70 { M32R_INSN_BLEZ, M32R2F_INSN_BLEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, 71 { M32R_INSN_BLTZ, M32R2F_INSN_BLTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, 72 { M32R_INSN_BNEZ, M32R2F_INSN_BNEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, 73 { M32R_INSN_BL8, M32R2F_INSN_BL8, M32R2F_SFMT_BL8, M32R2F_INSN_PAR_BL8, M32R2F_INSN_WRITE_BL8 }, 74 { M32R_INSN_BL24, M32R2F_INSN_BL24, M32R2F_SFMT_BL24, NOPAR, NOPAR }, 75 { M32R_INSN_BCL8, M32R2F_INSN_BCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_BCL8, M32R2F_INSN_WRITE_BCL8 }, 76 { M32R_INSN_BCL24, M32R2F_INSN_BCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR }, 77 { M32R_INSN_BNC8, M32R2F_INSN_BNC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BNC8, M32R2F_INSN_WRITE_BNC8 }, 78 { M32R_INSN_BNC24, M32R2F_INSN_BNC24, M32R2F_SFMT_BC24, NOPAR, NOPAR }, 79 { M32R_INSN_BNE, M32R2F_INSN_BNE, M32R2F_SFMT_BEQ, NOPAR, NOPAR }, 80 { M32R_INSN_BRA8, M32R2F_INSN_BRA8, M32R2F_SFMT_BRA8, M32R2F_INSN_PAR_BRA8, M32R2F_INSN_WRITE_BRA8 }, 81 { M32R_INSN_BRA24, M32R2F_INSN_BRA24, M32R2F_SFMT_BRA24, NOPAR, NOPAR }, 82 { M32R_INSN_BNCL8, M32R2F_INSN_BNCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_BNCL8, M32R2F_INSN_WRITE_BNCL8 }, 83 { M32R_INSN_BNCL24, M32R2F_INSN_BNCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR }, 84 { M32R_INSN_CMP, M32R2F_INSN_CMP, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMP, M32R2F_INSN_WRITE_CMP }, 85 { M32R_INSN_CMPI, M32R2F_INSN_CMPI, M32R2F_SFMT_CMPI, NOPAR, NOPAR }, 86 { M32R_INSN_CMPU, M32R2F_INSN_CMPU, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMPU, M32R2F_INSN_WRITE_CMPU }, 87 { M32R_INSN_CMPUI, M32R2F_INSN_CMPUI, M32R2F_SFMT_CMPI, NOPAR, NOPAR }, 88 { M32R_INSN_CMPEQ, M32R2F_INSN_CMPEQ, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMPEQ, M32R2F_INSN_WRITE_CMPEQ }, 89 { M32R_INSN_CMPZ, M32R2F_INSN_CMPZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR_CMPZ, M32R2F_INSN_WRITE_CMPZ }, 90 { M32R_INSN_DIV, M32R2F_INSN_DIV, M32R2F_SFMT_DIV, NOPAR, NOPAR }, 91 { M32R_INSN_DIVU, M32R2F_INSN_DIVU, M32R2F_SFMT_DIV, NOPAR, NOPAR }, 92 { M32R_INSN_REM, M32R2F_INSN_REM, M32R2F_SFMT_DIV, NOPAR, NOPAR }, 93 { M32R_INSN_REMU, M32R2F_INSN_REMU, M32R2F_SFMT_DIV, NOPAR, NOPAR }, 94 { M32R_INSN_REMH, M32R2F_INSN_REMH, M32R2F_SFMT_DIV, NOPAR, NOPAR }, 95 { M32R_INSN_REMUH, M32R2F_INSN_REMUH, M32R2F_SFMT_DIV, NOPAR, NOPAR }, 96 { M32R_INSN_REMB, M32R2F_INSN_REMB, M32R2F_SFMT_DIV, NOPAR, NOPAR }, 97 { M32R_INSN_REMUB, M32R2F_INSN_REMUB, M32R2F_SFMT_DIV, NOPAR, NOPAR }, 98 { M32R_INSN_DIVUH, M32R2F_INSN_DIVUH, M32R2F_SFMT_DIV, NOPAR, NOPAR }, 99 { M32R_INSN_DIVB, M32R2F_INSN_DIVB, M32R2F_SFMT_DIV, NOPAR, NOPAR }, 100 { M32R_INSN_DIVUB, M32R2F_INSN_DIVUB, M32R2F_SFMT_DIV, NOPAR, NOPAR }, 101 { M32R_INSN_DIVH, M32R2F_INSN_DIVH, M32R2F_SFMT_DIV, NOPAR, NOPAR }, 102 { M32R_INSN_JC, M32R2F_INSN_JC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JC, M32R2F_INSN_WRITE_JC }, 103 { M32R_INSN_JNC, M32R2F_INSN_JNC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JNC, M32R2F_INSN_WRITE_JNC }, 104 { M32R_INSN_JL, M32R2F_INSN_JL, M32R2F_SFMT_JL, M32R2F_INSN_PAR_JL, M32R2F_INSN_WRITE_JL }, 105 { M32R_INSN_JMP, M32R2F_INSN_JMP, M32R2F_SFMT_JMP, M32R2F_INSN_PAR_JMP, M32R2F_INSN_WRITE_JMP }, 106 { M32R_INSN_LD, M32R2F_INSN_LD, M32R2F_SFMT_LD, M32R2F_INSN_PAR_LD, M32R2F_INSN_WRITE_LD }, 107 { M32R_INSN_LD_D, M32R2F_INSN_LD_D, M32R2F_SFMT_LD_D, NOPAR, NOPAR }, 108 { M32R_INSN_LDB, M32R2F_INSN_LDB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDB, M32R2F_INSN_WRITE_LDB }, 109 { M32R_INSN_LDB_D, M32R2F_INSN_LDB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR }, 110 { M32R_INSN_LDH, M32R2F_INSN_LDH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDH, M32R2F_INSN_WRITE_LDH }, 111 { M32R_INSN_LDH_D, M32R2F_INSN_LDH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR }, 112 { M32R_INSN_LDUB, M32R2F_INSN_LDUB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDUB, M32R2F_INSN_WRITE_LDUB }, 113 { M32R_INSN_LDUB_D, M32R2F_INSN_LDUB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR }, 114 { M32R_INSN_LDUH, M32R2F_INSN_LDUH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDUH, M32R2F_INSN_WRITE_LDUH }, 115 { M32R_INSN_LDUH_D, M32R2F_INSN_LDUH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR }, 116 { M32R_INSN_LD_PLUS, M32R2F_INSN_LD_PLUS, M32R2F_SFMT_LD_PLUS, M32R2F_INSN_PAR_LD_PLUS, M32R2F_INSN_WRITE_LD_PLUS }, 117 { M32R_INSN_LD24, M32R2F_INSN_LD24, M32R2F_SFMT_LD24, NOPAR, NOPAR }, 118 { M32R_INSN_LDI8, M32R2F_INSN_LDI8, M32R2F_SFMT_LDI8, M32R2F_INSN_PAR_LDI8, M32R2F_INSN_WRITE_LDI8 }, 119 { M32R_INSN_LDI16, M32R2F_INSN_LDI16, M32R2F_SFMT_LDI16, NOPAR, NOPAR }, 120 { M32R_INSN_LOCK, M32R2F_INSN_LOCK, M32R2F_SFMT_LOCK, M32R2F_INSN_PAR_LOCK, M32R2F_INSN_WRITE_LOCK }, 121 { M32R_INSN_MACHI_A, M32R2F_INSN_MACHI_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACHI_A, M32R2F_INSN_WRITE_MACHI_A }, 122 { M32R_INSN_MACLO_A, M32R2F_INSN_MACLO_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACLO_A, M32R2F_INSN_WRITE_MACLO_A }, 123 { M32R_INSN_MACWHI_A, M32R2F_INSN_MACWHI_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACWHI_A, M32R2F_INSN_WRITE_MACWHI_A }, 124 { M32R_INSN_MACWLO_A, M32R2F_INSN_MACWLO_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACWLO_A, M32R2F_INSN_WRITE_MACWLO_A }, 125 { M32R_INSN_MUL, M32R2F_INSN_MUL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_MUL, M32R2F_INSN_WRITE_MUL }, 126 { M32R_INSN_MULHI_A, M32R2F_INSN_MULHI_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULHI_A, M32R2F_INSN_WRITE_MULHI_A }, 127 { M32R_INSN_MULLO_A, M32R2F_INSN_MULLO_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULLO_A, M32R2F_INSN_WRITE_MULLO_A }, 128 { M32R_INSN_MULWHI_A, M32R2F_INSN_MULWHI_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULWHI_A, M32R2F_INSN_WRITE_MULWHI_A }, 129 { M32R_INSN_MULWLO_A, M32R2F_INSN_MULWLO_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULWLO_A, M32R2F_INSN_WRITE_MULWLO_A }, 130 { M32R_INSN_MV, M32R2F_INSN_MV, M32R2F_SFMT_MV, M32R2F_INSN_PAR_MV, M32R2F_INSN_WRITE_MV }, 131 { M32R_INSN_MVFACHI_A, M32R2F_INSN_MVFACHI_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACHI_A, M32R2F_INSN_WRITE_MVFACHI_A }, 132 { M32R_INSN_MVFACLO_A, M32R2F_INSN_MVFACLO_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACLO_A, M32R2F_INSN_WRITE_MVFACLO_A }, 133 { M32R_INSN_MVFACMI_A, M32R2F_INSN_MVFACMI_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACMI_A, M32R2F_INSN_WRITE_MVFACMI_A }, 134 { M32R_INSN_MVFC, M32R2F_INSN_MVFC, M32R2F_SFMT_MVFC, M32R2F_INSN_PAR_MVFC, M32R2F_INSN_WRITE_MVFC }, 135 { M32R_INSN_MVTACHI_A, M32R2F_INSN_MVTACHI_A, M32R2F_SFMT_MVTACHI_A, M32R2F_INSN_PAR_MVTACHI_A, M32R2F_INSN_WRITE_MVTACHI_A }, 136 { M32R_INSN_MVTACLO_A, M32R2F_INSN_MVTACLO_A, M32R2F_SFMT_MVTACHI_A, M32R2F_INSN_PAR_MVTACLO_A, M32R2F_INSN_WRITE_MVTACLO_A }, 137 { M32R_INSN_MVTC, M32R2F_INSN_MVTC, M32R2F_SFMT_MVTC, M32R2F_INSN_PAR_MVTC, M32R2F_INSN_WRITE_MVTC }, 138 { M32R_INSN_NEG, M32R2F_INSN_NEG, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NEG, M32R2F_INSN_WRITE_NEG }, 139 { M32R_INSN_NOP, M32R2F_INSN_NOP, M32R2F_SFMT_NOP, M32R2F_INSN_PAR_NOP, M32R2F_INSN_WRITE_NOP }, 140 { M32R_INSN_NOT, M32R2F_INSN_NOT, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NOT, M32R2F_INSN_WRITE_NOT }, 141 { M32R_INSN_RAC_DSI, M32R2F_INSN_RAC_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_INSN_PAR_RAC_DSI, M32R2F_INSN_WRITE_RAC_DSI }, 142 { M32R_INSN_RACH_DSI, M32R2F_INSN_RACH_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_INSN_PAR_RACH_DSI, M32R2F_INSN_WRITE_RACH_DSI }, 143 { M32R_INSN_RTE, M32R2F_INSN_RTE, M32R2F_SFMT_RTE, M32R2F_INSN_PAR_RTE, M32R2F_INSN_WRITE_RTE }, 144 { M32R_INSN_SETH, M32R2F_INSN_SETH, M32R2F_SFMT_SETH, NOPAR, NOPAR }, 145 { M32R_INSN_SLL, M32R2F_INSN_SLL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SLL, M32R2F_INSN_WRITE_SLL }, 146 { M32R_INSN_SLL3, M32R2F_INSN_SLL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR }, 147 { M32R_INSN_SLLI, M32R2F_INSN_SLLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SLLI, M32R2F_INSN_WRITE_SLLI }, 148 { M32R_INSN_SRA, M32R2F_INSN_SRA, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRA, M32R2F_INSN_WRITE_SRA }, 149 { M32R_INSN_SRA3, M32R2F_INSN_SRA3, M32R2F_SFMT_SLL3, NOPAR, NOPAR }, 150 { M32R_INSN_SRAI, M32R2F_INSN_SRAI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRAI, M32R2F_INSN_WRITE_SRAI }, 151 { M32R_INSN_SRL, M32R2F_INSN_SRL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRL, M32R2F_INSN_WRITE_SRL }, 152 { M32R_INSN_SRL3, M32R2F_INSN_SRL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR }, 153 { M32R_INSN_SRLI, M32R2F_INSN_SRLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRLI, M32R2F_INSN_WRITE_SRLI }, 154 { M32R_INSN_ST, M32R2F_INSN_ST, M32R2F_SFMT_ST, M32R2F_INSN_PAR_ST, M32R2F_INSN_WRITE_ST }, 155 { M32R_INSN_ST_D, M32R2F_INSN_ST_D, M32R2F_SFMT_ST_D, NOPAR, NOPAR }, 156 { M32R_INSN_STB, M32R2F_INSN_STB, M32R2F_SFMT_STB, M32R2F_INSN_PAR_STB, M32R2F_INSN_WRITE_STB }, 157 { M32R_INSN_STB_D, M32R2F_INSN_STB_D, M32R2F_SFMT_STB_D, NOPAR, NOPAR }, 158 { M32R_INSN_STH, M32R2F_INSN_STH, M32R2F_SFMT_STH, M32R2F_INSN_PAR_STH, M32R2F_INSN_WRITE_STH }, 159 { M32R_INSN_STH_D, M32R2F_INSN_STH_D, M32R2F_SFMT_STH_D, NOPAR, NOPAR }, 160 { M32R_INSN_ST_PLUS, M32R2F_INSN_ST_PLUS, M32R2F_SFMT_ST_PLUS, M32R2F_INSN_PAR_ST_PLUS, M32R2F_INSN_WRITE_ST_PLUS }, 161 { M32R_INSN_STH_PLUS, M32R2F_INSN_STH_PLUS, M32R2F_SFMT_STH_PLUS, M32R2F_INSN_PAR_STH_PLUS, M32R2F_INSN_WRITE_STH_PLUS }, 162 { M32R_INSN_STB_PLUS, M32R2F_INSN_STB_PLUS, M32R2F_SFMT_STB_PLUS, M32R2F_INSN_PAR_STB_PLUS, M32R2F_INSN_WRITE_STB_PLUS }, 163 { M32R_INSN_ST_MINUS, M32R2F_INSN_ST_MINUS, M32R2F_SFMT_ST_PLUS, M32R2F_INSN_PAR_ST_MINUS, M32R2F_INSN_WRITE_ST_MINUS }, 164 { M32R_INSN_SUB, M32R2F_INSN_SUB, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SUB, M32R2F_INSN_WRITE_SUB }, 165 { M32R_INSN_SUBV, M32R2F_INSN_SUBV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_SUBV, M32R2F_INSN_WRITE_SUBV }, 166 { M32R_INSN_SUBX, M32R2F_INSN_SUBX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_SUBX, M32R2F_INSN_WRITE_SUBX }, 167 { M32R_INSN_TRAP, M32R2F_INSN_TRAP, M32R2F_SFMT_TRAP, M32R2F_INSN_PAR_TRAP, M32R2F_INSN_WRITE_TRAP }, 168 { M32R_INSN_UNLOCK, M32R2F_INSN_UNLOCK, M32R2F_SFMT_UNLOCK, M32R2F_INSN_PAR_UNLOCK, M32R2F_INSN_WRITE_UNLOCK }, 169 { M32R_INSN_SATB, M32R2F_INSN_SATB, M32R2F_SFMT_SATB, NOPAR, NOPAR }, 170 { M32R_INSN_SATH, M32R2F_INSN_SATH, M32R2F_SFMT_SATB, NOPAR, NOPAR }, 171 { M32R_INSN_SAT, M32R2F_INSN_SAT, M32R2F_SFMT_SAT, NOPAR, NOPAR }, 172 { M32R_INSN_PCMPBZ, M32R2F_INSN_PCMPBZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR_PCMPBZ, M32R2F_INSN_WRITE_PCMPBZ }, 173 { M32R_INSN_SADD, M32R2F_INSN_SADD, M32R2F_SFMT_SADD, M32R2F_INSN_PAR_SADD, M32R2F_INSN_WRITE_SADD }, 174 { M32R_INSN_MACWU1, M32R2F_INSN_MACWU1, M32R2F_SFMT_MACWU1, M32R2F_INSN_PAR_MACWU1, M32R2F_INSN_WRITE_MACWU1 }, 175 { M32R_INSN_MSBLO, M32R2F_INSN_MSBLO, M32R2F_SFMT_MSBLO, M32R2F_INSN_PAR_MSBLO, M32R2F_INSN_WRITE_MSBLO }, 176 { M32R_INSN_MULWU1, M32R2F_INSN_MULWU1, M32R2F_SFMT_MULWU1, M32R2F_INSN_PAR_MULWU1, M32R2F_INSN_WRITE_MULWU1 }, 177 { M32R_INSN_MACLH1, M32R2F_INSN_MACLH1, M32R2F_SFMT_MACWU1, M32R2F_INSN_PAR_MACLH1, M32R2F_INSN_WRITE_MACLH1 }, 178 { M32R_INSN_SC, M32R2F_INSN_SC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SC, M32R2F_INSN_WRITE_SC }, 179 { M32R_INSN_SNC, M32R2F_INSN_SNC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SNC, M32R2F_INSN_WRITE_SNC }, 180 { M32R_INSN_CLRPSW, M32R2F_INSN_CLRPSW, M32R2F_SFMT_CLRPSW, M32R2F_INSN_PAR_CLRPSW, M32R2F_INSN_WRITE_CLRPSW }, 181 { M32R_INSN_SETPSW, M32R2F_INSN_SETPSW, M32R2F_SFMT_SETPSW, M32R2F_INSN_PAR_SETPSW, M32R2F_INSN_WRITE_SETPSW }, 182 { M32R_INSN_BSET, M32R2F_INSN_BSET, M32R2F_SFMT_BSET, NOPAR, NOPAR }, 183 { M32R_INSN_BCLR, M32R2F_INSN_BCLR, M32R2F_SFMT_BSET, NOPAR, NOPAR }, 184 { M32R_INSN_BTST, M32R2F_INSN_BTST, M32R2F_SFMT_BTST, M32R2F_INSN_PAR_BTST, M32R2F_INSN_WRITE_BTST }, 185}; 186 187static const struct insn_sem m32r2f_insn_sem_invalid = { 188 VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR 189}; 190 191/* Initialize an IDESC from the compile-time computable parts. */ 192 193static INLINE void 194init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) 195{ 196 const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; 197 198 id->num = t->index; 199 id->sfmt = t->sfmt; 200 if ((int) t->type <= 0) 201 id->idata = & cgen_virtual_insn_table[- (int) t->type]; 202 else 203 id->idata = & insn_table[t->type]; 204 id->attrs = CGEN_INSN_ATTRS (id->idata); 205 /* Oh my god, a magic number. */ 206 id->length = CGEN_INSN_BITSIZE (id->idata) / 8; 207 208#if WITH_PROFILE_MODEL_P 209 id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; 210 { 211 SIM_DESC sd = CPU_STATE (cpu); 212 SIM_ASSERT (t->index == id->timing->num); 213 } 214#endif 215 216 /* Semantic pointers are initialized elsewhere. */ 217} 218 219/* Initialize the instruction descriptor table. */ 220 221void 222m32r2f_init_idesc_table (SIM_CPU *cpu) 223{ 224 IDESC *id,*tabend; 225 const struct insn_sem *t,*tend; 226 int tabsize = M32R2F_INSN__MAX; 227 IDESC *table = m32r2f_insn_data; 228 229 memset (table, 0, tabsize * sizeof (IDESC)); 230 231 /* First set all entries to the `invalid insn'. */ 232 t = & m32r2f_insn_sem_invalid; 233 for (id = table, tabend = table + tabsize; id < tabend; ++id) 234 init_idesc (cpu, id, t); 235 236 /* Now fill in the values for the chosen cpu. */ 237 for (t = m32r2f_insn_sem, tend = t + sizeof (m32r2f_insn_sem) / sizeof (*t); 238 t != tend; ++t) 239 { 240 init_idesc (cpu, & table[t->index], t); 241 if (t->par_index != NOPAR) 242 { 243 init_idesc (cpu, &table[t->par_index], t); 244 table[t->index].par_idesc = &table[t->par_index]; 245 } 246 if (t->par_index != NOPAR) 247 { 248 init_idesc (cpu, &table[t->write_index], t); 249 table[t->par_index].par_idesc = &table[t->write_index]; 250 } 251 } 252 253 /* Link the IDESC table into the cpu. */ 254 CPU_IDESC (cpu) = table; 255} 256 257/* Given an instruction, return a pointer to its IDESC entry. */ 258 259const IDESC * 260m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, 261 CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, 262 ARGBUF *abuf) 263{ 264 /* Result of decoder. */ 265 M32R2F_INSN_TYPE itype; 266 267 { 268 CGEN_INSN_INT insn = base_insn; 269 270 { 271 unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); 272 switch (val) 273 { 274 case 0 : itype = M32R2F_INSN_SUBV; goto extract_sfmt_addv; 275 case 1 : itype = M32R2F_INSN_SUBX; goto extract_sfmt_addx; 276 case 2 : itype = M32R2F_INSN_SUB; goto extract_sfmt_add; 277 case 3 : itype = M32R2F_INSN_NEG; goto extract_sfmt_mv; 278 case 4 : itype = M32R2F_INSN_CMP; goto extract_sfmt_cmp; 279 case 5 : itype = M32R2F_INSN_CMPU; goto extract_sfmt_cmp; 280 case 6 : itype = M32R2F_INSN_CMPEQ; goto extract_sfmt_cmp; 281 case 7 : 282 { 283 unsigned int val = (((insn >> 8) & (3 << 0))); 284 switch (val) 285 { 286 case 0 : itype = M32R2F_INSN_CMPZ; goto extract_sfmt_cmpz; 287 case 3 : itype = M32R2F_INSN_PCMPBZ; goto extract_sfmt_cmpz; 288 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; 289 } 290 } 291 case 8 : itype = M32R2F_INSN_ADDV; goto extract_sfmt_addv; 292 case 9 : itype = M32R2F_INSN_ADDX; goto extract_sfmt_addx; 293 case 10 : itype = M32R2F_INSN_ADD; goto extract_sfmt_add; 294 case 11 : itype = M32R2F_INSN_NOT; goto extract_sfmt_mv; 295 case 12 : itype = M32R2F_INSN_AND; goto extract_sfmt_add; 296 case 13 : itype = M32R2F_INSN_XOR; goto extract_sfmt_add; 297 case 14 : itype = M32R2F_INSN_OR; goto extract_sfmt_add; 298 case 15 : itype = M32R2F_INSN_BTST; goto extract_sfmt_btst; 299 case 16 : itype = M32R2F_INSN_SRL; goto extract_sfmt_add; 300 case 18 : itype = M32R2F_INSN_SRA; goto extract_sfmt_add; 301 case 20 : itype = M32R2F_INSN_SLL; goto extract_sfmt_add; 302 case 22 : itype = M32R2F_INSN_MUL; goto extract_sfmt_add; 303 case 24 : itype = M32R2F_INSN_MV; goto extract_sfmt_mv; 304 case 25 : itype = M32R2F_INSN_MVFC; goto extract_sfmt_mvfc; 305 case 26 : itype = M32R2F_INSN_MVTC; goto extract_sfmt_mvtc; 306 case 28 : 307 { 308 unsigned int val = (((insn >> 8) & (3 << 0))); 309 switch (val) 310 { 311 case 0 : itype = M32R2F_INSN_JC; goto extract_sfmt_jc; 312 case 1 : itype = M32R2F_INSN_JNC; goto extract_sfmt_jc; 313 case 2 : itype = M32R2F_INSN_JL; goto extract_sfmt_jl; 314 case 3 : itype = M32R2F_INSN_JMP; goto extract_sfmt_jmp; 315 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; 316 } 317 } 318 case 29 : itype = M32R2F_INSN_RTE; goto extract_sfmt_rte; 319 case 31 : itype = M32R2F_INSN_TRAP; goto extract_sfmt_trap; 320 case 32 : itype = M32R2F_INSN_STB; goto extract_sfmt_stb; 321 case 33 : itype = M32R2F_INSN_STB_PLUS; goto extract_sfmt_stb_plus; 322 case 34 : itype = M32R2F_INSN_STH; goto extract_sfmt_sth; 323 case 35 : itype = M32R2F_INSN_STH_PLUS; goto extract_sfmt_sth_plus; 324 case 36 : itype = M32R2F_INSN_ST; goto extract_sfmt_st; 325 case 37 : itype = M32R2F_INSN_UNLOCK; goto extract_sfmt_unlock; 326 case 38 : itype = M32R2F_INSN_ST_PLUS; goto extract_sfmt_st_plus; 327 case 39 : itype = M32R2F_INSN_ST_MINUS; goto extract_sfmt_st_plus; 328 case 40 : itype = M32R2F_INSN_LDB; goto extract_sfmt_ldb; 329 case 41 : itype = M32R2F_INSN_LDUB; goto extract_sfmt_ldb; 330 case 42 : itype = M32R2F_INSN_LDH; goto extract_sfmt_ldh; 331 case 43 : itype = M32R2F_INSN_LDUH; goto extract_sfmt_ldh; 332 case 44 : itype = M32R2F_INSN_LD; goto extract_sfmt_ld; 333 case 45 : itype = M32R2F_INSN_LOCK; goto extract_sfmt_lock; 334 case 46 : itype = M32R2F_INSN_LD_PLUS; goto extract_sfmt_ld_plus; 335 case 48 : /* fall through */ 336 case 56 : itype = M32R2F_INSN_MULHI_A; goto extract_sfmt_mulhi_a; 337 case 49 : /* fall through */ 338 case 57 : itype = M32R2F_INSN_MULLO_A; goto extract_sfmt_mulhi_a; 339 case 50 : /* fall through */ 340 case 58 : itype = M32R2F_INSN_MULWHI_A; goto extract_sfmt_mulhi_a; 341 case 51 : /* fall through */ 342 case 59 : itype = M32R2F_INSN_MULWLO_A; goto extract_sfmt_mulhi_a; 343 case 52 : /* fall through */ 344 case 60 : itype = M32R2F_INSN_MACHI_A; goto extract_sfmt_machi_a; 345 case 53 : /* fall through */ 346 case 61 : itype = M32R2F_INSN_MACLO_A; goto extract_sfmt_machi_a; 347 case 54 : /* fall through */ 348 case 62 : itype = M32R2F_INSN_MACWHI_A; goto extract_sfmt_machi_a; 349 case 55 : /* fall through */ 350 case 63 : itype = M32R2F_INSN_MACWLO_A; goto extract_sfmt_machi_a; 351 case 64 : /* fall through */ 352 case 65 : /* fall through */ 353 case 66 : /* fall through */ 354 case 67 : /* fall through */ 355 case 68 : /* fall through */ 356 case 69 : /* fall through */ 357 case 70 : /* fall through */ 358 case 71 : /* fall through */ 359 case 72 : /* fall through */ 360 case 73 : /* fall through */ 361 case 74 : /* fall through */ 362 case 75 : /* fall through */ 363 case 76 : /* fall through */ 364 case 77 : /* fall through */ 365 case 78 : /* fall through */ 366 case 79 : itype = M32R2F_INSN_ADDI; goto extract_sfmt_addi; 367 case 80 : /* fall through */ 368 case 81 : itype = M32R2F_INSN_SRLI; goto extract_sfmt_slli; 369 case 82 : /* fall through */ 370 case 83 : itype = M32R2F_INSN_SRAI; goto extract_sfmt_slli; 371 case 84 : /* fall through */ 372 case 85 : itype = M32R2F_INSN_SLLI; goto extract_sfmt_slli; 373 case 87 : 374 { 375 unsigned int val = (((insn >> 0) & (1 << 0))); 376 switch (val) 377 { 378 case 0 : itype = M32R2F_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a; 379 case 1 : itype = M32R2F_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a; 380 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; 381 } 382 } 383 case 88 : itype = M32R2F_INSN_RACH_DSI; goto extract_sfmt_rac_dsi; 384 case 89 : itype = M32R2F_INSN_RAC_DSI; goto extract_sfmt_rac_dsi; 385 case 90 : itype = M32R2F_INSN_MULWU1; goto extract_sfmt_mulwu1; 386 case 91 : itype = M32R2F_INSN_MACWU1; goto extract_sfmt_macwu1; 387 case 92 : itype = M32R2F_INSN_MACLH1; goto extract_sfmt_macwu1; 388 case 93 : itype = M32R2F_INSN_MSBLO; goto extract_sfmt_msblo; 389 case 94 : itype = M32R2F_INSN_SADD; goto extract_sfmt_sadd; 390 case 95 : 391 { 392 unsigned int val = (((insn >> 0) & (3 << 0))); 393 switch (val) 394 { 395 case 0 : itype = M32R2F_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a; 396 case 1 : itype = M32R2F_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a; 397 case 2 : itype = M32R2F_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a; 398 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; 399 } 400 } 401 case 96 : /* fall through */ 402 case 97 : /* fall through */ 403 case 98 : /* fall through */ 404 case 99 : /* fall through */ 405 case 100 : /* fall through */ 406 case 101 : /* fall through */ 407 case 102 : /* fall through */ 408 case 103 : /* fall through */ 409 case 104 : /* fall through */ 410 case 105 : /* fall through */ 411 case 106 : /* fall through */ 412 case 107 : /* fall through */ 413 case 108 : /* fall through */ 414 case 109 : /* fall through */ 415 case 110 : /* fall through */ 416 case 111 : itype = M32R2F_INSN_LDI8; goto extract_sfmt_ldi8; 417 case 112 : 418 { 419 unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0))); 420 switch (val) 421 { 422 case 0 : itype = M32R2F_INSN_NOP; goto extract_sfmt_nop; 423 case 2 : /* fall through */ 424 case 3 : itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw; 425 case 4 : /* fall through */ 426 case 5 : itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw; 427 case 9 : itype = M32R2F_INSN_SC; goto extract_sfmt_sc; 428 case 11 : itype = M32R2F_INSN_SNC; goto extract_sfmt_sc; 429 case 16 : /* fall through */ 430 case 17 : itype = M32R2F_INSN_BCL8; goto extract_sfmt_bcl8; 431 case 18 : /* fall through */ 432 case 19 : itype = M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8; 433 case 24 : /* fall through */ 434 case 25 : itype = M32R2F_INSN_BC8; goto extract_sfmt_bc8; 435 case 26 : /* fall through */ 436 case 27 : itype = M32R2F_INSN_BNC8; goto extract_sfmt_bc8; 437 case 28 : /* fall through */ 438 case 29 : itype = M32R2F_INSN_BL8; goto extract_sfmt_bl8; 439 case 30 : /* fall through */ 440 case 31 : itype = M32R2F_INSN_BRA8; goto extract_sfmt_bra8; 441 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; 442 } 443 } 444 case 113 : /* fall through */ 445 case 114 : /* fall through */ 446 case 115 : /* fall through */ 447 case 116 : /* fall through */ 448 case 117 : /* fall through */ 449 case 118 : /* fall through */ 450 case 119 : /* fall through */ 451 case 120 : /* fall through */ 452 case 121 : /* fall through */ 453 case 122 : /* fall through */ 454 case 123 : /* fall through */ 455 case 124 : /* fall through */ 456 case 125 : /* fall through */ 457 case 126 : /* fall through */ 458 case 127 : 459 { 460 unsigned int val = (((insn >> 8) & (15 << 0))); 461 switch (val) 462 { 463 case 1 : itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw; 464 case 2 : itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw; 465 case 8 : itype = M32R2F_INSN_BCL8; goto extract_sfmt_bcl8; 466 case 9 : itype = M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8; 467 case 12 : itype = M32R2F_INSN_BC8; goto extract_sfmt_bc8; 468 case 13 : itype = M32R2F_INSN_BNC8; goto extract_sfmt_bc8; 469 case 14 : itype = M32R2F_INSN_BL8; goto extract_sfmt_bl8; 470 case 15 : itype = M32R2F_INSN_BRA8; goto extract_sfmt_bra8; 471 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; 472 } 473 } 474 case 132 : itype = M32R2F_INSN_CMPI; goto extract_sfmt_cmpi; 475 case 133 : itype = M32R2F_INSN_CMPUI; goto extract_sfmt_cmpi; 476 case 134 : 477 { 478 unsigned int val = (((insn >> -8) & (3 << 0))); 479 switch (val) 480 { 481 case 0 : itype = M32R2F_INSN_SAT; goto extract_sfmt_sat; 482 case 2 : itype = M32R2F_INSN_SATH; goto extract_sfmt_satb; 483 case 3 : itype = M32R2F_INSN_SATB; goto extract_sfmt_satb; 484 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; 485 } 486 } 487 case 136 : itype = M32R2F_INSN_ADDV3; goto extract_sfmt_addv3; 488 case 138 : itype = M32R2F_INSN_ADD3; goto extract_sfmt_add3; 489 case 140 : itype = M32R2F_INSN_AND3; goto extract_sfmt_and3; 490 case 141 : itype = M32R2F_INSN_XOR3; goto extract_sfmt_and3; 491 case 142 : itype = M32R2F_INSN_OR3; goto extract_sfmt_or3; 492 case 144 : 493 { 494 unsigned int val = (((insn >> -13) & (3 << 0))); 495 switch (val) 496 { 497 case 0 : itype = M32R2F_INSN_DIV; goto extract_sfmt_div; 498 case 2 : itype = M32R2F_INSN_DIVH; goto extract_sfmt_div; 499 case 3 : itype = M32R2F_INSN_DIVB; goto extract_sfmt_div; 500 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; 501 } 502 } 503 case 145 : 504 { 505 unsigned int val = (((insn >> -13) & (3 << 0))); 506 switch (val) 507 { 508 case 0 : itype = M32R2F_INSN_DIVU; goto extract_sfmt_div; 509 case 2 : itype = M32R2F_INSN_DIVUH; goto extract_sfmt_div; 510 case 3 : itype = M32R2F_INSN_DIVUB; goto extract_sfmt_div; 511 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; 512 } 513 } 514 case 146 : 515 { 516 unsigned int val = (((insn >> -13) & (3 << 0))); 517 switch (val) 518 { 519 case 0 : itype = M32R2F_INSN_REM; goto extract_sfmt_div; 520 case 2 : itype = M32R2F_INSN_REMH; goto extract_sfmt_div; 521 case 3 : itype = M32R2F_INSN_REMB; goto extract_sfmt_div; 522 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; 523 } 524 } 525 case 147 : 526 { 527 unsigned int val = (((insn >> -13) & (3 << 0))); 528 switch (val) 529 { 530 case 0 : itype = M32R2F_INSN_REMU; goto extract_sfmt_div; 531 case 2 : itype = M32R2F_INSN_REMUH; goto extract_sfmt_div; 532 case 3 : itype = M32R2F_INSN_REMUB; goto extract_sfmt_div; 533 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; 534 } 535 } 536 case 152 : itype = M32R2F_INSN_SRL3; goto extract_sfmt_sll3; 537 case 154 : itype = M32R2F_INSN_SRA3; goto extract_sfmt_sll3; 538 case 156 : itype = M32R2F_INSN_SLL3; goto extract_sfmt_sll3; 539 case 159 : itype = M32R2F_INSN_LDI16; goto extract_sfmt_ldi16; 540 case 160 : itype = M32R2F_INSN_STB_D; goto extract_sfmt_stb_d; 541 case 162 : itype = M32R2F_INSN_STH_D; goto extract_sfmt_sth_d; 542 case 164 : itype = M32R2F_INSN_ST_D; goto extract_sfmt_st_d; 543 case 166 : itype = M32R2F_INSN_BSET; goto extract_sfmt_bset; 544 case 167 : itype = M32R2F_INSN_BCLR; goto extract_sfmt_bset; 545 case 168 : itype = M32R2F_INSN_LDB_D; goto extract_sfmt_ldb_d; 546 case 169 : itype = M32R2F_INSN_LDUB_D; goto extract_sfmt_ldb_d; 547 case 170 : itype = M32R2F_INSN_LDH_D; goto extract_sfmt_ldh_d; 548 case 171 : itype = M32R2F_INSN_LDUH_D; goto extract_sfmt_ldh_d; 549 case 172 : itype = M32R2F_INSN_LD_D; goto extract_sfmt_ld_d; 550 case 176 : itype = M32R2F_INSN_BEQ; goto extract_sfmt_beq; 551 case 177 : itype = M32R2F_INSN_BNE; goto extract_sfmt_beq; 552 case 184 : itype = M32R2F_INSN_BEQZ; goto extract_sfmt_beqz; 553 case 185 : itype = M32R2F_INSN_BNEZ; goto extract_sfmt_beqz; 554 case 186 : itype = M32R2F_INSN_BLTZ; goto extract_sfmt_beqz; 555 case 187 : itype = M32R2F_INSN_BGEZ; goto extract_sfmt_beqz; 556 case 188 : itype = M32R2F_INSN_BLEZ; goto extract_sfmt_beqz; 557 case 189 : itype = M32R2F_INSN_BGTZ; goto extract_sfmt_beqz; 558 case 220 : itype = M32R2F_INSN_SETH; goto extract_sfmt_seth; 559 case 224 : /* fall through */ 560 case 225 : /* fall through */ 561 case 226 : /* fall through */ 562 case 227 : /* fall through */ 563 case 228 : /* fall through */ 564 case 229 : /* fall through */ 565 case 230 : /* fall through */ 566 case 231 : /* fall through */ 567 case 232 : /* fall through */ 568 case 233 : /* fall through */ 569 case 234 : /* fall through */ 570 case 235 : /* fall through */ 571 case 236 : /* fall through */ 572 case 237 : /* fall through */ 573 case 238 : /* fall through */ 574 case 239 : itype = M32R2F_INSN_LD24; goto extract_sfmt_ld24; 575 case 240 : /* fall through */ 576 case 241 : /* fall through */ 577 case 242 : /* fall through */ 578 case 243 : /* fall through */ 579 case 244 : /* fall through */ 580 case 245 : /* fall through */ 581 case 246 : /* fall through */ 582 case 247 : /* fall through */ 583 case 248 : /* fall through */ 584 case 249 : /* fall through */ 585 case 250 : /* fall through */ 586 case 251 : /* fall through */ 587 case 252 : /* fall through */ 588 case 253 : /* fall through */ 589 case 254 : /* fall through */ 590 case 255 : 591 { 592 unsigned int val = (((insn >> 8) & (7 << 0))); 593 switch (val) 594 { 595 case 0 : itype = M32R2F_INSN_BCL24; goto extract_sfmt_bcl24; 596 case 1 : itype = M32R2F_INSN_BNCL24; goto extract_sfmt_bcl24; 597 case 4 : itype = M32R2F_INSN_BC24; goto extract_sfmt_bc24; 598 case 5 : itype = M32R2F_INSN_BNC24; goto extract_sfmt_bc24; 599 case 6 : itype = M32R2F_INSN_BL24; goto extract_sfmt_bl24; 600 case 7 : itype = M32R2F_INSN_BRA24; goto extract_sfmt_bra24; 601 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; 602 } 603 } 604 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; 605 } 606 } 607 } 608 609 /* The instruction has been decoded, now extract the fields. */ 610 611 extract_sfmt_empty: 612 { 613 const IDESC *idesc = &m32r2f_insn_data[itype]; 614#define FLD(f) abuf->fields.fmt_empty.f 615 616 617 /* Record the fields for the semantic handler. */ 618 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); 619 620#undef FLD 621 return idesc; 622 } 623 624 extract_sfmt_add: 625 { 626 const IDESC *idesc = &m32r2f_insn_data[itype]; 627 CGEN_INSN_INT insn = entire_insn; 628#define FLD(f) abuf->fields.sfmt_add.f 629 UINT f_r1; 630 UINT f_r2; 631 632 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 633 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 634 635 /* Record the fields for the semantic handler. */ 636 FLD (f_r1) = f_r1; 637 FLD (f_r2) = f_r2; 638 FLD (i_dr) = & CPU (h_gr)[f_r1]; 639 FLD (i_sr) = & CPU (h_gr)[f_r2]; 640 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 641 642#if WITH_PROFILE_MODEL_P 643 /* Record the fields for profiling. */ 644 if (PROFILE_MODEL_P (current_cpu)) 645 { 646 FLD (in_dr) = f_r1; 647 FLD (in_sr) = f_r2; 648 FLD (out_dr) = f_r1; 649 } 650#endif 651#undef FLD 652 return idesc; 653 } 654 655 extract_sfmt_add3: 656 { 657 const IDESC *idesc = &m32r2f_insn_data[itype]; 658 CGEN_INSN_INT insn = entire_insn; 659#define FLD(f) abuf->fields.sfmt_add3.f 660 UINT f_r1; 661 UINT f_r2; 662 INT f_simm16; 663 664 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 665 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 666 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); 667 668 /* Record the fields for the semantic handler. */ 669 FLD (f_simm16) = f_simm16; 670 FLD (f_r2) = f_r2; 671 FLD (f_r1) = f_r1; 672 FLD (i_sr) = & CPU (h_gr)[f_r2]; 673 FLD (i_dr) = & CPU (h_gr)[f_r1]; 674 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 675 676#if WITH_PROFILE_MODEL_P 677 /* Record the fields for profiling. */ 678 if (PROFILE_MODEL_P (current_cpu)) 679 { 680 FLD (in_sr) = f_r2; 681 FLD (out_dr) = f_r1; 682 } 683#endif 684#undef FLD 685 return idesc; 686 } 687 688 extract_sfmt_and3: 689 { 690 const IDESC *idesc = &m32r2f_insn_data[itype]; 691 CGEN_INSN_INT insn = entire_insn; 692#define FLD(f) abuf->fields.sfmt_and3.f 693 UINT f_r1; 694 UINT f_r2; 695 UINT f_uimm16; 696 697 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 698 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 699 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); 700 701 /* Record the fields for the semantic handler. */ 702 FLD (f_r2) = f_r2; 703 FLD (f_uimm16) = f_uimm16; 704 FLD (f_r1) = f_r1; 705 FLD (i_sr) = & CPU (h_gr)[f_r2]; 706 FLD (i_dr) = & CPU (h_gr)[f_r1]; 707 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 708 709#if WITH_PROFILE_MODEL_P 710 /* Record the fields for profiling. */ 711 if (PROFILE_MODEL_P (current_cpu)) 712 { 713 FLD (in_sr) = f_r2; 714 FLD (out_dr) = f_r1; 715 } 716#endif 717#undef FLD 718 return idesc; 719 } 720 721 extract_sfmt_or3: 722 { 723 const IDESC *idesc = &m32r2f_insn_data[itype]; 724 CGEN_INSN_INT insn = entire_insn; 725#define FLD(f) abuf->fields.sfmt_and3.f 726 UINT f_r1; 727 UINT f_r2; 728 UINT f_uimm16; 729 730 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 731 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 732 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); 733 734 /* Record the fields for the semantic handler. */ 735 FLD (f_r2) = f_r2; 736 FLD (f_uimm16) = f_uimm16; 737 FLD (f_r1) = f_r1; 738 FLD (i_sr) = & CPU (h_gr)[f_r2]; 739 FLD (i_dr) = & CPU (h_gr)[f_r1]; 740 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 741 742#if WITH_PROFILE_MODEL_P 743 /* Record the fields for profiling. */ 744 if (PROFILE_MODEL_P (current_cpu)) 745 { 746 FLD (in_sr) = f_r2; 747 FLD (out_dr) = f_r1; 748 } 749#endif 750#undef FLD 751 return idesc; 752 } 753 754 extract_sfmt_addi: 755 { 756 const IDESC *idesc = &m32r2f_insn_data[itype]; 757 CGEN_INSN_INT insn = entire_insn; 758#define FLD(f) abuf->fields.sfmt_addi.f 759 UINT f_r1; 760 INT f_simm8; 761 762 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 763 f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); 764 765 /* Record the fields for the semantic handler. */ 766 FLD (f_r1) = f_r1; 767 FLD (f_simm8) = f_simm8; 768 FLD (i_dr) = & CPU (h_gr)[f_r1]; 769 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0)); 770 771#if WITH_PROFILE_MODEL_P 772 /* Record the fields for profiling. */ 773 if (PROFILE_MODEL_P (current_cpu)) 774 { 775 FLD (in_dr) = f_r1; 776 FLD (out_dr) = f_r1; 777 } 778#endif 779#undef FLD 780 return idesc; 781 } 782 783 extract_sfmt_addv: 784 { 785 const IDESC *idesc = &m32r2f_insn_data[itype]; 786 CGEN_INSN_INT insn = entire_insn; 787#define FLD(f) abuf->fields.sfmt_add.f 788 UINT f_r1; 789 UINT f_r2; 790 791 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 792 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 793 794 /* Record the fields for the semantic handler. */ 795 FLD (f_r1) = f_r1; 796 FLD (f_r2) = f_r2; 797 FLD (i_dr) = & CPU (h_gr)[f_r1]; 798 FLD (i_sr) = & CPU (h_gr)[f_r2]; 799 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 800 801#if WITH_PROFILE_MODEL_P 802 /* Record the fields for profiling. */ 803 if (PROFILE_MODEL_P (current_cpu)) 804 { 805 FLD (in_dr) = f_r1; 806 FLD (in_sr) = f_r2; 807 FLD (out_dr) = f_r1; 808 } 809#endif 810#undef FLD 811 return idesc; 812 } 813 814 extract_sfmt_addv3: 815 { 816 const IDESC *idesc = &m32r2f_insn_data[itype]; 817 CGEN_INSN_INT insn = entire_insn; 818#define FLD(f) abuf->fields.sfmt_add3.f 819 UINT f_r1; 820 UINT f_r2; 821 INT f_simm16; 822 823 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 824 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 825 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); 826 827 /* Record the fields for the semantic handler. */ 828 FLD (f_simm16) = f_simm16; 829 FLD (f_r2) = f_r2; 830 FLD (f_r1) = f_r1; 831 FLD (i_sr) = & CPU (h_gr)[f_r2]; 832 FLD (i_dr) = & CPU (h_gr)[f_r1]; 833 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 834 835#if WITH_PROFILE_MODEL_P 836 /* Record the fields for profiling. */ 837 if (PROFILE_MODEL_P (current_cpu)) 838 { 839 FLD (in_sr) = f_r2; 840 FLD (out_dr) = f_r1; 841 } 842#endif 843#undef FLD 844 return idesc; 845 } 846 847 extract_sfmt_addx: 848 { 849 const IDESC *idesc = &m32r2f_insn_data[itype]; 850 CGEN_INSN_INT insn = entire_insn; 851#define FLD(f) abuf->fields.sfmt_add.f 852 UINT f_r1; 853 UINT f_r2; 854 855 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 856 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 857 858 /* Record the fields for the semantic handler. */ 859 FLD (f_r1) = f_r1; 860 FLD (f_r2) = f_r2; 861 FLD (i_dr) = & CPU (h_gr)[f_r1]; 862 FLD (i_sr) = & CPU (h_gr)[f_r2]; 863 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 864 865#if WITH_PROFILE_MODEL_P 866 /* Record the fields for profiling. */ 867 if (PROFILE_MODEL_P (current_cpu)) 868 { 869 FLD (in_dr) = f_r1; 870 FLD (in_sr) = f_r2; 871 FLD (out_dr) = f_r1; 872 } 873#endif 874#undef FLD 875 return idesc; 876 } 877 878 extract_sfmt_bc8: 879 { 880 const IDESC *idesc = &m32r2f_insn_data[itype]; 881 CGEN_INSN_INT insn = entire_insn; 882#define FLD(f) abuf->fields.sfmt_bl8.f 883 SI f_disp8; 884 885 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); 886 887 /* Record the fields for the semantic handler. */ 888 FLD (i_disp8) = f_disp8; 889 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); 890 891#if WITH_PROFILE_MODEL_P 892 /* Record the fields for profiling. */ 893 if (PROFILE_MODEL_P (current_cpu)) 894 { 895 } 896#endif 897#undef FLD 898 return idesc; 899 } 900 901 extract_sfmt_bc24: 902 { 903 const IDESC *idesc = &m32r2f_insn_data[itype]; 904 CGEN_INSN_INT insn = entire_insn; 905#define FLD(f) abuf->fields.sfmt_bl24.f 906 SI f_disp24; 907 908 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); 909 910 /* Record the fields for the semantic handler. */ 911 FLD (i_disp24) = f_disp24; 912 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); 913 914#if WITH_PROFILE_MODEL_P 915 /* Record the fields for profiling. */ 916 if (PROFILE_MODEL_P (current_cpu)) 917 { 918 } 919#endif 920#undef FLD 921 return idesc; 922 } 923 924 extract_sfmt_beq: 925 { 926 const IDESC *idesc = &m32r2f_insn_data[itype]; 927 CGEN_INSN_INT insn = entire_insn; 928#define FLD(f) abuf->fields.sfmt_beq.f 929 UINT f_r1; 930 UINT f_r2; 931 SI f_disp16; 932 933 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 934 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 935 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); 936 937 /* Record the fields for the semantic handler. */ 938 FLD (f_r1) = f_r1; 939 FLD (f_r2) = f_r2; 940 FLD (i_disp16) = f_disp16; 941 FLD (i_src1) = & CPU (h_gr)[f_r1]; 942 FLD (i_src2) = & CPU (h_gr)[f_r2]; 943 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 944 945#if WITH_PROFILE_MODEL_P 946 /* Record the fields for profiling. */ 947 if (PROFILE_MODEL_P (current_cpu)) 948 { 949 FLD (in_src1) = f_r1; 950 FLD (in_src2) = f_r2; 951 } 952#endif 953#undef FLD 954 return idesc; 955 } 956 957 extract_sfmt_beqz: 958 { 959 const IDESC *idesc = &m32r2f_insn_data[itype]; 960 CGEN_INSN_INT insn = entire_insn; 961#define FLD(f) abuf->fields.sfmt_beq.f 962 UINT f_r2; 963 SI f_disp16; 964 965 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 966 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); 967 968 /* Record the fields for the semantic handler. */ 969 FLD (f_r2) = f_r2; 970 FLD (i_disp16) = f_disp16; 971 FLD (i_src2) = & CPU (h_gr)[f_r2]; 972 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0)); 973 974#if WITH_PROFILE_MODEL_P 975 /* Record the fields for profiling. */ 976 if (PROFILE_MODEL_P (current_cpu)) 977 { 978 FLD (in_src2) = f_r2; 979 } 980#endif 981#undef FLD 982 return idesc; 983 } 984 985 extract_sfmt_bl8: 986 { 987 const IDESC *idesc = &m32r2f_insn_data[itype]; 988 CGEN_INSN_INT insn = entire_insn; 989#define FLD(f) abuf->fields.sfmt_bl8.f 990 SI f_disp8; 991 992 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); 993 994 /* Record the fields for the semantic handler. */ 995 FLD (i_disp8) = f_disp8; 996 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); 997 998#if WITH_PROFILE_MODEL_P 999 /* Record the fields for profiling. */ 1000 if (PROFILE_MODEL_P (current_cpu)) 1001 { 1002 FLD (out_h_gr_SI_14) = 14; 1003 } 1004#endif 1005#undef FLD 1006 return idesc; 1007 } 1008 1009 extract_sfmt_bl24: 1010 { 1011 const IDESC *idesc = &m32r2f_insn_data[itype]; 1012 CGEN_INSN_INT insn = entire_insn; 1013#define FLD(f) abuf->fields.sfmt_bl24.f 1014 SI f_disp24; 1015 1016 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); 1017 1018 /* Record the fields for the semantic handler. */ 1019 FLD (i_disp24) = f_disp24; 1020 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); 1021 1022#if WITH_PROFILE_MODEL_P 1023 /* Record the fields for profiling. */ 1024 if (PROFILE_MODEL_P (current_cpu)) 1025 { 1026 FLD (out_h_gr_SI_14) = 14; 1027 } 1028#endif 1029#undef FLD 1030 return idesc; 1031 } 1032 1033 extract_sfmt_bcl8: 1034 { 1035 const IDESC *idesc = &m32r2f_insn_data[itype]; 1036 CGEN_INSN_INT insn = entire_insn; 1037#define FLD(f) abuf->fields.sfmt_bl8.f 1038 SI f_disp8; 1039 1040 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); 1041 1042 /* Record the fields for the semantic handler. */ 1043 FLD (i_disp8) = f_disp8; 1044 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); 1045 1046#if WITH_PROFILE_MODEL_P 1047 /* Record the fields for profiling. */ 1048 if (PROFILE_MODEL_P (current_cpu)) 1049 { 1050 FLD (out_h_gr_SI_14) = 14; 1051 } 1052#endif 1053#undef FLD 1054 return idesc; 1055 } 1056 1057 extract_sfmt_bcl24: 1058 { 1059 const IDESC *idesc = &m32r2f_insn_data[itype]; 1060 CGEN_INSN_INT insn = entire_insn; 1061#define FLD(f) abuf->fields.sfmt_bl24.f 1062 SI f_disp24; 1063 1064 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); 1065 1066 /* Record the fields for the semantic handler. */ 1067 FLD (i_disp24) = f_disp24; 1068 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); 1069 1070#if WITH_PROFILE_MODEL_P 1071 /* Record the fields for profiling. */ 1072 if (PROFILE_MODEL_P (current_cpu)) 1073 { 1074 FLD (out_h_gr_SI_14) = 14; 1075 } 1076#endif 1077#undef FLD 1078 return idesc; 1079 } 1080 1081 extract_sfmt_bra8: 1082 { 1083 const IDESC *idesc = &m32r2f_insn_data[itype]; 1084 CGEN_INSN_INT insn = entire_insn; 1085#define FLD(f) abuf->fields.sfmt_bl8.f 1086 SI f_disp8; 1087 1088 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); 1089 1090 /* Record the fields for the semantic handler. */ 1091 FLD (i_disp8) = f_disp8; 1092 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); 1093 1094#if WITH_PROFILE_MODEL_P 1095 /* Record the fields for profiling. */ 1096 if (PROFILE_MODEL_P (current_cpu)) 1097 { 1098 } 1099#endif 1100#undef FLD 1101 return idesc; 1102 } 1103 1104 extract_sfmt_bra24: 1105 { 1106 const IDESC *idesc = &m32r2f_insn_data[itype]; 1107 CGEN_INSN_INT insn = entire_insn; 1108#define FLD(f) abuf->fields.sfmt_bl24.f 1109 SI f_disp24; 1110 1111 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); 1112 1113 /* Record the fields for the semantic handler. */ 1114 FLD (i_disp24) = f_disp24; 1115 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); 1116 1117#if WITH_PROFILE_MODEL_P 1118 /* Record the fields for profiling. */ 1119 if (PROFILE_MODEL_P (current_cpu)) 1120 { 1121 } 1122#endif 1123#undef FLD 1124 return idesc; 1125 } 1126 1127 extract_sfmt_cmp: 1128 { 1129 const IDESC *idesc = &m32r2f_insn_data[itype]; 1130 CGEN_INSN_INT insn = entire_insn; 1131#define FLD(f) abuf->fields.sfmt_st_plus.f 1132 UINT f_r1; 1133 UINT f_r2; 1134 1135 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1136 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1137 1138 /* Record the fields for the semantic handler. */ 1139 FLD (f_r1) = f_r1; 1140 FLD (f_r2) = f_r2; 1141 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1142 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1143 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1144 1145#if WITH_PROFILE_MODEL_P 1146 /* Record the fields for profiling. */ 1147 if (PROFILE_MODEL_P (current_cpu)) 1148 { 1149 FLD (in_src1) = f_r1; 1150 FLD (in_src2) = f_r2; 1151 } 1152#endif 1153#undef FLD 1154 return idesc; 1155 } 1156 1157 extract_sfmt_cmpi: 1158 { 1159 const IDESC *idesc = &m32r2f_insn_data[itype]; 1160 CGEN_INSN_INT insn = entire_insn; 1161#define FLD(f) abuf->fields.sfmt_st_d.f 1162 UINT f_r2; 1163 INT f_simm16; 1164 1165 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1166 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); 1167 1168 /* Record the fields for the semantic handler. */ 1169 FLD (f_simm16) = f_simm16; 1170 FLD (f_r2) = f_r2; 1171 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1172 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); 1173 1174#if WITH_PROFILE_MODEL_P 1175 /* Record the fields for profiling. */ 1176 if (PROFILE_MODEL_P (current_cpu)) 1177 { 1178 FLD (in_src2) = f_r2; 1179 } 1180#endif 1181#undef FLD 1182 return idesc; 1183 } 1184 1185 extract_sfmt_cmpz: 1186 { 1187 const IDESC *idesc = &m32r2f_insn_data[itype]; 1188 CGEN_INSN_INT insn = entire_insn; 1189#define FLD(f) abuf->fields.sfmt_st_plus.f 1190 UINT f_r2; 1191 1192 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1193 1194 /* Record the fields for the semantic handler. */ 1195 FLD (f_r2) = f_r2; 1196 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1197 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); 1198 1199#if WITH_PROFILE_MODEL_P 1200 /* Record the fields for profiling. */ 1201 if (PROFILE_MODEL_P (current_cpu)) 1202 { 1203 FLD (in_src2) = f_r2; 1204 } 1205#endif 1206#undef FLD 1207 return idesc; 1208 } 1209 1210 extract_sfmt_div: 1211 { 1212 const IDESC *idesc = &m32r2f_insn_data[itype]; 1213 CGEN_INSN_INT insn = entire_insn; 1214#define FLD(f) abuf->fields.sfmt_add.f 1215 UINT f_r1; 1216 UINT f_r2; 1217 1218 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1219 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1220 1221 /* Record the fields for the semantic handler. */ 1222 FLD (f_r1) = f_r1; 1223 FLD (f_r2) = f_r2; 1224 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1225 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1226 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 1227 1228#if WITH_PROFILE_MODEL_P 1229 /* Record the fields for profiling. */ 1230 if (PROFILE_MODEL_P (current_cpu)) 1231 { 1232 FLD (in_dr) = f_r1; 1233 FLD (in_sr) = f_r2; 1234 FLD (out_dr) = f_r1; 1235 } 1236#endif 1237#undef FLD 1238 return idesc; 1239 } 1240 1241 extract_sfmt_jc: 1242 { 1243 const IDESC *idesc = &m32r2f_insn_data[itype]; 1244 CGEN_INSN_INT insn = entire_insn; 1245#define FLD(f) abuf->fields.sfmt_jl.f 1246 UINT f_r2; 1247 1248 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1249 1250 /* Record the fields for the semantic handler. */ 1251 FLD (f_r2) = f_r2; 1252 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1253 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); 1254 1255#if WITH_PROFILE_MODEL_P 1256 /* Record the fields for profiling. */ 1257 if (PROFILE_MODEL_P (current_cpu)) 1258 { 1259 FLD (in_sr) = f_r2; 1260 } 1261#endif 1262#undef FLD 1263 return idesc; 1264 } 1265 1266 extract_sfmt_jl: 1267 { 1268 const IDESC *idesc = &m32r2f_insn_data[itype]; 1269 CGEN_INSN_INT insn = entire_insn; 1270#define FLD(f) abuf->fields.sfmt_jl.f 1271 UINT f_r2; 1272 1273 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1274 1275 /* Record the fields for the semantic handler. */ 1276 FLD (f_r2) = f_r2; 1277 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1278 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); 1279 1280#if WITH_PROFILE_MODEL_P 1281 /* Record the fields for profiling. */ 1282 if (PROFILE_MODEL_P (current_cpu)) 1283 { 1284 FLD (in_sr) = f_r2; 1285 FLD (out_h_gr_SI_14) = 14; 1286 } 1287#endif 1288#undef FLD 1289 return idesc; 1290 } 1291 1292 extract_sfmt_jmp: 1293 { 1294 const IDESC *idesc = &m32r2f_insn_data[itype]; 1295 CGEN_INSN_INT insn = entire_insn; 1296#define FLD(f) abuf->fields.sfmt_jl.f 1297 UINT f_r2; 1298 1299 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1300 1301 /* Record the fields for the semantic handler. */ 1302 FLD (f_r2) = f_r2; 1303 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1304 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); 1305 1306#if WITH_PROFILE_MODEL_P 1307 /* Record the fields for profiling. */ 1308 if (PROFILE_MODEL_P (current_cpu)) 1309 { 1310 FLD (in_sr) = f_r2; 1311 } 1312#endif 1313#undef FLD 1314 return idesc; 1315 } 1316 1317 extract_sfmt_ld: 1318 { 1319 const IDESC *idesc = &m32r2f_insn_data[itype]; 1320 CGEN_INSN_INT insn = entire_insn; 1321#define FLD(f) abuf->fields.sfmt_ld_plus.f 1322 UINT f_r1; 1323 UINT f_r2; 1324 1325 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1326 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1327 1328 /* Record the fields for the semantic handler. */ 1329 FLD (f_r2) = f_r2; 1330 FLD (f_r1) = f_r1; 1331 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1332 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1333 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1334 1335#if WITH_PROFILE_MODEL_P 1336 /* Record the fields for profiling. */ 1337 if (PROFILE_MODEL_P (current_cpu)) 1338 { 1339 FLD (in_sr) = f_r2; 1340 FLD (out_dr) = f_r1; 1341 } 1342#endif 1343#undef FLD 1344 return idesc; 1345 } 1346 1347 extract_sfmt_ld_d: 1348 { 1349 const IDESC *idesc = &m32r2f_insn_data[itype]; 1350 CGEN_INSN_INT insn = entire_insn; 1351#define FLD(f) abuf->fields.sfmt_add3.f 1352 UINT f_r1; 1353 UINT f_r2; 1354 INT f_simm16; 1355 1356 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1357 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1358 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); 1359 1360 /* Record the fields for the semantic handler. */ 1361 FLD (f_simm16) = f_simm16; 1362 FLD (f_r2) = f_r2; 1363 FLD (f_r1) = f_r1; 1364 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1365 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1366 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1367 1368#if WITH_PROFILE_MODEL_P 1369 /* Record the fields for profiling. */ 1370 if (PROFILE_MODEL_P (current_cpu)) 1371 { 1372 FLD (in_sr) = f_r2; 1373 FLD (out_dr) = f_r1; 1374 } 1375#endif 1376#undef FLD 1377 return idesc; 1378 } 1379 1380 extract_sfmt_ldb: 1381 { 1382 const IDESC *idesc = &m32r2f_insn_data[itype]; 1383 CGEN_INSN_INT insn = entire_insn; 1384#define FLD(f) abuf->fields.sfmt_ld_plus.f 1385 UINT f_r1; 1386 UINT f_r2; 1387 1388 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1389 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1390 1391 /* Record the fields for the semantic handler. */ 1392 FLD (f_r2) = f_r2; 1393 FLD (f_r1) = f_r1; 1394 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1395 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1396 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1397 1398#if WITH_PROFILE_MODEL_P 1399 /* Record the fields for profiling. */ 1400 if (PROFILE_MODEL_P (current_cpu)) 1401 { 1402 FLD (in_sr) = f_r2; 1403 FLD (out_dr) = f_r1; 1404 } 1405#endif 1406#undef FLD 1407 return idesc; 1408 } 1409 1410 extract_sfmt_ldb_d: 1411 { 1412 const IDESC *idesc = &m32r2f_insn_data[itype]; 1413 CGEN_INSN_INT insn = entire_insn; 1414#define FLD(f) abuf->fields.sfmt_add3.f 1415 UINT f_r1; 1416 UINT f_r2; 1417 INT f_simm16; 1418 1419 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1420 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1421 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); 1422 1423 /* Record the fields for the semantic handler. */ 1424 FLD (f_simm16) = f_simm16; 1425 FLD (f_r2) = f_r2; 1426 FLD (f_r1) = f_r1; 1427 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1428 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1429 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1430 1431#if WITH_PROFILE_MODEL_P 1432 /* Record the fields for profiling. */ 1433 if (PROFILE_MODEL_P (current_cpu)) 1434 { 1435 FLD (in_sr) = f_r2; 1436 FLD (out_dr) = f_r1; 1437 } 1438#endif 1439#undef FLD 1440 return idesc; 1441 } 1442 1443 extract_sfmt_ldh: 1444 { 1445 const IDESC *idesc = &m32r2f_insn_data[itype]; 1446 CGEN_INSN_INT insn = entire_insn; 1447#define FLD(f) abuf->fields.sfmt_ld_plus.f 1448 UINT f_r1; 1449 UINT f_r2; 1450 1451 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1452 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1453 1454 /* Record the fields for the semantic handler. */ 1455 FLD (f_r2) = f_r2; 1456 FLD (f_r1) = f_r1; 1457 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1458 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1459 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1460 1461#if WITH_PROFILE_MODEL_P 1462 /* Record the fields for profiling. */ 1463 if (PROFILE_MODEL_P (current_cpu)) 1464 { 1465 FLD (in_sr) = f_r2; 1466 FLD (out_dr) = f_r1; 1467 } 1468#endif 1469#undef FLD 1470 return idesc; 1471 } 1472 1473 extract_sfmt_ldh_d: 1474 { 1475 const IDESC *idesc = &m32r2f_insn_data[itype]; 1476 CGEN_INSN_INT insn = entire_insn; 1477#define FLD(f) abuf->fields.sfmt_add3.f 1478 UINT f_r1; 1479 UINT f_r2; 1480 INT f_simm16; 1481 1482 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1483 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1484 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); 1485 1486 /* Record the fields for the semantic handler. */ 1487 FLD (f_simm16) = f_simm16; 1488 FLD (f_r2) = f_r2; 1489 FLD (f_r1) = f_r1; 1490 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1491 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1492 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1493 1494#if WITH_PROFILE_MODEL_P 1495 /* Record the fields for profiling. */ 1496 if (PROFILE_MODEL_P (current_cpu)) 1497 { 1498 FLD (in_sr) = f_r2; 1499 FLD (out_dr) = f_r1; 1500 } 1501#endif 1502#undef FLD 1503 return idesc; 1504 } 1505 1506 extract_sfmt_ld_plus: 1507 { 1508 const IDESC *idesc = &m32r2f_insn_data[itype]; 1509 CGEN_INSN_INT insn = entire_insn; 1510#define FLD(f) abuf->fields.sfmt_ld_plus.f 1511 UINT f_r1; 1512 UINT f_r2; 1513 1514 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1515 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1516 1517 /* Record the fields for the semantic handler. */ 1518 FLD (f_r2) = f_r2; 1519 FLD (f_r1) = f_r1; 1520 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1521 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1522 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1523 1524#if WITH_PROFILE_MODEL_P 1525 /* Record the fields for profiling. */ 1526 if (PROFILE_MODEL_P (current_cpu)) 1527 { 1528 FLD (in_sr) = f_r2; 1529 FLD (out_dr) = f_r1; 1530 FLD (out_sr) = f_r2; 1531 } 1532#endif 1533#undef FLD 1534 return idesc; 1535 } 1536 1537 extract_sfmt_ld24: 1538 { 1539 const IDESC *idesc = &m32r2f_insn_data[itype]; 1540 CGEN_INSN_INT insn = entire_insn; 1541#define FLD(f) abuf->fields.sfmt_ld24.f 1542 UINT f_r1; 1543 UINT f_uimm24; 1544 1545 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1546 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); 1547 1548 /* Record the fields for the semantic handler. */ 1549 FLD (f_r1) = f_r1; 1550 FLD (i_uimm24) = f_uimm24; 1551 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1552 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0)); 1553 1554#if WITH_PROFILE_MODEL_P 1555 /* Record the fields for profiling. */ 1556 if (PROFILE_MODEL_P (current_cpu)) 1557 { 1558 FLD (out_dr) = f_r1; 1559 } 1560#endif 1561#undef FLD 1562 return idesc; 1563 } 1564 1565 extract_sfmt_ldi8: 1566 { 1567 const IDESC *idesc = &m32r2f_insn_data[itype]; 1568 CGEN_INSN_INT insn = entire_insn; 1569#define FLD(f) abuf->fields.sfmt_addi.f 1570 UINT f_r1; 1571 INT f_simm8; 1572 1573 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1574 f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); 1575 1576 /* Record the fields for the semantic handler. */ 1577 FLD (f_simm8) = f_simm8; 1578 FLD (f_r1) = f_r1; 1579 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1580 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1581 1582#if WITH_PROFILE_MODEL_P 1583 /* Record the fields for profiling. */ 1584 if (PROFILE_MODEL_P (current_cpu)) 1585 { 1586 FLD (out_dr) = f_r1; 1587 } 1588#endif 1589#undef FLD 1590 return idesc; 1591 } 1592 1593 extract_sfmt_ldi16: 1594 { 1595 const IDESC *idesc = &m32r2f_insn_data[itype]; 1596 CGEN_INSN_INT insn = entire_insn; 1597#define FLD(f) abuf->fields.sfmt_add3.f 1598 UINT f_r1; 1599 INT f_simm16; 1600 1601 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1602 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); 1603 1604 /* Record the fields for the semantic handler. */ 1605 FLD (f_simm16) = f_simm16; 1606 FLD (f_r1) = f_r1; 1607 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1608 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1609 1610#if WITH_PROFILE_MODEL_P 1611 /* Record the fields for profiling. */ 1612 if (PROFILE_MODEL_P (current_cpu)) 1613 { 1614 FLD (out_dr) = f_r1; 1615 } 1616#endif 1617#undef FLD 1618 return idesc; 1619 } 1620 1621 extract_sfmt_lock: 1622 { 1623 const IDESC *idesc = &m32r2f_insn_data[itype]; 1624 CGEN_INSN_INT insn = entire_insn; 1625#define FLD(f) abuf->fields.sfmt_ld_plus.f 1626 UINT f_r1; 1627 UINT f_r2; 1628 1629 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1630 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1631 1632 /* Record the fields for the semantic handler. */ 1633 FLD (f_r2) = f_r2; 1634 FLD (f_r1) = f_r1; 1635 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1636 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1637 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1638 1639#if WITH_PROFILE_MODEL_P 1640 /* Record the fields for profiling. */ 1641 if (PROFILE_MODEL_P (current_cpu)) 1642 { 1643 FLD (in_sr) = f_r2; 1644 FLD (out_dr) = f_r1; 1645 } 1646#endif 1647#undef FLD 1648 return idesc; 1649 } 1650 1651 extract_sfmt_machi_a: 1652 { 1653 const IDESC *idesc = &m32r2f_insn_data[itype]; 1654 CGEN_INSN_INT insn = entire_insn; 1655#define FLD(f) abuf->fields.sfmt_machi_a.f 1656 UINT f_r1; 1657 UINT f_acc; 1658 UINT f_r2; 1659 1660 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1661 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); 1662 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1663 1664 /* Record the fields for the semantic handler. */ 1665 FLD (f_acc) = f_acc; 1666 FLD (f_r1) = f_r1; 1667 FLD (f_r2) = f_r2; 1668 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1669 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1670 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1671 1672#if WITH_PROFILE_MODEL_P 1673 /* Record the fields for profiling. */ 1674 if (PROFILE_MODEL_P (current_cpu)) 1675 { 1676 FLD (in_src1) = f_r1; 1677 FLD (in_src2) = f_r2; 1678 } 1679#endif 1680#undef FLD 1681 return idesc; 1682 } 1683 1684 extract_sfmt_mulhi_a: 1685 { 1686 const IDESC *idesc = &m32r2f_insn_data[itype]; 1687 CGEN_INSN_INT insn = entire_insn; 1688#define FLD(f) abuf->fields.sfmt_machi_a.f 1689 UINT f_r1; 1690 UINT f_acc; 1691 UINT f_r2; 1692 1693 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1694 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); 1695 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1696 1697 /* Record the fields for the semantic handler. */ 1698 FLD (f_r1) = f_r1; 1699 FLD (f_r2) = f_r2; 1700 FLD (f_acc) = f_acc; 1701 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1702 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1703 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1704 1705#if WITH_PROFILE_MODEL_P 1706 /* Record the fields for profiling. */ 1707 if (PROFILE_MODEL_P (current_cpu)) 1708 { 1709 FLD (in_src1) = f_r1; 1710 FLD (in_src2) = f_r2; 1711 } 1712#endif 1713#undef FLD 1714 return idesc; 1715 } 1716 1717 extract_sfmt_mv: 1718 { 1719 const IDESC *idesc = &m32r2f_insn_data[itype]; 1720 CGEN_INSN_INT insn = entire_insn; 1721#define FLD(f) abuf->fields.sfmt_ld_plus.f 1722 UINT f_r1; 1723 UINT f_r2; 1724 1725 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1726 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1727 1728 /* Record the fields for the semantic handler. */ 1729 FLD (f_r2) = f_r2; 1730 FLD (f_r1) = f_r1; 1731 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1732 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1733 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1734 1735#if WITH_PROFILE_MODEL_P 1736 /* Record the fields for profiling. */ 1737 if (PROFILE_MODEL_P (current_cpu)) 1738 { 1739 FLD (in_sr) = f_r2; 1740 FLD (out_dr) = f_r1; 1741 } 1742#endif 1743#undef FLD 1744 return idesc; 1745 } 1746 1747 extract_sfmt_mvfachi_a: 1748 { 1749 const IDESC *idesc = &m32r2f_insn_data[itype]; 1750 CGEN_INSN_INT insn = entire_insn; 1751#define FLD(f) abuf->fields.sfmt_mvfachi_a.f 1752 UINT f_r1; 1753 UINT f_accs; 1754 1755 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1756 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); 1757 1758 /* Record the fields for the semantic handler. */ 1759 FLD (f_accs) = f_accs; 1760 FLD (f_r1) = f_r1; 1761 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1762 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1763 1764#if WITH_PROFILE_MODEL_P 1765 /* Record the fields for profiling. */ 1766 if (PROFILE_MODEL_P (current_cpu)) 1767 { 1768 FLD (out_dr) = f_r1; 1769 } 1770#endif 1771#undef FLD 1772 return idesc; 1773 } 1774 1775 extract_sfmt_mvfc: 1776 { 1777 const IDESC *idesc = &m32r2f_insn_data[itype]; 1778 CGEN_INSN_INT insn = entire_insn; 1779#define FLD(f) abuf->fields.sfmt_ld_plus.f 1780 UINT f_r1; 1781 UINT f_r2; 1782 1783 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1784 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1785 1786 /* Record the fields for the semantic handler. */ 1787 FLD (f_r2) = f_r2; 1788 FLD (f_r1) = f_r1; 1789 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1790 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1791 1792#if WITH_PROFILE_MODEL_P 1793 /* Record the fields for profiling. */ 1794 if (PROFILE_MODEL_P (current_cpu)) 1795 { 1796 FLD (out_dr) = f_r1; 1797 } 1798#endif 1799#undef FLD 1800 return idesc; 1801 } 1802 1803 extract_sfmt_mvtachi_a: 1804 { 1805 const IDESC *idesc = &m32r2f_insn_data[itype]; 1806 CGEN_INSN_INT insn = entire_insn; 1807#define FLD(f) abuf->fields.sfmt_mvtachi_a.f 1808 UINT f_r1; 1809 UINT f_accs; 1810 1811 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1812 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); 1813 1814 /* Record the fields for the semantic handler. */ 1815 FLD (f_accs) = f_accs; 1816 FLD (f_r1) = f_r1; 1817 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1818 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0)); 1819 1820#if WITH_PROFILE_MODEL_P 1821 /* Record the fields for profiling. */ 1822 if (PROFILE_MODEL_P (current_cpu)) 1823 { 1824 FLD (in_src1) = f_r1; 1825 } 1826#endif 1827#undef FLD 1828 return idesc; 1829 } 1830 1831 extract_sfmt_mvtc: 1832 { 1833 const IDESC *idesc = &m32r2f_insn_data[itype]; 1834 CGEN_INSN_INT insn = entire_insn; 1835#define FLD(f) abuf->fields.sfmt_ld_plus.f 1836 UINT f_r1; 1837 UINT f_r2; 1838 1839 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1840 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1841 1842 /* Record the fields for the semantic handler. */ 1843 FLD (f_r2) = f_r2; 1844 FLD (f_r1) = f_r1; 1845 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1846 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 1847 1848#if WITH_PROFILE_MODEL_P 1849 /* Record the fields for profiling. */ 1850 if (PROFILE_MODEL_P (current_cpu)) 1851 { 1852 FLD (in_sr) = f_r2; 1853 } 1854#endif 1855#undef FLD 1856 return idesc; 1857 } 1858 1859 extract_sfmt_nop: 1860 { 1861 const IDESC *idesc = &m32r2f_insn_data[itype]; 1862#define FLD(f) abuf->fields.fmt_empty.f 1863 1864 1865 /* Record the fields for the semantic handler. */ 1866 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0)); 1867 1868#undef FLD 1869 return idesc; 1870 } 1871 1872 extract_sfmt_rac_dsi: 1873 { 1874 const IDESC *idesc = &m32r2f_insn_data[itype]; 1875 CGEN_INSN_INT insn = entire_insn; 1876#define FLD(f) abuf->fields.sfmt_rac_dsi.f 1877 UINT f_accd; 1878 UINT f_accs; 1879 SI f_imm1; 1880 1881 f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); 1882 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); 1883 f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); 1884 1885 /* Record the fields for the semantic handler. */ 1886 FLD (f_accs) = f_accs; 1887 FLD (f_imm1) = f_imm1; 1888 FLD (f_accd) = f_accd; 1889 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0)); 1890 1891#undef FLD 1892 return idesc; 1893 } 1894 1895 extract_sfmt_rte: 1896 { 1897 const IDESC *idesc = &m32r2f_insn_data[itype]; 1898#define FLD(f) abuf->fields.fmt_empty.f 1899 1900 1901 /* Record the fields for the semantic handler. */ 1902 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0)); 1903 1904#if WITH_PROFILE_MODEL_P 1905 /* Record the fields for profiling. */ 1906 if (PROFILE_MODEL_P (current_cpu)) 1907 { 1908 } 1909#endif 1910#undef FLD 1911 return idesc; 1912 } 1913 1914 extract_sfmt_seth: 1915 { 1916 const IDESC *idesc = &m32r2f_insn_data[itype]; 1917 CGEN_INSN_INT insn = entire_insn; 1918#define FLD(f) abuf->fields.sfmt_seth.f 1919 UINT f_r1; 1920 UINT f_hi16; 1921 1922 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1923 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); 1924 1925 /* Record the fields for the semantic handler. */ 1926 FLD (f_hi16) = f_hi16; 1927 FLD (f_r1) = f_r1; 1928 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1929 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1930 1931#if WITH_PROFILE_MODEL_P 1932 /* Record the fields for profiling. */ 1933 if (PROFILE_MODEL_P (current_cpu)) 1934 { 1935 FLD (out_dr) = f_r1; 1936 } 1937#endif 1938#undef FLD 1939 return idesc; 1940 } 1941 1942 extract_sfmt_sll3: 1943 { 1944 const IDESC *idesc = &m32r2f_insn_data[itype]; 1945 CGEN_INSN_INT insn = entire_insn; 1946#define FLD(f) abuf->fields.sfmt_add3.f 1947 UINT f_r1; 1948 UINT f_r2; 1949 INT f_simm16; 1950 1951 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1952 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1953 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); 1954 1955 /* Record the fields for the semantic handler. */ 1956 FLD (f_simm16) = f_simm16; 1957 FLD (f_r2) = f_r2; 1958 FLD (f_r1) = f_r1; 1959 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1960 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1961 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1962 1963#if WITH_PROFILE_MODEL_P 1964 /* Record the fields for profiling. */ 1965 if (PROFILE_MODEL_P (current_cpu)) 1966 { 1967 FLD (in_sr) = f_r2; 1968 FLD (out_dr) = f_r1; 1969 } 1970#endif 1971#undef FLD 1972 return idesc; 1973 } 1974 1975 extract_sfmt_slli: 1976 { 1977 const IDESC *idesc = &m32r2f_insn_data[itype]; 1978 CGEN_INSN_INT insn = entire_insn; 1979#define FLD(f) abuf->fields.sfmt_slli.f 1980 UINT f_r1; 1981 UINT f_uimm5; 1982 1983 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1984 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); 1985 1986 /* Record the fields for the semantic handler. */ 1987 FLD (f_r1) = f_r1; 1988 FLD (f_uimm5) = f_uimm5; 1989 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1990 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0)); 1991 1992#if WITH_PROFILE_MODEL_P 1993 /* Record the fields for profiling. */ 1994 if (PROFILE_MODEL_P (current_cpu)) 1995 { 1996 FLD (in_dr) = f_r1; 1997 FLD (out_dr) = f_r1; 1998 } 1999#endif 2000#undef FLD 2001 return idesc; 2002 } 2003 2004 extract_sfmt_st: 2005 { 2006 const IDESC *idesc = &m32r2f_insn_data[itype]; 2007 CGEN_INSN_INT insn = entire_insn; 2008#define FLD(f) abuf->fields.sfmt_st_plus.f 2009 UINT f_r1; 2010 UINT f_r2; 2011 2012 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2013 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2014 2015 /* Record the fields for the semantic handler. */ 2016 FLD (f_r1) = f_r1; 2017 FLD (f_r2) = f_r2; 2018 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2019 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2020 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2021 2022#if WITH_PROFILE_MODEL_P 2023 /* Record the fields for profiling. */ 2024 if (PROFILE_MODEL_P (current_cpu)) 2025 { 2026 FLD (in_src1) = f_r1; 2027 FLD (in_src2) = f_r2; 2028 } 2029#endif 2030#undef FLD 2031 return idesc; 2032 } 2033 2034 extract_sfmt_st_d: 2035 { 2036 const IDESC *idesc = &m32r2f_insn_data[itype]; 2037 CGEN_INSN_INT insn = entire_insn; 2038#define FLD(f) abuf->fields.sfmt_st_d.f 2039 UINT f_r1; 2040 UINT f_r2; 2041 INT f_simm16; 2042 2043 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2044 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2045 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); 2046 2047 /* Record the fields for the semantic handler. */ 2048 FLD (f_simm16) = f_simm16; 2049 FLD (f_r1) = f_r1; 2050 FLD (f_r2) = f_r2; 2051 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2052 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2053 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2054 2055#if WITH_PROFILE_MODEL_P 2056 /* Record the fields for profiling. */ 2057 if (PROFILE_MODEL_P (current_cpu)) 2058 { 2059 FLD (in_src1) = f_r1; 2060 FLD (in_src2) = f_r2; 2061 } 2062#endif 2063#undef FLD 2064 return idesc; 2065 } 2066 2067 extract_sfmt_stb: 2068 { 2069 const IDESC *idesc = &m32r2f_insn_data[itype]; 2070 CGEN_INSN_INT insn = entire_insn; 2071#define FLD(f) abuf->fields.sfmt_st_plus.f 2072 UINT f_r1; 2073 UINT f_r2; 2074 2075 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2076 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2077 2078 /* Record the fields for the semantic handler. */ 2079 FLD (f_r1) = f_r1; 2080 FLD (f_r2) = f_r2; 2081 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2082 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2083 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2084 2085#if WITH_PROFILE_MODEL_P 2086 /* Record the fields for profiling. */ 2087 if (PROFILE_MODEL_P (current_cpu)) 2088 { 2089 FLD (in_src1) = f_r1; 2090 FLD (in_src2) = f_r2; 2091 } 2092#endif 2093#undef FLD 2094 return idesc; 2095 } 2096 2097 extract_sfmt_stb_d: 2098 { 2099 const IDESC *idesc = &m32r2f_insn_data[itype]; 2100 CGEN_INSN_INT insn = entire_insn; 2101#define FLD(f) abuf->fields.sfmt_st_d.f 2102 UINT f_r1; 2103 UINT f_r2; 2104 INT f_simm16; 2105 2106 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2107 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2108 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); 2109 2110 /* Record the fields for the semantic handler. */ 2111 FLD (f_simm16) = f_simm16; 2112 FLD (f_r1) = f_r1; 2113 FLD (f_r2) = f_r2; 2114 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2115 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2116 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2117 2118#if WITH_PROFILE_MODEL_P 2119 /* Record the fields for profiling. */ 2120 if (PROFILE_MODEL_P (current_cpu)) 2121 { 2122 FLD (in_src1) = f_r1; 2123 FLD (in_src2) = f_r2; 2124 } 2125#endif 2126#undef FLD 2127 return idesc; 2128 } 2129 2130 extract_sfmt_sth: 2131 { 2132 const IDESC *idesc = &m32r2f_insn_data[itype]; 2133 CGEN_INSN_INT insn = entire_insn; 2134#define FLD(f) abuf->fields.sfmt_st_plus.f 2135 UINT f_r1; 2136 UINT f_r2; 2137 2138 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2139 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2140 2141 /* Record the fields for the semantic handler. */ 2142 FLD (f_r1) = f_r1; 2143 FLD (f_r2) = f_r2; 2144 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2145 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2146 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2147 2148#if WITH_PROFILE_MODEL_P 2149 /* Record the fields for profiling. */ 2150 if (PROFILE_MODEL_P (current_cpu)) 2151 { 2152 FLD (in_src1) = f_r1; 2153 FLD (in_src2) = f_r2; 2154 } 2155#endif 2156#undef FLD 2157 return idesc; 2158 } 2159 2160 extract_sfmt_sth_d: 2161 { 2162 const IDESC *idesc = &m32r2f_insn_data[itype]; 2163 CGEN_INSN_INT insn = entire_insn; 2164#define FLD(f) abuf->fields.sfmt_st_d.f 2165 UINT f_r1; 2166 UINT f_r2; 2167 INT f_simm16; 2168 2169 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2170 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2171 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); 2172 2173 /* Record the fields for the semantic handler. */ 2174 FLD (f_simm16) = f_simm16; 2175 FLD (f_r1) = f_r1; 2176 FLD (f_r2) = f_r2; 2177 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2178 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2179 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2180 2181#if WITH_PROFILE_MODEL_P 2182 /* Record the fields for profiling. */ 2183 if (PROFILE_MODEL_P (current_cpu)) 2184 { 2185 FLD (in_src1) = f_r1; 2186 FLD (in_src2) = f_r2; 2187 } 2188#endif 2189#undef FLD 2190 return idesc; 2191 } 2192 2193 extract_sfmt_st_plus: 2194 { 2195 const IDESC *idesc = &m32r2f_insn_data[itype]; 2196 CGEN_INSN_INT insn = entire_insn; 2197#define FLD(f) abuf->fields.sfmt_st_plus.f 2198 UINT f_r1; 2199 UINT f_r2; 2200 2201 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2202 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2203 2204 /* Record the fields for the semantic handler. */ 2205 FLD (f_r1) = f_r1; 2206 FLD (f_r2) = f_r2; 2207 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2208 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2209 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2210 2211#if WITH_PROFILE_MODEL_P 2212 /* Record the fields for profiling. */ 2213 if (PROFILE_MODEL_P (current_cpu)) 2214 { 2215 FLD (in_src1) = f_r1; 2216 FLD (in_src2) = f_r2; 2217 FLD (out_src2) = f_r2; 2218 } 2219#endif 2220#undef FLD 2221 return idesc; 2222 } 2223 2224 extract_sfmt_sth_plus: 2225 { 2226 const IDESC *idesc = &m32r2f_insn_data[itype]; 2227 CGEN_INSN_INT insn = entire_insn; 2228#define FLD(f) abuf->fields.sfmt_st_plus.f 2229 UINT f_r1; 2230 UINT f_r2; 2231 2232 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2233 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2234 2235 /* Record the fields for the semantic handler. */ 2236 FLD (f_r1) = f_r1; 2237 FLD (f_r2) = f_r2; 2238 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2239 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2240 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2241 2242#if WITH_PROFILE_MODEL_P 2243 /* Record the fields for profiling. */ 2244 if (PROFILE_MODEL_P (current_cpu)) 2245 { 2246 FLD (in_src1) = f_r1; 2247 FLD (in_src2) = f_r2; 2248 FLD (out_src2) = f_r2; 2249 } 2250#endif 2251#undef FLD 2252 return idesc; 2253 } 2254 2255 extract_sfmt_stb_plus: 2256 { 2257 const IDESC *idesc = &m32r2f_insn_data[itype]; 2258 CGEN_INSN_INT insn = entire_insn; 2259#define FLD(f) abuf->fields.sfmt_st_plus.f 2260 UINT f_r1; 2261 UINT f_r2; 2262 2263 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2264 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2265 2266 /* Record the fields for the semantic handler. */ 2267 FLD (f_r1) = f_r1; 2268 FLD (f_r2) = f_r2; 2269 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2270 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2271 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2272 2273#if WITH_PROFILE_MODEL_P 2274 /* Record the fields for profiling. */ 2275 if (PROFILE_MODEL_P (current_cpu)) 2276 { 2277 FLD (in_src1) = f_r1; 2278 FLD (in_src2) = f_r2; 2279 FLD (out_src2) = f_r2; 2280 } 2281#endif 2282#undef FLD 2283 return idesc; 2284 } 2285 2286 extract_sfmt_trap: 2287 { 2288 const IDESC *idesc = &m32r2f_insn_data[itype]; 2289 CGEN_INSN_INT insn = entire_insn; 2290#define FLD(f) abuf->fields.sfmt_trap.f 2291 UINT f_uimm4; 2292 2293 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2294 2295 /* Record the fields for the semantic handler. */ 2296 FLD (f_uimm4) = f_uimm4; 2297 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0)); 2298 2299#if WITH_PROFILE_MODEL_P 2300 /* Record the fields for profiling. */ 2301 if (PROFILE_MODEL_P (current_cpu)) 2302 { 2303 } 2304#endif 2305#undef FLD 2306 return idesc; 2307 } 2308 2309 extract_sfmt_unlock: 2310 { 2311 const IDESC *idesc = &m32r2f_insn_data[itype]; 2312 CGEN_INSN_INT insn = entire_insn; 2313#define FLD(f) abuf->fields.sfmt_st_plus.f 2314 UINT f_r1; 2315 UINT f_r2; 2316 2317 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2318 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2319 2320 /* Record the fields for the semantic handler. */ 2321 FLD (f_r1) = f_r1; 2322 FLD (f_r2) = f_r2; 2323 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2324 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2325 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2326 2327#if WITH_PROFILE_MODEL_P 2328 /* Record the fields for profiling. */ 2329 if (PROFILE_MODEL_P (current_cpu)) 2330 { 2331 FLD (in_src1) = f_r1; 2332 FLD (in_src2) = f_r2; 2333 } 2334#endif 2335#undef FLD 2336 return idesc; 2337 } 2338 2339 extract_sfmt_satb: 2340 { 2341 const IDESC *idesc = &m32r2f_insn_data[itype]; 2342 CGEN_INSN_INT insn = entire_insn; 2343#define FLD(f) abuf->fields.sfmt_ld_plus.f 2344 UINT f_r1; 2345 UINT f_r2; 2346 2347 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2348 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2349 2350 /* Record the fields for the semantic handler. */ 2351 FLD (f_r2) = f_r2; 2352 FLD (f_r1) = f_r1; 2353 FLD (i_sr) = & CPU (h_gr)[f_r2]; 2354 FLD (i_dr) = & CPU (h_gr)[f_r1]; 2355 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 2356 2357#if WITH_PROFILE_MODEL_P 2358 /* Record the fields for profiling. */ 2359 if (PROFILE_MODEL_P (current_cpu)) 2360 { 2361 FLD (in_sr) = f_r2; 2362 FLD (out_dr) = f_r1; 2363 } 2364#endif 2365#undef FLD 2366 return idesc; 2367 } 2368 2369 extract_sfmt_sat: 2370 { 2371 const IDESC *idesc = &m32r2f_insn_data[itype]; 2372 CGEN_INSN_INT insn = entire_insn; 2373#define FLD(f) abuf->fields.sfmt_ld_plus.f 2374 UINT f_r1; 2375 UINT f_r2; 2376 2377 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2378 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2379 2380 /* Record the fields for the semantic handler. */ 2381 FLD (f_r2) = f_r2; 2382 FLD (f_r1) = f_r1; 2383 FLD (i_sr) = & CPU (h_gr)[f_r2]; 2384 FLD (i_dr) = & CPU (h_gr)[f_r1]; 2385 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 2386 2387#if WITH_PROFILE_MODEL_P 2388 /* Record the fields for profiling. */ 2389 if (PROFILE_MODEL_P (current_cpu)) 2390 { 2391 FLD (in_sr) = f_r2; 2392 FLD (out_dr) = f_r1; 2393 } 2394#endif 2395#undef FLD 2396 return idesc; 2397 } 2398 2399 extract_sfmt_sadd: 2400 { 2401 const IDESC *idesc = &m32r2f_insn_data[itype]; 2402#define FLD(f) abuf->fields.fmt_empty.f 2403 2404 2405 /* Record the fields for the semantic handler. */ 2406 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0)); 2407 2408#undef FLD 2409 return idesc; 2410 } 2411 2412 extract_sfmt_macwu1: 2413 { 2414 const IDESC *idesc = &m32r2f_insn_data[itype]; 2415 CGEN_INSN_INT insn = entire_insn; 2416#define FLD(f) abuf->fields.sfmt_st_plus.f 2417 UINT f_r1; 2418 UINT f_r2; 2419 2420 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2421 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2422 2423 /* Record the fields for the semantic handler. */ 2424 FLD (f_r1) = f_r1; 2425 FLD (f_r2) = f_r2; 2426 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2427 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2428 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2429 2430#if WITH_PROFILE_MODEL_P 2431 /* Record the fields for profiling. */ 2432 if (PROFILE_MODEL_P (current_cpu)) 2433 { 2434 FLD (in_src1) = f_r1; 2435 FLD (in_src2) = f_r2; 2436 } 2437#endif 2438#undef FLD 2439 return idesc; 2440 } 2441 2442 extract_sfmt_msblo: 2443 { 2444 const IDESC *idesc = &m32r2f_insn_data[itype]; 2445 CGEN_INSN_INT insn = entire_insn; 2446#define FLD(f) abuf->fields.sfmt_st_plus.f 2447 UINT f_r1; 2448 UINT f_r2; 2449 2450 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2451 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2452 2453 /* Record the fields for the semantic handler. */ 2454 FLD (f_r1) = f_r1; 2455 FLD (f_r2) = f_r2; 2456 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2457 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2458 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2459 2460#if WITH_PROFILE_MODEL_P 2461 /* Record the fields for profiling. */ 2462 if (PROFILE_MODEL_P (current_cpu)) 2463 { 2464 FLD (in_src1) = f_r1; 2465 FLD (in_src2) = f_r2; 2466 } 2467#endif 2468#undef FLD 2469 return idesc; 2470 } 2471 2472 extract_sfmt_mulwu1: 2473 { 2474 const IDESC *idesc = &m32r2f_insn_data[itype]; 2475 CGEN_INSN_INT insn = entire_insn; 2476#define FLD(f) abuf->fields.sfmt_st_plus.f 2477 UINT f_r1; 2478 UINT f_r2; 2479 2480 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2481 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2482 2483 /* Record the fields for the semantic handler. */ 2484 FLD (f_r1) = f_r1; 2485 FLD (f_r2) = f_r2; 2486 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2487 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2488 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2489 2490#if WITH_PROFILE_MODEL_P 2491 /* Record the fields for profiling. */ 2492 if (PROFILE_MODEL_P (current_cpu)) 2493 { 2494 FLD (in_src1) = f_r1; 2495 FLD (in_src2) = f_r2; 2496 } 2497#endif 2498#undef FLD 2499 return idesc; 2500 } 2501 2502 extract_sfmt_sc: 2503 { 2504 const IDESC *idesc = &m32r2f_insn_data[itype]; 2505#define FLD(f) abuf->fields.fmt_empty.f 2506 2507 2508 /* Record the fields for the semantic handler. */ 2509 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0)); 2510 2511#undef FLD 2512 return idesc; 2513 } 2514 2515 extract_sfmt_clrpsw: 2516 { 2517 const IDESC *idesc = &m32r2f_insn_data[itype]; 2518 CGEN_INSN_INT insn = entire_insn; 2519#define FLD(f) abuf->fields.sfmt_clrpsw.f 2520 UINT f_uimm8; 2521 2522 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); 2523 2524 /* Record the fields for the semantic handler. */ 2525 FLD (f_uimm8) = f_uimm8; 2526 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); 2527 2528#undef FLD 2529 return idesc; 2530 } 2531 2532 extract_sfmt_setpsw: 2533 { 2534 const IDESC *idesc = &m32r2f_insn_data[itype]; 2535 CGEN_INSN_INT insn = entire_insn; 2536#define FLD(f) abuf->fields.sfmt_clrpsw.f 2537 UINT f_uimm8; 2538 2539 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); 2540 2541 /* Record the fields for the semantic handler. */ 2542 FLD (f_uimm8) = f_uimm8; 2543 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); 2544 2545#undef FLD 2546 return idesc; 2547 } 2548 2549 extract_sfmt_bset: 2550 { 2551 const IDESC *idesc = &m32r2f_insn_data[itype]; 2552 CGEN_INSN_INT insn = entire_insn; 2553#define FLD(f) abuf->fields.sfmt_bset.f 2554 UINT f_uimm3; 2555 UINT f_r2; 2556 INT f_simm16; 2557 2558 f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); 2559 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2560 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); 2561 2562 /* Record the fields for the semantic handler. */ 2563 FLD (f_simm16) = f_simm16; 2564 FLD (f_r2) = f_r2; 2565 FLD (f_uimm3) = f_uimm3; 2566 FLD (i_sr) = & CPU (h_gr)[f_r2]; 2567 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); 2568 2569#if WITH_PROFILE_MODEL_P 2570 /* Record the fields for profiling. */ 2571 if (PROFILE_MODEL_P (current_cpu)) 2572 { 2573 FLD (in_sr) = f_r2; 2574 } 2575#endif 2576#undef FLD 2577 return idesc; 2578 } 2579 2580 extract_sfmt_btst: 2581 { 2582 const IDESC *idesc = &m32r2f_insn_data[itype]; 2583 CGEN_INSN_INT insn = entire_insn; 2584#define FLD(f) abuf->fields.sfmt_bset.f 2585 UINT f_uimm3; 2586 UINT f_r2; 2587 2588 f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); 2589 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2590 2591 /* Record the fields for the semantic handler. */ 2592 FLD (f_r2) = f_r2; 2593 FLD (f_uimm3) = f_uimm3; 2594 FLD (i_sr) = & CPU (h_gr)[f_r2]; 2595 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); 2596 2597#if WITH_PROFILE_MODEL_P 2598 /* Record the fields for profiling. */ 2599 if (PROFILE_MODEL_P (current_cpu)) 2600 { 2601 FLD (in_sr) = f_r2; 2602 } 2603#endif 2604#undef FLD 2605 return idesc; 2606 } 2607 2608} 2609