1/* CPU family header for sh64. 2 3THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5Copyright 1996-2005 Free Software Foundation, Inc. 6 7This file is part of the GNU simulators. 8 9This program is free software; you can redistribute it and/or modify 10it under the terms of the GNU General Public License as published by 11the Free Software Foundation; either version 3 of the License, or 12(at your option) any later version. 13 14This program is distributed in the hope that it will be useful, 15but WITHOUT ANY WARRANTY; without even the implied warranty of 16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17GNU General Public License for more details. 18 19You should have received a copy of the GNU General Public License 20along with this program. If not, see <http://www.gnu.org/licenses/>. 21 22*/ 23 24#ifndef CPU_SH64_H 25#define CPU_SH64_H 26 27/* Maximum number of instructions that are fetched at a time. 28 This is for LIW type instructions sets (e.g. m32r). */ 29#define MAX_LIW_INSNS 1 30 31/* Maximum number of instructions that can be executed in parallel. */ 32#define MAX_PARALLEL_INSNS 1 33 34/* CPU state information. */ 35typedef struct { 36 /* Hardware elements. */ 37 struct { 38 /* Program counter */ 39 UDI h_pc; 40#define GET_H_PC() CPU (h_pc) 41#define SET_H_PC(x) \ 42do { \ 43{\ 44CPU (h_ism) = ANDDI ((x), 1);\ 45CPU (h_pc) = ANDDI ((x), INVDI (1));\ 46}\ 47;} while (0) 48 /* General purpose integer registers */ 49 DI h_gr[64]; 50#define GET_H_GR(index) ((((index) == (63))) ? (0) : (CPU (h_gr[index]))) 51#define SET_H_GR(index, x) \ 52do { \ 53if ((((index)) != (63))) {\ 54CPU (h_gr[(index)]) = (x);\ 55} else {\ 56((void) 0); /*nop*/\ 57}\ 58;} while (0) 59 /* Control registers */ 60 DI h_cr[64]; 61#define GET_H_CR(index) ((((index) == (0))) ? (ZEXTSIDI (CPU (h_sr))) : (CPU (h_cr[index]))) 62#define SET_H_CR(index, x) \ 63do { \ 64if ((((index)) == (0))) {\ 65CPU (h_sr) = (x);\ 66} else {\ 67CPU (h_cr[(index)]) = (x);\ 68}\ 69;} while (0) 70 /* Status register */ 71 SI h_sr; 72#define GET_H_SR() CPU (h_sr) 73#define SET_H_SR(x) (CPU (h_sr) = (x)) 74 /* Floating point status and control register */ 75 SI h_fpscr; 76#define GET_H_FPSCR() CPU (h_fpscr) 77#define SET_H_FPSCR(x) (CPU (h_fpscr) = (x)) 78 /* Single precision floating point registers */ 79 SF h_fr[64]; 80#define GET_H_FR(a1) CPU (h_fr)[a1] 81#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x)) 82 /* Single/Double precision floating point registers */ 83 DF h_fsd[16]; 84#define GET_H_FSD(index) ((GET_H_PRBIT ()) ? (GET_H_DRC (index)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), CPU (h_fr[index])))) 85#define SET_H_FSD(index, x) \ 86do { \ 87if (GET_H_PRBIT ()) {\ 88SET_H_DRC ((index), (x));\ 89} else {\ 90SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), (x)));\ 91}\ 92;} while (0) 93 /* floating point registers for fmov */ 94 DF h_fmov[16]; 95#define GET_H_FMOV(index) ((NOTBI (GET_H_SZBIT ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), GET_H_FRC (index))) : (((((((index) & (1))) == (1))) ? (GET_H_XD (((index) & ((~ (1)))))) : (GET_H_DR (index))))) 96#define SET_H_FMOV(index, x) \ 97do { \ 98if (NOTBI (GET_H_SZBIT ())) {\ 99SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), (x)));\ 100} else {\ 101if ((((((index)) & (1))) == (1))) {\ 102SET_H_XD ((((index)) & ((~ (1)))), (x));\ 103} else {\ 104SET_H_DR ((index), (x));\ 105}\ 106}\ 107;} while (0) 108 /* Branch target registers */ 109 DI h_tr[8]; 110#define GET_H_TR(a1) CPU (h_tr)[a1] 111#define SET_H_TR(a1, x) (CPU (h_tr)[a1] = (x)) 112 /* Current instruction set mode */ 113 BI h_ism; 114#define GET_H_ISM() CPU (h_ism) 115#define SET_H_ISM(x) \ 116do { \ 117cgen_rtx_error (current_cpu, "cannot set ism directly");\ 118;} while (0) 119 } hardware; 120#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) 121} SH64_CPU_DATA; 122 123/* Virtual regs. */ 124 125#define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff)) 126#define SET_H_GRC(index, x) \ 127do { \ 128CPU (h_gr[(index)]) = EXTSIDI ((x));\ 129;} while (0) 130#define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_fpscr), 21), 1) 131#define SET_H_FRBIT(x) \ 132do { \ 133CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (21))))), SLLSI ((x), 21));\ 134;} while (0) 135#define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_fpscr), 20), 1) 136#define SET_H_SZBIT(x) \ 137do { \ 138CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (20))))), SLLSI ((x), 20));\ 139;} while (0) 140#define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_fpscr), 19), 1) 141#define SET_H_PRBIT(x) \ 142do { \ 143CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (19))))), SLLSI ((x), 19));\ 144;} while (0) 145#define GET_H_SBIT() ANDSI (SRLSI (CPU (h_sr), 1), 1) 146#define SET_H_SBIT(x) \ 147do { \ 148CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (2))), SLLSI ((x), 1));\ 149;} while (0) 150#define GET_H_MBIT() ANDSI (SRLSI (CPU (h_sr), 9), 1) 151#define SET_H_MBIT(x) \ 152do { \ 153CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (9))))), SLLSI ((x), 9));\ 154;} while (0) 155#define GET_H_QBIT() ANDSI (SRLSI (CPU (h_sr), 8), 1) 156#define SET_H_QBIT(x) \ 157do { \ 158CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (8))))), SLLSI ((x), 8));\ 159;} while (0) 160#define GET_H_FP(index) CPU (h_fr[index]) 161#define SET_H_FP(index, x) \ 162do { \ 163CPU (h_fr[(index)]) = (x);\ 164;} while (0) 165#define GET_H_FV(index) CPU (h_fr[index]) 166#define SET_H_FV(index, x) \ 167do { \ 168CPU (h_fr[(index)]) = (x);\ 169;} while (0) 170#define GET_H_FMTX(index) CPU (h_fr[index]) 171#define SET_H_FMTX(index, x) \ 172do { \ 173CPU (h_fr[(index)]) = (x);\ 174;} while (0) 175#define GET_H_DR(index) SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[index]))), 32), ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[((index) + (1))]))))) 176#define SET_H_DR(index, x) \ 177do { \ 178{\ 179CPU (h_fr[(index)]) = SUBWORDSISF (SUBWORDDFSI ((x), 0));\ 180CPU (h_fr[(((index)) + (1))]) = SUBWORDSISF (SUBWORDDFSI ((x), 1));\ 181}\ 182;} while (0) 183#define GET_H_ENDIAN() sh64_endian (current_cpu) 184#define SET_H_ENDIAN(x) \ 185do { \ 186cgen_rtx_error (current_cpu, "cannot alter target byte order mid-program");\ 187;} while (0) 188#define GET_H_FRC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))]) 189#define SET_H_FRC(index, x) \ 190do { \ 191CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\ 192;} while (0) 193#define GET_H_DRC(index) GET_H_DR (((((16) * (GET_H_FRBIT ()))) + (index))) 194#define SET_H_DRC(index, x) \ 195do { \ 196SET_H_DR (((((16) * (GET_H_FRBIT ()))) + ((index))), (x));\ 197;} while (0) 198#define GET_H_XF(index) CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))]) 199#define SET_H_XF(index, x) \ 200do { \ 201CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index)))]) = (x);\ 202;} while (0) 203#define GET_H_XD(index) GET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))) 204#define SET_H_XD(index, x) \ 205do { \ 206SET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index))), (x));\ 207;} while (0) 208#define GET_H_FVC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))]) 209#define SET_H_FVC(index, x) \ 210do { \ 211CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\ 212;} while (0) 213#define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1) 214#define SET_H_GBR(x) \ 215do { \ 216CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\ 217;} while (0) 218#define GET_H_VBR() SUBWORDDISI (CPU (h_gr[((UINT) 20)]), 1) 219#define SET_H_VBR(x) \ 220do { \ 221CPU (h_gr[((UINT) 20)]) = EXTSIDI ((x));\ 222;} while (0) 223#define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UINT) 18)]), 1) 224#define SET_H_PR(x) \ 225do { \ 226CPU (h_gr[((UINT) 18)]) = EXTSIDI ((x));\ 227;} while (0) 228#define GET_H_MACL() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1) 229#define SET_H_MACL(x) \ 230do { \ 231CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)), 32), ZEXTSIDI ((x)));\ 232;} while (0) 233#define GET_H_MACH() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0) 234#define SET_H_MACH(x) \ 235do { \ 236CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI ((x)), 32), ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)));\ 237;} while (0) 238#define GET_H_TBIT() ANDBI (CPU (h_gr[((UINT) 19)]), 1) 239#define SET_H_TBIT(x) \ 240do { \ 241CPU (h_gr[((UINT) 19)]) = ORDI (ANDDI (CPU (h_gr[((UINT) 19)]), INVDI (1)), ZEXTBIDI ((x)));\ 242;} while (0) 243 244/* Cover fns for register access. */ 245UDI sh64_h_pc_get (SIM_CPU *); 246void sh64_h_pc_set (SIM_CPU *, UDI); 247DI sh64_h_gr_get (SIM_CPU *, UINT); 248void sh64_h_gr_set (SIM_CPU *, UINT, DI); 249SI sh64_h_grc_get (SIM_CPU *, UINT); 250void sh64_h_grc_set (SIM_CPU *, UINT, SI); 251DI sh64_h_cr_get (SIM_CPU *, UINT); 252void sh64_h_cr_set (SIM_CPU *, UINT, DI); 253SI sh64_h_sr_get (SIM_CPU *); 254void sh64_h_sr_set (SIM_CPU *, SI); 255SI sh64_h_fpscr_get (SIM_CPU *); 256void sh64_h_fpscr_set (SIM_CPU *, SI); 257BI sh64_h_frbit_get (SIM_CPU *); 258void sh64_h_frbit_set (SIM_CPU *, BI); 259BI sh64_h_szbit_get (SIM_CPU *); 260void sh64_h_szbit_set (SIM_CPU *, BI); 261BI sh64_h_prbit_get (SIM_CPU *); 262void sh64_h_prbit_set (SIM_CPU *, BI); 263BI sh64_h_sbit_get (SIM_CPU *); 264void sh64_h_sbit_set (SIM_CPU *, BI); 265BI sh64_h_mbit_get (SIM_CPU *); 266void sh64_h_mbit_set (SIM_CPU *, BI); 267BI sh64_h_qbit_get (SIM_CPU *); 268void sh64_h_qbit_set (SIM_CPU *, BI); 269SF sh64_h_fr_get (SIM_CPU *, UINT); 270void sh64_h_fr_set (SIM_CPU *, UINT, SF); 271SF sh64_h_fp_get (SIM_CPU *, UINT); 272void sh64_h_fp_set (SIM_CPU *, UINT, SF); 273SF sh64_h_fv_get (SIM_CPU *, UINT); 274void sh64_h_fv_set (SIM_CPU *, UINT, SF); 275SF sh64_h_fmtx_get (SIM_CPU *, UINT); 276void sh64_h_fmtx_set (SIM_CPU *, UINT, SF); 277DF sh64_h_dr_get (SIM_CPU *, UINT); 278void sh64_h_dr_set (SIM_CPU *, UINT, DF); 279DF sh64_h_fsd_get (SIM_CPU *, UINT); 280void sh64_h_fsd_set (SIM_CPU *, UINT, DF); 281DF sh64_h_fmov_get (SIM_CPU *, UINT); 282void sh64_h_fmov_set (SIM_CPU *, UINT, DF); 283DI sh64_h_tr_get (SIM_CPU *, UINT); 284void sh64_h_tr_set (SIM_CPU *, UINT, DI); 285BI sh64_h_endian_get (SIM_CPU *); 286void sh64_h_endian_set (SIM_CPU *, BI); 287BI sh64_h_ism_get (SIM_CPU *); 288void sh64_h_ism_set (SIM_CPU *, BI); 289SF sh64_h_frc_get (SIM_CPU *, UINT); 290void sh64_h_frc_set (SIM_CPU *, UINT, SF); 291DF sh64_h_drc_get (SIM_CPU *, UINT); 292void sh64_h_drc_set (SIM_CPU *, UINT, DF); 293SF sh64_h_xf_get (SIM_CPU *, UINT); 294void sh64_h_xf_set (SIM_CPU *, UINT, SF); 295DF sh64_h_xd_get (SIM_CPU *, UINT); 296void sh64_h_xd_set (SIM_CPU *, UINT, DF); 297SF sh64_h_fvc_get (SIM_CPU *, UINT); 298void sh64_h_fvc_set (SIM_CPU *, UINT, SF); 299SI sh64_h_gbr_get (SIM_CPU *); 300void sh64_h_gbr_set (SIM_CPU *, SI); 301SI sh64_h_vbr_get (SIM_CPU *); 302void sh64_h_vbr_set (SIM_CPU *, SI); 303SI sh64_h_pr_get (SIM_CPU *); 304void sh64_h_pr_set (SIM_CPU *, SI); 305SI sh64_h_macl_get (SIM_CPU *); 306void sh64_h_macl_set (SIM_CPU *, SI); 307SI sh64_h_mach_get (SIM_CPU *); 308void sh64_h_mach_set (SIM_CPU *, SI); 309BI sh64_h_tbit_get (SIM_CPU *); 310void sh64_h_tbit_set (SIM_CPU *, BI); 311 312/* These must be hand-written. */ 313extern CPUREG_FETCH_FN sh64_fetch_register; 314extern CPUREG_STORE_FN sh64_store_register; 315 316typedef struct { 317 int empty; 318} MODEL_SH4_DATA; 319 320typedef struct { 321 int empty; 322} MODEL_SH5_DATA; 323 324typedef struct { 325 int empty; 326} MODEL_SH5_MEDIA_DATA; 327 328/* Collection of various things for the trace handler to use. */ 329 330typedef struct trace_record { 331 IADDR pc; 332 /* FIXME:wip */ 333} TRACE_RECORD; 334 335#endif /* CPU_SH64_H */ 336