Searched refs:UART_LSR_DR (Results 1 - 25 of 57) sorted by relevance

123

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/powerpc/boot/
H A Dns16550.c25 #define UART_LSR_DR 0x01 /* Receiver data ready */ macro
46 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0);
52 return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/powerpc/boot/
H A Dns16550.c25 #define UART_LSR_DR 0x01 /* Receiver data ready */ macro
46 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0);
52 return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/serial/
H A Dm32r_sio_reg.h131 #define UART_LSR_DR 0x04 /* Receiver data ready */ macro
H A Dsunsu.c284 up->port.read_status_mask &= ~UART_LSR_DR;
370 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
448 if (status & UART_LSR_DR)
514 } while (serial_in(up, UART_LSR) & UART_LSR_DR);
524 if ((status & UART_LSR_DR) || (status & UART_LSR_BI))
816 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
842 up->port.ignore_status_mask |= UART_LSR_DR;
H A Dpxa.c94 up->port.read_status_mask &= ~UART_LSR_DR;
159 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
239 if (lsr & UART_LSR_DR)
473 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
499 up->port.ignore_status_mask |= UART_LSR_DR;
H A Dvr41xx_siu.c278 port->read_status_mask &= ~UART_LSR_DR;
366 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
438 if (lsr & UART_LSR_DR)
561 port->read_status_mask = UART_LSR_THRE | UART_LSR_OE | UART_LSR_DR;
577 port->ignore_status_mask |= UART_LSR_DR;
H A Dm32r_sio.c306 up->port.read_status_mask &= ~UART_LSR_DR;
387 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
751 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
777 up->port.ignore_status_mask |= UART_LSR_DR;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/serial/
H A Dm32r_sio_reg.h131 #define UART_LSR_DR 0x04 /* Receiver data ready */ macro
H A Dsunsu.c284 up->port.read_status_mask &= ~UART_LSR_DR;
370 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
448 if (status & UART_LSR_DR)
514 } while (serial_in(up, UART_LSR) & UART_LSR_DR);
524 if ((status & UART_LSR_DR) || (status & UART_LSR_BI))
816 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
842 up->port.ignore_status_mask |= UART_LSR_DR;
H A Dpxa.c94 up->port.read_status_mask &= ~UART_LSR_DR;
159 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
239 if (lsr & UART_LSR_DR)
473 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
499 up->port.ignore_status_mask |= UART_LSR_DR;
H A Dvr41xx_siu.c278 port->read_status_mask &= ~UART_LSR_DR;
366 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
438 if (lsr & UART_LSR_DR)
561 port->read_status_mask = UART_LSR_THRE | UART_LSR_OE | UART_LSR_DR;
577 port->ignore_status_mask |= UART_LSR_DR;
H A Dm32r_sio.c306 up->port.read_status_mask &= ~UART_LSR_DR;
387 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
751 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
777 up->port.ignore_status_mask |= UART_LSR_DR;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/powerpc/platforms/embedded6xx/
H A Dls_uart.c46 while (in_8(avr_addr + UART_LSR) & UART_LSR_DR)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/powerpc/platforms/embedded6xx/
H A Dls_uart.c46 while (in_8(avr_addr + UART_LSR) & UART_LSR_DR)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mn10300/kernel/
H A Dgdb-io-serial-low.S48 btst UART_LSR_DR,d3
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/frv/kernel/
H A Dgdb-io.c119 while (__UART(LSR) & UART_LSR_DR) {
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/frv/kernel/
H A Dgdb-io.c119 while (__UART(LSR) & UART_LSR_DR) {
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mn10300/kernel/
H A Dgdb-io-serial-low.S48 btst UART_LSR_DR,d3
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/mmc/card/
H A Dsdio_uart.c320 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
346 port->ignore_status_mask |= UART_LSR_DR;
386 port->read_status_mask &= ~UART_LSR_DR;
442 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
563 if (lsr & UART_LSR_DR)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/mmc/card/
H A Dsdio_uart.c320 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
346 port->ignore_status_mask |= UART_LSR_DR;
386 port->read_status_mask &= ~UART_LSR_DR;
442 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
563 if (lsr & UART_LSR_DR)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/include/linux/
H A Dserial_reg.h120 #define UART_LSR_DR 0x01 /* Receiver data ready */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-orion5x/
H A Dkurobox_pro-setup.c195 while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) {
H A Dterastation_pro2-setup.c175 while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) {
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/include/linux/
H A Dserial_reg.h120 #define UART_LSR_DR 0x01 /* Receiver data ready */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-orion5x/
H A Dkurobox_pro-setup.c195 while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) {

Completed in 194 milliseconds

123