1/* 2 * su.c: Small serial driver for keyboard/mouse interface on sparc32/PCI 3 * 4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be) 5 * Copyright (C) 1998-1999 Pete Zaitcev (zaitcev@yahoo.com) 6 * 7 * This is mainly a variation of 8250.c, credits go to authors mentioned 8 * therein. In fact this driver should be merged into the generic 8250.c 9 * infrastructure perhaps using a 8250_sparc.c module. 10 * 11 * Fixed to use tty_get_baud_rate(). 12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12 13 * 14 * Converted to new 2.5.x UART layer. 15 * David S. Miller (davem@davemloft.net), 2002-Jul-29 16 */ 17 18#include <linux/module.h> 19#include <linux/kernel.h> 20#include <linux/spinlock.h> 21#include <linux/errno.h> 22#include <linux/tty.h> 23#include <linux/tty_flip.h> 24#include <linux/major.h> 25#include <linux/string.h> 26#include <linux/ptrace.h> 27#include <linux/ioport.h> 28#include <linux/circ_buf.h> 29#include <linux/serial.h> 30#include <linux/sysrq.h> 31#include <linux/console.h> 32#include <linux/slab.h> 33#ifdef CONFIG_SERIO 34#include <linux/serio.h> 35#endif 36#include <linux/serial_reg.h> 37#include <linux/init.h> 38#include <linux/delay.h> 39#include <linux/of_device.h> 40 41#include <asm/io.h> 42#include <asm/irq.h> 43#include <asm/prom.h> 44 45#if defined(CONFIG_SERIAL_SUNSU_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 46#define SUPPORT_SYSRQ 47#endif 48 49#include <linux/serial_core.h> 50 51#include "suncore.h" 52 53/* We are on a NS PC87303 clocked with 24.0 MHz, which results 54 * in a UART clock of 1.8462 MHz. 55 */ 56#define SU_BASE_BAUD (1846200 / 16) 57 58enum su_type { SU_PORT_NONE, SU_PORT_MS, SU_PORT_KBD, SU_PORT_PORT }; 59static char *su_typev[] = { "su(???)", "su(mouse)", "su(kbd)", "su(serial)" }; 60 61/* 62 * Here we define the default xmit fifo size used for each type of UART. 63 */ 64static const struct serial_uart_config uart_config[PORT_MAX_8250+1] = { 65 { "unknown", 1, 0 }, 66 { "8250", 1, 0 }, 67 { "16450", 1, 0 }, 68 { "16550", 1, 0 }, 69 { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO }, 70 { "Cirrus", 1, 0 }, 71 { "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH }, 72 { "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH }, 73 { "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO }, 74 { "Startech", 1, 0 }, 75 { "16C950/954", 128, UART_CLEAR_FIFO | UART_USE_FIFO }, 76 { "ST16654", 64, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH }, 77 { "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH }, 78 { "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO } 79}; 80 81struct uart_sunsu_port { 82 struct uart_port port; 83 unsigned char acr; 84 unsigned char ier; 85 unsigned short rev; 86 unsigned char lcr; 87 unsigned int lsr_break_flag; 88 unsigned int cflag; 89 90 /* Probing information. */ 91 enum su_type su_type; 92 unsigned int type_probed; 93 unsigned long reg_size; 94 95#ifdef CONFIG_SERIO 96 struct serio serio; 97 int serio_open; 98#endif 99}; 100 101static unsigned int serial_in(struct uart_sunsu_port *up, int offset) 102{ 103 offset <<= up->port.regshift; 104 105 switch (up->port.iotype) { 106 case UPIO_HUB6: 107 outb(up->port.hub6 - 1 + offset, up->port.iobase); 108 return inb(up->port.iobase + 1); 109 110 case UPIO_MEM: 111 return readb(up->port.membase + offset); 112 113 default: 114 return inb(up->port.iobase + offset); 115 } 116} 117 118static void serial_out(struct uart_sunsu_port *up, int offset, int value) 119{ 120#ifndef CONFIG_SPARC64 121 /* 122 * MrCoffee has weird schematics: IRQ4 & P10(?) pins of SuperIO are 123 * connected with a gate then go to SlavIO. When IRQ4 goes tristated 124 * gate outputs a logical one. Since we use level triggered interrupts 125 * we have lockup and watchdog reset. We cannot mask IRQ because 126 * keyboard shares IRQ with us (Word has it as Bob Smelik's design). 127 * This problem is similar to what Alpha people suffer, see serial.c. 128 */ 129 if (offset == UART_MCR) 130 value |= UART_MCR_OUT2; 131#endif 132 offset <<= up->port.regshift; 133 134 switch (up->port.iotype) { 135 case UPIO_HUB6: 136 outb(up->port.hub6 - 1 + offset, up->port.iobase); 137 outb(value, up->port.iobase + 1); 138 break; 139 140 case UPIO_MEM: 141 writeb(value, up->port.membase + offset); 142 break; 143 144 default: 145 outb(value, up->port.iobase + offset); 146 } 147} 148 149/* 150 * We used to support using pause I/O for certain machines. We 151 * haven't supported this for a while, but just in case it's badly 152 * needed for certain old 386 machines, I've left these #define's 153 * in.... 154 */ 155#define serial_inp(up, offset) serial_in(up, offset) 156#define serial_outp(up, offset, value) serial_out(up, offset, value) 157 158 159/* 160 * For the 16C950 161 */ 162static void serial_icr_write(struct uart_sunsu_port *up, int offset, int value) 163{ 164 serial_out(up, UART_SCR, offset); 165 serial_out(up, UART_ICR, value); 166} 167 168 169#ifdef CONFIG_SERIAL_8250_RSA 170/* 171 * Attempts to turn on the RSA FIFO. Returns zero on failure. 172 * We set the port uart clock rate if we succeed. 173 */ 174static int __enable_rsa(struct uart_sunsu_port *up) 175{ 176 unsigned char mode; 177 int result; 178 179 mode = serial_inp(up, UART_RSA_MSR); 180 result = mode & UART_RSA_MSR_FIFO; 181 182 if (!result) { 183 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); 184 mode = serial_inp(up, UART_RSA_MSR); 185 result = mode & UART_RSA_MSR_FIFO; 186 } 187 188 if (result) 189 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; 190 191 return result; 192} 193 194static void enable_rsa(struct uart_sunsu_port *up) 195{ 196 if (up->port.type == PORT_RSA) { 197 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { 198 spin_lock_irq(&up->port.lock); 199 __enable_rsa(up); 200 spin_unlock_irq(&up->port.lock); 201 } 202 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) 203 serial_outp(up, UART_RSA_FRR, 0); 204 } 205} 206 207/* 208 * Attempts to turn off the RSA FIFO. Returns zero on failure. 209 * It is unknown why interrupts were disabled in here. However, 210 * the caller is expected to preserve this behaviour by grabbing 211 * the spinlock before calling this function. 212 */ 213static void disable_rsa(struct uart_sunsu_port *up) 214{ 215 unsigned char mode; 216 int result; 217 218 if (up->port.type == PORT_RSA && 219 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { 220 spin_lock_irq(&up->port.lock); 221 222 mode = serial_inp(up, UART_RSA_MSR); 223 result = !(mode & UART_RSA_MSR_FIFO); 224 225 if (!result) { 226 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); 227 mode = serial_inp(up, UART_RSA_MSR); 228 result = !(mode & UART_RSA_MSR_FIFO); 229 } 230 231 if (result) 232 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; 233 spin_unlock_irq(&up->port.lock); 234 } 235} 236#endif /* CONFIG_SERIAL_8250_RSA */ 237 238static inline void __stop_tx(struct uart_sunsu_port *p) 239{ 240 if (p->ier & UART_IER_THRI) { 241 p->ier &= ~UART_IER_THRI; 242 serial_out(p, UART_IER, p->ier); 243 } 244} 245 246static void sunsu_stop_tx(struct uart_port *port) 247{ 248 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; 249 250 __stop_tx(up); 251 252 /* 253 * We really want to stop the transmitter from sending. 254 */ 255 if (up->port.type == PORT_16C950) { 256 up->acr |= UART_ACR_TXDIS; 257 serial_icr_write(up, UART_ACR, up->acr); 258 } 259} 260 261static void sunsu_start_tx(struct uart_port *port) 262{ 263 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; 264 265 if (!(up->ier & UART_IER_THRI)) { 266 up->ier |= UART_IER_THRI; 267 serial_out(up, UART_IER, up->ier); 268 } 269 270 /* 271 * Re-enable the transmitter if we disabled it. 272 */ 273 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { 274 up->acr &= ~UART_ACR_TXDIS; 275 serial_icr_write(up, UART_ACR, up->acr); 276 } 277} 278 279static void sunsu_stop_rx(struct uart_port *port) 280{ 281 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; 282 283 up->ier &= ~UART_IER_RLSI; 284 up->port.read_status_mask &= ~UART_LSR_DR; 285 serial_out(up, UART_IER, up->ier); 286} 287 288static void sunsu_enable_ms(struct uart_port *port) 289{ 290 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; 291 unsigned long flags; 292 293 spin_lock_irqsave(&up->port.lock, flags); 294 up->ier |= UART_IER_MSI; 295 serial_out(up, UART_IER, up->ier); 296 spin_unlock_irqrestore(&up->port.lock, flags); 297} 298 299static struct tty_struct * 300receive_chars(struct uart_sunsu_port *up, unsigned char *status) 301{ 302 struct tty_struct *tty = up->port.state->port.tty; 303 unsigned char ch, flag; 304 int max_count = 256; 305 int saw_console_brk = 0; 306 307 do { 308 ch = serial_inp(up, UART_RX); 309 flag = TTY_NORMAL; 310 up->port.icount.rx++; 311 312 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | 313 UART_LSR_FE | UART_LSR_OE))) { 314 /* 315 * For statistics only 316 */ 317 if (*status & UART_LSR_BI) { 318 *status &= ~(UART_LSR_FE | UART_LSR_PE); 319 up->port.icount.brk++; 320 if (up->port.cons != NULL && 321 up->port.line == up->port.cons->index) 322 saw_console_brk = 1; 323 /* 324 * We do the SysRQ and SAK checking 325 * here because otherwise the break 326 * may get masked by ignore_status_mask 327 * or read_status_mask. 328 */ 329 if (uart_handle_break(&up->port)) 330 goto ignore_char; 331 } else if (*status & UART_LSR_PE) 332 up->port.icount.parity++; 333 else if (*status & UART_LSR_FE) 334 up->port.icount.frame++; 335 if (*status & UART_LSR_OE) 336 up->port.icount.overrun++; 337 338 /* 339 * Mask off conditions which should be ingored. 340 */ 341 *status &= up->port.read_status_mask; 342 343 if (up->port.cons != NULL && 344 up->port.line == up->port.cons->index) { 345 /* Recover the break flag from console xmit */ 346 *status |= up->lsr_break_flag; 347 up->lsr_break_flag = 0; 348 } 349 350 if (*status & UART_LSR_BI) { 351 flag = TTY_BREAK; 352 } else if (*status & UART_LSR_PE) 353 flag = TTY_PARITY; 354 else if (*status & UART_LSR_FE) 355 flag = TTY_FRAME; 356 } 357 if (uart_handle_sysrq_char(&up->port, ch)) 358 goto ignore_char; 359 if ((*status & up->port.ignore_status_mask) == 0) 360 tty_insert_flip_char(tty, ch, flag); 361 if (*status & UART_LSR_OE) 362 /* 363 * Overrun is special, since it's reported 364 * immediately, and doesn't affect the current 365 * character. 366 */ 367 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 368 ignore_char: 369 *status = serial_inp(up, UART_LSR); 370 } while ((*status & UART_LSR_DR) && (max_count-- > 0)); 371 372 if (saw_console_brk) 373 sun_do_break(); 374 375 return tty; 376} 377 378static void transmit_chars(struct uart_sunsu_port *up) 379{ 380 struct circ_buf *xmit = &up->port.state->xmit; 381 int count; 382 383 if (up->port.x_char) { 384 serial_outp(up, UART_TX, up->port.x_char); 385 up->port.icount.tx++; 386 up->port.x_char = 0; 387 return; 388 } 389 if (uart_tx_stopped(&up->port)) { 390 sunsu_stop_tx(&up->port); 391 return; 392 } 393 if (uart_circ_empty(xmit)) { 394 __stop_tx(up); 395 return; 396 } 397 398 count = up->port.fifosize; 399 do { 400 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 401 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 402 up->port.icount.tx++; 403 if (uart_circ_empty(xmit)) 404 break; 405 } while (--count > 0); 406 407 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 408 uart_write_wakeup(&up->port); 409 410 if (uart_circ_empty(xmit)) 411 __stop_tx(up); 412} 413 414static void check_modem_status(struct uart_sunsu_port *up) 415{ 416 int status; 417 418 status = serial_in(up, UART_MSR); 419 420 if ((status & UART_MSR_ANY_DELTA) == 0) 421 return; 422 423 if (status & UART_MSR_TERI) 424 up->port.icount.rng++; 425 if (status & UART_MSR_DDSR) 426 up->port.icount.dsr++; 427 if (status & UART_MSR_DDCD) 428 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); 429 if (status & UART_MSR_DCTS) 430 uart_handle_cts_change(&up->port, status & UART_MSR_CTS); 431 432 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 433} 434 435static irqreturn_t sunsu_serial_interrupt(int irq, void *dev_id) 436{ 437 struct uart_sunsu_port *up = dev_id; 438 unsigned long flags; 439 unsigned char status; 440 441 spin_lock_irqsave(&up->port.lock, flags); 442 443 do { 444 struct tty_struct *tty; 445 446 status = serial_inp(up, UART_LSR); 447 tty = NULL; 448 if (status & UART_LSR_DR) 449 tty = receive_chars(up, &status); 450 check_modem_status(up); 451 if (status & UART_LSR_THRE) 452 transmit_chars(up); 453 454 spin_unlock_irqrestore(&up->port.lock, flags); 455 456 if (tty) 457 tty_flip_buffer_push(tty); 458 459 spin_lock_irqsave(&up->port.lock, flags); 460 461 } while (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)); 462 463 spin_unlock_irqrestore(&up->port.lock, flags); 464 465 return IRQ_HANDLED; 466} 467 468/* Separate interrupt handling path for keyboard/mouse ports. */ 469 470static void 471sunsu_change_speed(struct uart_port *port, unsigned int cflag, 472 unsigned int iflag, unsigned int quot); 473 474static void sunsu_change_mouse_baud(struct uart_sunsu_port *up) 475{ 476 unsigned int cur_cflag = up->cflag; 477 int quot, new_baud; 478 479 up->cflag &= ~CBAUD; 480 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud); 481 482 quot = up->port.uartclk / (16 * new_baud); 483 484 sunsu_change_speed(&up->port, up->cflag, 0, quot); 485} 486 487static void receive_kbd_ms_chars(struct uart_sunsu_port *up, int is_break) 488{ 489 do { 490 unsigned char ch = serial_inp(up, UART_RX); 491 492 /* Stop-A is handled by drivers/char/keyboard.c now. */ 493 if (up->su_type == SU_PORT_KBD) { 494#ifdef CONFIG_SERIO 495 serio_interrupt(&up->serio, ch, 0); 496#endif 497 } else if (up->su_type == SU_PORT_MS) { 498 int ret = suncore_mouse_baud_detection(ch, is_break); 499 500 switch (ret) { 501 case 2: 502 sunsu_change_mouse_baud(up); 503 /* fallthru */ 504 case 1: 505 break; 506 507 case 0: 508#ifdef CONFIG_SERIO 509 serio_interrupt(&up->serio, ch, 0); 510#endif 511 break; 512 }; 513 } 514 } while (serial_in(up, UART_LSR) & UART_LSR_DR); 515} 516 517static irqreturn_t sunsu_kbd_ms_interrupt(int irq, void *dev_id) 518{ 519 struct uart_sunsu_port *up = dev_id; 520 521 if (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)) { 522 unsigned char status = serial_inp(up, UART_LSR); 523 524 if ((status & UART_LSR_DR) || (status & UART_LSR_BI)) 525 receive_kbd_ms_chars(up, (status & UART_LSR_BI) != 0); 526 } 527 528 return IRQ_HANDLED; 529} 530 531static unsigned int sunsu_tx_empty(struct uart_port *port) 532{ 533 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; 534 unsigned long flags; 535 unsigned int ret; 536 537 spin_lock_irqsave(&up->port.lock, flags); 538 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 539 spin_unlock_irqrestore(&up->port.lock, flags); 540 541 return ret; 542} 543 544static unsigned int sunsu_get_mctrl(struct uart_port *port) 545{ 546 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; 547 unsigned char status; 548 unsigned int ret; 549 550 status = serial_in(up, UART_MSR); 551 552 ret = 0; 553 if (status & UART_MSR_DCD) 554 ret |= TIOCM_CAR; 555 if (status & UART_MSR_RI) 556 ret |= TIOCM_RNG; 557 if (status & UART_MSR_DSR) 558 ret |= TIOCM_DSR; 559 if (status & UART_MSR_CTS) 560 ret |= TIOCM_CTS; 561 return ret; 562} 563 564static void sunsu_set_mctrl(struct uart_port *port, unsigned int mctrl) 565{ 566 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; 567 unsigned char mcr = 0; 568 569 if (mctrl & TIOCM_RTS) 570 mcr |= UART_MCR_RTS; 571 if (mctrl & TIOCM_DTR) 572 mcr |= UART_MCR_DTR; 573 if (mctrl & TIOCM_OUT1) 574 mcr |= UART_MCR_OUT1; 575 if (mctrl & TIOCM_OUT2) 576 mcr |= UART_MCR_OUT2; 577 if (mctrl & TIOCM_LOOP) 578 mcr |= UART_MCR_LOOP; 579 580 serial_out(up, UART_MCR, mcr); 581} 582 583static void sunsu_break_ctl(struct uart_port *port, int break_state) 584{ 585 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; 586 unsigned long flags; 587 588 spin_lock_irqsave(&up->port.lock, flags); 589 if (break_state == -1) 590 up->lcr |= UART_LCR_SBC; 591 else 592 up->lcr &= ~UART_LCR_SBC; 593 serial_out(up, UART_LCR, up->lcr); 594 spin_unlock_irqrestore(&up->port.lock, flags); 595} 596 597static int sunsu_startup(struct uart_port *port) 598{ 599 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; 600 unsigned long flags; 601 int retval; 602 603 if (up->port.type == PORT_16C950) { 604 /* Wake up and initialize UART */ 605 up->acr = 0; 606 serial_outp(up, UART_LCR, 0xBF); 607 serial_outp(up, UART_EFR, UART_EFR_ECB); 608 serial_outp(up, UART_IER, 0); 609 serial_outp(up, UART_LCR, 0); 610 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ 611 serial_outp(up, UART_LCR, 0xBF); 612 serial_outp(up, UART_EFR, UART_EFR_ECB); 613 serial_outp(up, UART_LCR, 0); 614 } 615 616#ifdef CONFIG_SERIAL_8250_RSA 617 /* 618 * If this is an RSA port, see if we can kick it up to the 619 * higher speed clock. 620 */ 621 enable_rsa(up); 622#endif 623 624 /* 625 * Clear the FIFO buffers and disable them. 626 * (they will be reenabled in set_termios()) 627 */ 628 if (uart_config[up->port.type].flags & UART_CLEAR_FIFO) { 629 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 630 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | 631 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 632 serial_outp(up, UART_FCR, 0); 633 } 634 635 /* 636 * Clear the interrupt registers. 637 */ 638 (void) serial_inp(up, UART_LSR); 639 (void) serial_inp(up, UART_RX); 640 (void) serial_inp(up, UART_IIR); 641 (void) serial_inp(up, UART_MSR); 642 643 /* 644 * At this point, there's no way the LSR could still be 0xff; 645 * if it is, then bail out, because there's likely no UART 646 * here. 647 */ 648 if (!(up->port.flags & UPF_BUGGY_UART) && 649 (serial_inp(up, UART_LSR) == 0xff)) { 650 printk("ttyS%d: LSR safety check engaged!\n", up->port.line); 651 return -ENODEV; 652 } 653 654 if (up->su_type != SU_PORT_PORT) { 655 retval = request_irq(up->port.irq, sunsu_kbd_ms_interrupt, 656 IRQF_SHARED, su_typev[up->su_type], up); 657 } else { 658 retval = request_irq(up->port.irq, sunsu_serial_interrupt, 659 IRQF_SHARED, su_typev[up->su_type], up); 660 } 661 if (retval) { 662 printk("su: Cannot register IRQ %d\n", up->port.irq); 663 return retval; 664 } 665 666 /* 667 * Now, initialize the UART 668 */ 669 serial_outp(up, UART_LCR, UART_LCR_WLEN8); 670 671 spin_lock_irqsave(&up->port.lock, flags); 672 673 up->port.mctrl |= TIOCM_OUT2; 674 675 sunsu_set_mctrl(&up->port, up->port.mctrl); 676 spin_unlock_irqrestore(&up->port.lock, flags); 677 678 /* 679 * Finally, enable interrupts. Note: Modem status interrupts 680 * are set via set_termios(), which will be occurring imminently 681 * anyway, so we don't enable them here. 682 */ 683 up->ier = UART_IER_RLSI | UART_IER_RDI; 684 serial_outp(up, UART_IER, up->ier); 685 686 if (up->port.flags & UPF_FOURPORT) { 687 unsigned int icp; 688 /* 689 * Enable interrupts on the AST Fourport board 690 */ 691 icp = (up->port.iobase & 0xfe0) | 0x01f; 692 outb_p(0x80, icp); 693 (void) inb_p(icp); 694 } 695 696 /* 697 * And clear the interrupt registers again for luck. 698 */ 699 (void) serial_inp(up, UART_LSR); 700 (void) serial_inp(up, UART_RX); 701 (void) serial_inp(up, UART_IIR); 702 (void) serial_inp(up, UART_MSR); 703 704 return 0; 705} 706 707static void sunsu_shutdown(struct uart_port *port) 708{ 709 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; 710 unsigned long flags; 711 712 /* 713 * Disable interrupts from this port 714 */ 715 up->ier = 0; 716 serial_outp(up, UART_IER, 0); 717 718 spin_lock_irqsave(&up->port.lock, flags); 719 if (up->port.flags & UPF_FOURPORT) { 720 /* reset interrupts on the AST Fourport board */ 721 inb((up->port.iobase & 0xfe0) | 0x1f); 722 up->port.mctrl |= TIOCM_OUT1; 723 } else 724 up->port.mctrl &= ~TIOCM_OUT2; 725 726 sunsu_set_mctrl(&up->port, up->port.mctrl); 727 spin_unlock_irqrestore(&up->port.lock, flags); 728 729 /* 730 * Disable break condition and FIFOs 731 */ 732 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC); 733 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | 734 UART_FCR_CLEAR_RCVR | 735 UART_FCR_CLEAR_XMIT); 736 serial_outp(up, UART_FCR, 0); 737 738#ifdef CONFIG_SERIAL_8250_RSA 739 /* 740 * Reset the RSA board back to 115kbps compat mode. 741 */ 742 disable_rsa(up); 743#endif 744 745 /* 746 * Read data port to reset things. 747 */ 748 (void) serial_in(up, UART_RX); 749 750 free_irq(up->port.irq, up); 751} 752 753static void 754sunsu_change_speed(struct uart_port *port, unsigned int cflag, 755 unsigned int iflag, unsigned int quot) 756{ 757 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; 758 unsigned char cval, fcr = 0; 759 unsigned long flags; 760 761 switch (cflag & CSIZE) { 762 case CS5: 763 cval = 0x00; 764 break; 765 case CS6: 766 cval = 0x01; 767 break; 768 case CS7: 769 cval = 0x02; 770 break; 771 default: 772 case CS8: 773 cval = 0x03; 774 break; 775 } 776 777 if (cflag & CSTOPB) 778 cval |= 0x04; 779 if (cflag & PARENB) 780 cval |= UART_LCR_PARITY; 781 if (!(cflag & PARODD)) 782 cval |= UART_LCR_EPAR; 783#ifdef CMSPAR 784 if (cflag & CMSPAR) 785 cval |= UART_LCR_SPAR; 786#endif 787 788 if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 && 789 up->rev == 0x5201) 790 quot ++; 791 792 if (uart_config[up->port.type].flags & UART_USE_FIFO) { 793 if ((up->port.uartclk / quot) < (2400 * 16)) 794 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; 795#ifdef CONFIG_SERIAL_8250_RSA 796 else if (up->port.type == PORT_RSA) 797 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14; 798#endif 799 else 800 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8; 801 } 802 if (up->port.type == PORT_16750) 803 fcr |= UART_FCR7_64BYTE; 804 805 /* 806 * Ok, we're now changing the port state. Do it with 807 * interrupts disabled. 808 */ 809 spin_lock_irqsave(&up->port.lock, flags); 810 811 /* 812 * Update the per-port timeout. 813 */ 814 uart_update_timeout(port, cflag, (port->uartclk / (16 * quot))); 815 816 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 817 if (iflag & INPCK) 818 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 819 if (iflag & (BRKINT | PARMRK)) 820 up->port.read_status_mask |= UART_LSR_BI; 821 822 /* 823 * Characteres to ignore 824 */ 825 up->port.ignore_status_mask = 0; 826 if (iflag & IGNPAR) 827 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 828 if (iflag & IGNBRK) { 829 up->port.ignore_status_mask |= UART_LSR_BI; 830 /* 831 * If we're ignoring parity and break indicators, 832 * ignore overruns too (for real raw support). 833 */ 834 if (iflag & IGNPAR) 835 up->port.ignore_status_mask |= UART_LSR_OE; 836 } 837 838 /* 839 * ignore all characters if CREAD is not set 840 */ 841 if ((cflag & CREAD) == 0) 842 up->port.ignore_status_mask |= UART_LSR_DR; 843 844 /* 845 * CTS flow control flag and modem status interrupts 846 */ 847 up->ier &= ~UART_IER_MSI; 848 if (UART_ENABLE_MS(&up->port, cflag)) 849 up->ier |= UART_IER_MSI; 850 851 serial_out(up, UART_IER, up->ier); 852 853 if (uart_config[up->port.type].flags & UART_STARTECH) { 854 serial_outp(up, UART_LCR, 0xBF); 855 serial_outp(up, UART_EFR, cflag & CRTSCTS ? UART_EFR_CTS :0); 856 } 857 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ 858 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */ 859 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */ 860 if (up->port.type == PORT_16750) 861 serial_outp(up, UART_FCR, fcr); /* set fcr */ 862 serial_outp(up, UART_LCR, cval); /* reset DLAB */ 863 up->lcr = cval; /* Save LCR */ 864 if (up->port.type != PORT_16750) { 865 if (fcr & UART_FCR_ENABLE_FIFO) { 866 /* emulated UARTs (Lucent Venus 167x) need two steps */ 867 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 868 } 869 serial_outp(up, UART_FCR, fcr); /* set fcr */ 870 } 871 872 up->cflag = cflag; 873 874 spin_unlock_irqrestore(&up->port.lock, flags); 875} 876 877static void 878sunsu_set_termios(struct uart_port *port, struct ktermios *termios, 879 struct ktermios *old) 880{ 881 unsigned int baud, quot; 882 883 /* 884 * Ask the core to calculate the divisor for us. 885 */ 886 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 887 quot = uart_get_divisor(port, baud); 888 889 sunsu_change_speed(port, termios->c_cflag, termios->c_iflag, quot); 890} 891 892static void sunsu_release_port(struct uart_port *port) 893{ 894} 895 896static int sunsu_request_port(struct uart_port *port) 897{ 898 return 0; 899} 900 901static void sunsu_config_port(struct uart_port *port, int flags) 902{ 903 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; 904 905 if (flags & UART_CONFIG_TYPE) { 906 /* 907 * We are supposed to call autoconfig here, but this requires 908 * splitting all the OBP probing crap from the UART probing. 909 * We'll do it when we kill sunsu.c altogether. 910 */ 911 port->type = up->type_probed; 912 } 913} 914 915static int 916sunsu_verify_port(struct uart_port *port, struct serial_struct *ser) 917{ 918 return -EINVAL; 919} 920 921static const char * 922sunsu_type(struct uart_port *port) 923{ 924 int type = port->type; 925 926 if (type >= ARRAY_SIZE(uart_config)) 927 type = 0; 928 return uart_config[type].name; 929} 930 931static struct uart_ops sunsu_pops = { 932 .tx_empty = sunsu_tx_empty, 933 .set_mctrl = sunsu_set_mctrl, 934 .get_mctrl = sunsu_get_mctrl, 935 .stop_tx = sunsu_stop_tx, 936 .start_tx = sunsu_start_tx, 937 .stop_rx = sunsu_stop_rx, 938 .enable_ms = sunsu_enable_ms, 939 .break_ctl = sunsu_break_ctl, 940 .startup = sunsu_startup, 941 .shutdown = sunsu_shutdown, 942 .set_termios = sunsu_set_termios, 943 .type = sunsu_type, 944 .release_port = sunsu_release_port, 945 .request_port = sunsu_request_port, 946 .config_port = sunsu_config_port, 947 .verify_port = sunsu_verify_port, 948}; 949 950#define UART_NR 4 951 952static struct uart_sunsu_port sunsu_ports[UART_NR]; 953 954#ifdef CONFIG_SERIO 955 956static DEFINE_SPINLOCK(sunsu_serio_lock); 957 958static int sunsu_serio_write(struct serio *serio, unsigned char ch) 959{ 960 struct uart_sunsu_port *up = serio->port_data; 961 unsigned long flags; 962 int lsr; 963 964 spin_lock_irqsave(&sunsu_serio_lock, flags); 965 966 do { 967 lsr = serial_in(up, UART_LSR); 968 } while (!(lsr & UART_LSR_THRE)); 969 970 /* Send the character out. */ 971 serial_out(up, UART_TX, ch); 972 973 spin_unlock_irqrestore(&sunsu_serio_lock, flags); 974 975 return 0; 976} 977 978static int sunsu_serio_open(struct serio *serio) 979{ 980 struct uart_sunsu_port *up = serio->port_data; 981 unsigned long flags; 982 int ret; 983 984 spin_lock_irqsave(&sunsu_serio_lock, flags); 985 if (!up->serio_open) { 986 up->serio_open = 1; 987 ret = 0; 988 } else 989 ret = -EBUSY; 990 spin_unlock_irqrestore(&sunsu_serio_lock, flags); 991 992 return ret; 993} 994 995static void sunsu_serio_close(struct serio *serio) 996{ 997 struct uart_sunsu_port *up = serio->port_data; 998 unsigned long flags; 999 1000 spin_lock_irqsave(&sunsu_serio_lock, flags); 1001 up->serio_open = 0; 1002 spin_unlock_irqrestore(&sunsu_serio_lock, flags); 1003} 1004 1005#endif /* CONFIG_SERIO */ 1006 1007static void sunsu_autoconfig(struct uart_sunsu_port *up) 1008{ 1009 unsigned char status1, status2, scratch, scratch2, scratch3; 1010 unsigned char save_lcr, save_mcr; 1011 unsigned long flags; 1012 1013 if (up->su_type == SU_PORT_NONE) 1014 return; 1015 1016 up->type_probed = PORT_UNKNOWN; 1017 up->port.iotype = UPIO_MEM; 1018 1019 spin_lock_irqsave(&up->port.lock, flags); 1020 1021 if (!(up->port.flags & UPF_BUGGY_UART)) { 1022 /* 1023 * Do a simple existence test first; if we fail this, there's 1024 * no point trying anything else. 1025 * 1026 * 0x80 is used as a nonsense port to prevent against false 1027 * positives due to ISA bus float. The assumption is that 1028 * 0x80 is a non-existent port; which should be safe since 1029 * include/asm/io.h also makes this assumption. 1030 */ 1031 scratch = serial_inp(up, UART_IER); 1032 serial_outp(up, UART_IER, 0); 1033#ifdef __i386__ 1034 outb(0xff, 0x080); 1035#endif 1036 scratch2 = serial_inp(up, UART_IER); 1037 serial_outp(up, UART_IER, 0x0f); 1038#ifdef __i386__ 1039 outb(0, 0x080); 1040#endif 1041 scratch3 = serial_inp(up, UART_IER); 1042 serial_outp(up, UART_IER, scratch); 1043 if (scratch2 != 0 || scratch3 != 0x0F) 1044 goto out; /* We failed; there's nothing here */ 1045 } 1046 1047 save_mcr = serial_in(up, UART_MCR); 1048 save_lcr = serial_in(up, UART_LCR); 1049 1050 /* 1051 * Check to see if a UART is really there. Certain broken 1052 * internal modems based on the Rockwell chipset fail this 1053 * test, because they apparently don't implement the loopback 1054 * test mode. So this test is skipped on the COM 1 through 1055 * COM 4 ports. This *should* be safe, since no board 1056 * manufacturer would be stupid enough to design a board 1057 * that conflicts with COM 1-4 --- we hope! 1058 */ 1059 if (!(up->port.flags & UPF_SKIP_TEST)) { 1060 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A); 1061 status1 = serial_inp(up, UART_MSR) & 0xF0; 1062 serial_outp(up, UART_MCR, save_mcr); 1063 if (status1 != 0x90) 1064 goto out; /* We failed loopback test */ 1065 } 1066 serial_outp(up, UART_LCR, 0xBF); /* set up for StarTech test */ 1067 serial_outp(up, UART_EFR, 0); /* EFR is the same as FCR */ 1068 serial_outp(up, UART_LCR, 0); 1069 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1070 scratch = serial_in(up, UART_IIR) >> 6; 1071 switch (scratch) { 1072 case 0: 1073 up->port.type = PORT_16450; 1074 break; 1075 case 1: 1076 up->port.type = PORT_UNKNOWN; 1077 break; 1078 case 2: 1079 up->port.type = PORT_16550; 1080 break; 1081 case 3: 1082 up->port.type = PORT_16550A; 1083 break; 1084 } 1085 if (up->port.type == PORT_16550A) { 1086 /* Check for Startech UART's */ 1087 serial_outp(up, UART_LCR, UART_LCR_DLAB); 1088 if (serial_in(up, UART_EFR) == 0) { 1089 up->port.type = PORT_16650; 1090 } else { 1091 serial_outp(up, UART_LCR, 0xBF); 1092 if (serial_in(up, UART_EFR) == 0) 1093 up->port.type = PORT_16650V2; 1094 } 1095 } 1096 if (up->port.type == PORT_16550A) { 1097 /* Check for TI 16750 */ 1098 serial_outp(up, UART_LCR, save_lcr | UART_LCR_DLAB); 1099 serial_outp(up, UART_FCR, 1100 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 1101 scratch = serial_in(up, UART_IIR) >> 5; 1102 if (scratch == 7) { 1103 /* 1104 * If this is a 16750, and not a cheap UART 1105 * clone, then it should only go into 64 byte 1106 * mode if the UART_FCR7_64BYTE bit was set 1107 * while UART_LCR_DLAB was latched. 1108 */ 1109 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1110 serial_outp(up, UART_LCR, 0); 1111 serial_outp(up, UART_FCR, 1112 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 1113 scratch = serial_in(up, UART_IIR) >> 5; 1114 if (scratch == 6) 1115 up->port.type = PORT_16750; 1116 } 1117 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1118 } 1119 serial_outp(up, UART_LCR, save_lcr); 1120 if (up->port.type == PORT_16450) { 1121 scratch = serial_in(up, UART_SCR); 1122 serial_outp(up, UART_SCR, 0xa5); 1123 status1 = serial_in(up, UART_SCR); 1124 serial_outp(up, UART_SCR, 0x5a); 1125 status2 = serial_in(up, UART_SCR); 1126 serial_outp(up, UART_SCR, scratch); 1127 1128 if ((status1 != 0xa5) || (status2 != 0x5a)) 1129 up->port.type = PORT_8250; 1130 } 1131 1132 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size; 1133 1134 if (up->port.type == PORT_UNKNOWN) 1135 goto out; 1136 up->type_probed = up->port.type; 1137 1138 /* 1139 * Reset the UART. 1140 */ 1141#ifdef CONFIG_SERIAL_8250_RSA 1142 if (up->port.type == PORT_RSA) 1143 serial_outp(up, UART_RSA_FRR, 0); 1144#endif 1145 serial_outp(up, UART_MCR, save_mcr); 1146 serial_outp(up, UART_FCR, (UART_FCR_ENABLE_FIFO | 1147 UART_FCR_CLEAR_RCVR | 1148 UART_FCR_CLEAR_XMIT)); 1149 serial_outp(up, UART_FCR, 0); 1150 (void)serial_in(up, UART_RX); 1151 serial_outp(up, UART_IER, 0); 1152 1153out: 1154 spin_unlock_irqrestore(&up->port.lock, flags); 1155} 1156 1157static struct uart_driver sunsu_reg = { 1158 .owner = THIS_MODULE, 1159 .driver_name = "sunsu", 1160 .dev_name = "ttyS", 1161 .major = TTY_MAJOR, 1162}; 1163 1164static int __devinit sunsu_kbd_ms_init(struct uart_sunsu_port *up) 1165{ 1166 int quot, baud; 1167#ifdef CONFIG_SERIO 1168 struct serio *serio; 1169#endif 1170 1171 if (up->su_type == SU_PORT_KBD) { 1172 up->cflag = B1200 | CS8 | CLOCAL | CREAD; 1173 baud = 1200; 1174 } else { 1175 up->cflag = B4800 | CS8 | CLOCAL | CREAD; 1176 baud = 4800; 1177 } 1178 quot = up->port.uartclk / (16 * baud); 1179 1180 sunsu_autoconfig(up); 1181 if (up->port.type == PORT_UNKNOWN) 1182 return -ENODEV; 1183 1184 printk("%s: %s port at %llx, irq %u\n", 1185 up->port.dev->of_node->full_name, 1186 (up->su_type == SU_PORT_KBD) ? "Keyboard" : "Mouse", 1187 (unsigned long long) up->port.mapbase, 1188 up->port.irq); 1189 1190#ifdef CONFIG_SERIO 1191 serio = &up->serio; 1192 serio->port_data = up; 1193 1194 serio->id.type = SERIO_RS232; 1195 if (up->su_type == SU_PORT_KBD) { 1196 serio->id.proto = SERIO_SUNKBD; 1197 strlcpy(serio->name, "sukbd", sizeof(serio->name)); 1198 } else { 1199 serio->id.proto = SERIO_SUN; 1200 serio->id.extra = 1; 1201 strlcpy(serio->name, "sums", sizeof(serio->name)); 1202 } 1203 strlcpy(serio->phys, 1204 (!(up->port.line & 1) ? "su/serio0" : "su/serio1"), 1205 sizeof(serio->phys)); 1206 1207 serio->write = sunsu_serio_write; 1208 serio->open = sunsu_serio_open; 1209 serio->close = sunsu_serio_close; 1210 serio->dev.parent = up->port.dev; 1211 1212 serio_register_port(serio); 1213#endif 1214 1215 sunsu_change_speed(&up->port, up->cflag, 0, quot); 1216 1217 sunsu_startup(&up->port); 1218 return 0; 1219} 1220 1221/* 1222 * ------------------------------------------------------------ 1223 * Serial console driver 1224 * ------------------------------------------------------------ 1225 */ 1226 1227#ifdef CONFIG_SERIAL_SUNSU_CONSOLE 1228 1229#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 1230 1231/* 1232 * Wait for transmitter & holding register to empty 1233 */ 1234static __inline__ void wait_for_xmitr(struct uart_sunsu_port *up) 1235{ 1236 unsigned int status, tmout = 10000; 1237 1238 /* Wait up to 10ms for the character(s) to be sent. */ 1239 do { 1240 status = serial_in(up, UART_LSR); 1241 1242 if (status & UART_LSR_BI) 1243 up->lsr_break_flag = UART_LSR_BI; 1244 1245 if (--tmout == 0) 1246 break; 1247 udelay(1); 1248 } while ((status & BOTH_EMPTY) != BOTH_EMPTY); 1249 1250 /* Wait up to 1s for flow control if necessary */ 1251 if (up->port.flags & UPF_CONS_FLOW) { 1252 tmout = 1000000; 1253 while (--tmout && 1254 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) 1255 udelay(1); 1256 } 1257} 1258 1259static void sunsu_console_putchar(struct uart_port *port, int ch) 1260{ 1261 struct uart_sunsu_port *up = (struct uart_sunsu_port *)port; 1262 1263 wait_for_xmitr(up); 1264 serial_out(up, UART_TX, ch); 1265} 1266 1267/* 1268 * Print a string to the serial port trying not to disturb 1269 * any possible real use of the port... 1270 */ 1271static void sunsu_console_write(struct console *co, const char *s, 1272 unsigned int count) 1273{ 1274 struct uart_sunsu_port *up = &sunsu_ports[co->index]; 1275 unsigned long flags; 1276 unsigned int ier; 1277 int locked = 1; 1278 1279 local_irq_save(flags); 1280 if (up->port.sysrq) { 1281 locked = 0; 1282 } else if (oops_in_progress) { 1283 locked = spin_trylock(&up->port.lock); 1284 } else 1285 spin_lock(&up->port.lock); 1286 1287 /* 1288 * First save the UER then disable the interrupts 1289 */ 1290 ier = serial_in(up, UART_IER); 1291 serial_out(up, UART_IER, 0); 1292 1293 uart_console_write(&up->port, s, count, sunsu_console_putchar); 1294 1295 /* 1296 * Finally, wait for transmitter to become empty 1297 * and restore the IER 1298 */ 1299 wait_for_xmitr(up); 1300 serial_out(up, UART_IER, ier); 1301 1302 if (locked) 1303 spin_unlock(&up->port.lock); 1304 local_irq_restore(flags); 1305} 1306 1307/* 1308 * Setup initial baud/bits/parity. We do two things here: 1309 * - construct a cflag setting for the first su_open() 1310 * - initialize the serial port 1311 * Return non-zero if we didn't find a serial port. 1312 */ 1313static int __init sunsu_console_setup(struct console *co, char *options) 1314{ 1315 static struct ktermios dummy; 1316 struct ktermios termios; 1317 struct uart_port *port; 1318 1319 printk("Console: ttyS%d (SU)\n", 1320 (sunsu_reg.minor - 64) + co->index); 1321 1322 /* 1323 * Check whether an invalid uart number has been specified, and 1324 * if so, search for the first available port that does have 1325 * console support. 1326 */ 1327 if (co->index >= UART_NR) 1328 co->index = 0; 1329 port = &sunsu_ports[co->index].port; 1330 1331 /* 1332 * Temporary fix. 1333 */ 1334 spin_lock_init(&port->lock); 1335 1336 /* Get firmware console settings. */ 1337 sunserial_console_termios(co, port->dev->of_node); 1338 1339 memset(&termios, 0, sizeof(struct ktermios)); 1340 termios.c_cflag = co->cflag; 1341 port->mctrl |= TIOCM_DTR; 1342 port->ops->set_termios(port, &termios, &dummy); 1343 1344 return 0; 1345} 1346 1347static struct console sunsu_console = { 1348 .name = "ttyS", 1349 .write = sunsu_console_write, 1350 .device = uart_console_device, 1351 .setup = sunsu_console_setup, 1352 .flags = CON_PRINTBUFFER, 1353 .index = -1, 1354 .data = &sunsu_reg, 1355}; 1356 1357/* 1358 * Register console. 1359 */ 1360 1361static inline struct console *SUNSU_CONSOLE(void) 1362{ 1363 return &sunsu_console; 1364} 1365#else 1366#define SUNSU_CONSOLE() (NULL) 1367#define sunsu_serial_console_init() do { } while (0) 1368#endif 1369 1370static enum su_type __devinit su_get_type(struct device_node *dp) 1371{ 1372 struct device_node *ap = of_find_node_by_path("/aliases"); 1373 1374 if (ap) { 1375 const char *keyb = of_get_property(ap, "keyboard", NULL); 1376 const char *ms = of_get_property(ap, "mouse", NULL); 1377 1378 if (keyb) { 1379 if (dp == of_find_node_by_path(keyb)) 1380 return SU_PORT_KBD; 1381 } 1382 if (ms) { 1383 if (dp == of_find_node_by_path(ms)) 1384 return SU_PORT_MS; 1385 } 1386 } 1387 1388 return SU_PORT_PORT; 1389} 1390 1391static int __devinit su_probe(struct platform_device *op, const struct of_device_id *match) 1392{ 1393 static int inst; 1394 struct device_node *dp = op->dev.of_node; 1395 struct uart_sunsu_port *up; 1396 struct resource *rp; 1397 enum su_type type; 1398 bool ignore_line; 1399 int err; 1400 1401 type = su_get_type(dp); 1402 if (type == SU_PORT_PORT) { 1403 if (inst >= UART_NR) 1404 return -EINVAL; 1405 up = &sunsu_ports[inst]; 1406 } else { 1407 up = kzalloc(sizeof(*up), GFP_KERNEL); 1408 if (!up) 1409 return -ENOMEM; 1410 } 1411 1412 up->port.line = inst; 1413 1414 spin_lock_init(&up->port.lock); 1415 1416 up->su_type = type; 1417 1418 rp = &op->resource[0]; 1419 up->port.mapbase = rp->start; 1420 up->reg_size = (rp->end - rp->start) + 1; 1421 up->port.membase = of_ioremap(rp, 0, up->reg_size, "su"); 1422 if (!up->port.membase) { 1423 if (type != SU_PORT_PORT) 1424 kfree(up); 1425 return -ENOMEM; 1426 } 1427 1428 up->port.irq = op->archdata.irqs[0]; 1429 1430 up->port.dev = &op->dev; 1431 1432 up->port.type = PORT_UNKNOWN; 1433 up->port.uartclk = (SU_BASE_BAUD * 16); 1434 1435 err = 0; 1436 if (up->su_type == SU_PORT_KBD || up->su_type == SU_PORT_MS) { 1437 err = sunsu_kbd_ms_init(up); 1438 if (err) { 1439 of_iounmap(&op->resource[0], 1440 up->port.membase, up->reg_size); 1441 kfree(up); 1442 return err; 1443 } 1444 dev_set_drvdata(&op->dev, up); 1445 1446 return 0; 1447 } 1448 1449 up->port.flags |= UPF_BOOT_AUTOCONF; 1450 1451 sunsu_autoconfig(up); 1452 1453 err = -ENODEV; 1454 if (up->port.type == PORT_UNKNOWN) 1455 goto out_unmap; 1456 1457 up->port.ops = &sunsu_pops; 1458 1459 ignore_line = false; 1460 if (!strcmp(dp->name, "rsc-console") || 1461 !strcmp(dp->name, "lom-console")) 1462 ignore_line = true; 1463 1464 sunserial_console_match(SUNSU_CONSOLE(), dp, 1465 &sunsu_reg, up->port.line, 1466 ignore_line); 1467 err = uart_add_one_port(&sunsu_reg, &up->port); 1468 if (err) 1469 goto out_unmap; 1470 1471 dev_set_drvdata(&op->dev, up); 1472 1473 inst++; 1474 1475 return 0; 1476 1477out_unmap: 1478 of_iounmap(&op->resource[0], up->port.membase, up->reg_size); 1479 return err; 1480} 1481 1482static int __devexit su_remove(struct platform_device *op) 1483{ 1484 struct uart_sunsu_port *up = dev_get_drvdata(&op->dev); 1485 bool kbdms = false; 1486 1487 if (up->su_type == SU_PORT_MS || 1488 up->su_type == SU_PORT_KBD) 1489 kbdms = true; 1490 1491 if (kbdms) { 1492#ifdef CONFIG_SERIO 1493 serio_unregister_port(&up->serio); 1494#endif 1495 } else if (up->port.type != PORT_UNKNOWN) 1496 uart_remove_one_port(&sunsu_reg, &up->port); 1497 1498 if (up->port.membase) 1499 of_iounmap(&op->resource[0], up->port.membase, up->reg_size); 1500 1501 if (kbdms) 1502 kfree(up); 1503 1504 dev_set_drvdata(&op->dev, NULL); 1505 1506 return 0; 1507} 1508 1509static const struct of_device_id su_match[] = { 1510 { 1511 .name = "su", 1512 }, 1513 { 1514 .name = "su_pnp", 1515 }, 1516 { 1517 .name = "serial", 1518 .compatible = "su", 1519 }, 1520 { 1521 .type = "serial", 1522 .compatible = "su", 1523 }, 1524 {}, 1525}; 1526MODULE_DEVICE_TABLE(of, su_match); 1527 1528static struct of_platform_driver su_driver = { 1529 .driver = { 1530 .name = "su", 1531 .owner = THIS_MODULE, 1532 .of_match_table = su_match, 1533 }, 1534 .probe = su_probe, 1535 .remove = __devexit_p(su_remove), 1536}; 1537 1538static int __init sunsu_init(void) 1539{ 1540 struct device_node *dp; 1541 int err; 1542 int num_uart = 0; 1543 1544 for_each_node_by_name(dp, "su") { 1545 if (su_get_type(dp) == SU_PORT_PORT) 1546 num_uart++; 1547 } 1548 for_each_node_by_name(dp, "su_pnp") { 1549 if (su_get_type(dp) == SU_PORT_PORT) 1550 num_uart++; 1551 } 1552 for_each_node_by_name(dp, "serial") { 1553 if (of_device_is_compatible(dp, "su")) { 1554 if (su_get_type(dp) == SU_PORT_PORT) 1555 num_uart++; 1556 } 1557 } 1558 for_each_node_by_type(dp, "serial") { 1559 if (of_device_is_compatible(dp, "su")) { 1560 if (su_get_type(dp) == SU_PORT_PORT) 1561 num_uart++; 1562 } 1563 } 1564 1565 if (num_uart) { 1566 err = sunserial_register_minors(&sunsu_reg, num_uart); 1567 if (err) 1568 return err; 1569 } 1570 1571 err = of_register_platform_driver(&su_driver); 1572 if (err && num_uart) 1573 sunserial_unregister_minors(&sunsu_reg, num_uart); 1574 1575 return err; 1576} 1577 1578static void __exit sunsu_exit(void) 1579{ 1580 if (sunsu_reg.nr) 1581 sunserial_unregister_minors(&sunsu_reg, sunsu_reg.nr); 1582} 1583 1584module_init(sunsu_init); 1585module_exit(sunsu_exit); 1586 1587MODULE_AUTHOR("Eddie C. Dost, Peter Zaitcev, and David S. Miller"); 1588MODULE_DESCRIPTION("Sun SU serial port driver"); 1589MODULE_VERSION("2.0"); 1590MODULE_LICENSE("GPL"); 1591